CN102520906A - Vector dot product accumulating network supporting reconfigurable fixed floating point and configurable vector length - Google Patents

Abstract

The invention discloses a vector dot product accumulating network supporting reconfigurable fixed floating point and configurable vector length, comprising a parallel reconfigurable multiplying unit for receiving vectors B, C, FBS and U as input, and performing vector multiplying operation to obtain multiplying result B*C of the vectors B and C; a floating point index and mantissa pre-processing part for receiving multiplying result B*C of the parallel reconfigurable multiplying unit and scalar A as input, finishing operations of selecting maximum floating point index, subtracting the indexes, shifting and aligning, complementing bits and converting and sticky compensating to obtain processed vector result B*C and scalar result A; a reconfigurable compressor for receiving processing result of the floating point index and mantissa pre-processing part, and compressing the result to obtain a sum string S and a binary string C; and a floating point index and mantissa post-processing/fixed point operating part for receiving the sum string S and the binary string C of the reconfigurable compressor, and finishing mantissa addition and post-processing to obtain a final vector dot product accumulating result.

Description

Support fixed-floating-point reconfigurable vector point-accumulation-add network with configurable vector length

technical field

The invention relates to the technical field of high-performance digital signal processors, in particular to a vector point accumulation and addition network with configurable vector length supporting fixed-floating point reconfiguration.

Background technique

In the field of modern digital signal processing, digital signal processor (DSP) is the core of the whole system, and the performance of DSP directly determines the performance of the whole system. In DSP, no matter how complicated the calculation is, it must be implemented by the calculation unit, so the calculation unit is the core component of the entire DSP, and its computing power is the main indicator to measure the performance of the DSP. In particular, with the continuous development of technology, high computing-intensive fields represented by modern radar signal processing, satellite image processing, image compression, high-definition video, etc., have higher and higher signal processing capabilities. This poses increasingly higher challenges to the computing unit, especially the variable-size, high-density parallel computing for specific fields puts pressure on the computing unit is self-evident.

In modern digital signal processing, "dot product" operations are widely used, such as FFT, FIR filtering, signal correlation, etc. All these operations are to multiply the input signal with a coefficient or local parameter and then integrate (accumulate), which is expressed as a dot product of two vectors (or sequences). For the dot product operation, the current mainstream DSP does not have a dedicated instruction, and it is generally completed by multiplying, accumulating, or multiplying and accumulating multiple instructions. This technique generally has some disadvantages:

1) The hardware utilization rate is low. For the vector dot product operation, only scalar multiplication, accumulation or scalar multiplication and accumulation resources are used, and vector operation resources are not reasonably utilized.

2) The processing ability is weak. Generally, only 16/32-bit scalar dot product operations can be performed. For vector dot products, only multiple scalar dot product operations can be performed. The data throughput is low and the efficiency is low.

3) The execution cycle is long. A dot product operation requires multiple multiplication, accumulation or multiply-accumulate instructions to be completed serially, there is data correlation, and the dot product operation requires multiple clock cycles.

4) The flexibility is not high. It can only support a specific data format or a specific length of dot product operation, and the number of data involved in the dot product operation is not configurable.

5) Programming is difficult. The dot product operation is completed by multiplication, accumulation or multiply-accumulate operations, and these operations are not single-cycle instructions, and the data correlation between each instruction needs to be considered.

The dot product operation belongs to the category of multi-operand calculation, and the multi-operand calculation needs to focus on analyzing the sign bit extension and data precision of the data. At present, some patents have discussed how to implement multi-operand operations. For example, the patent "A Reconfigurable Horizontal Summation Network Supporting Fixed-Floating Points" with application number 201010162375.X proposes a multi-operand addition operation, but its The precision of the floating point data format is not analyzed and the overall data length is not configurable. The patent application number 201010535666.9 "Instructions and Logic for Performing Dot Product Operations" proposes an idea for executing dot product instructions. The data format is configurable, but it is still a scalar dot product, and the data involved in the dot product operation The number is not configurable. Patent Application No. 201010559300.5 "Multifunction for SIMD Vector Microprocessor" introduces an idea of implementing a vector floating-point multiplication and addition unit, but it does not reconstruct fixed-point data and also participates in multiplication and addition operations. The number is not configurable.

Analyzing the dependence of the dot product operation at the arithmetic level, we can know that the dot product operation is completed by multiplication and accumulation operations; therefore, the idea of using scalar operation components to perform vector dot products in the traditional method is changed, and the existing vector multiplication resources are reused to increase Accumulating network resources and using vector operation components to perform vector dot product operations can fundamentally improve the capability of vector dot product operations. At the same time, analyze the correlation between floating-point data and fixed-point data format, preprocess floating-point data, and multiplex fixed-point data paths; support different data formats and different data granularities through reconfigurable compression technology; use Mask register configuration to participate The number of data of the dot product operation, thereby providing a kind of vector point accumulation network that supports different granularities, different data formats, and different vector lengths, to provide powerful vector dot product computing capabilities in digital signal processing, is the problem that the present invention needs to solve question.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to provide a vector point accumulation and addition network that supports fixed-floating point reconfigurability and configurable vector length, can support 8/16/32-bit fixed-point data, and 32-bit simplified IEEE-754 standard Single-precision floating-point data dot product operation can flexibly configure the length of the vector involved in the dot product operation, and rationally use vector operation resources to improve the efficiency and processing capacity of the vector dot product operation, simplify the programming complexity of the vector dot product operation software, and meet the needs of digital signals Handle the powerful vector dot product operation requirements.

(2) Technical solutions

In order to achieve the above object, the present invention provides a vector point accumulation network with configurable vector length that supports fixed-floating point reconfigurability, including: parallel reconfigurable multiplier 1, used to receive vector data B, C and data The options FBS and U are used as input to execute the vector multiplication operation, and the multiplication result B×C of the vector data B and C is obtained, and output to the floating-point exponent and mantissa preprocessing part 2; the floating-point exponent and mantissa preprocessing part 2 is used for Receive the multiplication result B×C and scalar data A of the parallel reconfigurable multiplier 1 as input, complete the operations of selecting the maximum value of the floating-point exponent, difference of the exponent, shift alignment, complement conversion and sticky bit compensation, and obtain the processed The vector result B×C and the scalar result A are output to the reconfigurable compressor part 3; the reconfigurable compressor part 3 is used to receive the processing results of the floating-point exponent and mantissa preprocessing part 2 and compress them , get "sum string" (S) and "carry string" (C), and output to floating-point exponent, mantissa post-processing/fixed-point operation part 4; and floating-point exponent, mantissa post-processing/fixed-point operation part 4 for Mantissa addition is performed on the "sum string" S and "carry string" C received from the reconfigurable compressor part 3, and the added mantissa result is post-processed to obtain the final vector point accumulation result.

(3) Beneficial effects

The vector point accumulation and addition network with configurable fixed-floating-point reconfigurable vector length provided by the present invention preprocesses floating-point data and multiplexes fixed-point data paths, and supports different data formats and formats through reconfigurable compression technology. Data granularity, use the Mask register to flexibly configure the length of the vector involved in the dot product operation, can support 8/16/32-bit fixed-point data, simplified IEEE-754 standard single-precision floating-point data vector dot product operation, can be flexibly configured to participate in the dot product The vector length of the operation has high operation performance, low overhead, many functions, less coding, and fast speed, which reduces the delay of the floating-point vector point accumulation and critical path, reduces the resources consumed by the fixed-point vector point accumulation, and simplifies the software. The complexity of programming increases the code density.

Description of drawings

FIG. 1 is a schematic structural diagram of a vector point accumulation and addition network that supports fixed-floating-point reconfigurable vector lengths and can be configured according to an embodiment of the present invention;

2 is a schematic diagram of an 8×8 multiplier configured as a 16×16 multiplier according to an embodiment of the present invention;

FIG. 3 is an array diagram of an 8×8-bit multiplier configured as a 16×16 multiplier according to an embodiment of the present invention;

Fig. 4 is a schematic diagram of the floating-point exponent and mantissa preprocessing part in the vector point accumulation network according to an embodiment of the present invention, and comparing three exponents at a time to obtain a larger floating-point exponent network;

5 is a schematic diagram of the floating-point exponent and mantissa preprocessing part in the vector point accumulation network according to an embodiment of the present invention, and the cascaded exponent comparator network obtaining the maximum floating-point exponent;

6 is a schematic diagram of floating-point exponent and mantissa preprocessing part and floating-point mantissa processing in the vector point accumulation network according to an embodiment of the present invention;

7 is a schematic diagram of the reconfigurable compressor part in the vector point accumulation network according to an embodiment of the present invention, 8/16/32-bit fixed-point, 32-bit floating-point reconfigurable compressor network;

8 is a schematic diagram of a 32-bit sub-compressor in the reconfigurable compressor part of the vector point accumulation network according to an embodiment of the present invention;

9 is a schematic diagram of the floating-point exponent, the mantissa post-processing/fixed-point operand part, and the parallel exponent correction unit in the vector point accumulation network according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The main features of the invention are: the data format can be reconfigured, and the vector length can be configured. The following description symbols are agreed during the description process: the dot product instruction is described as D=A+B DOTC{(U)}{(M)}{(FBS)}; where A and D are 32-bit scalar data, and B and C are 512-bit vector data, DOT means the dot product operator; Mask is a 64-bit register, each bit controls the 8-bit byte of the B×C result; M means that the vector point accumulation operation is affected by the Mask register, when the M option does not exist Indicates that the Mask register has no effect on the vector point accumulation operation; U indicates the unsigned option; FBS indicates the data format, expressed in 2-bit binary. "00" stands for 32-bit fixed point, "01" stands for 32-bit compact simple-precision floating point, "10" stands for 8-bit byte, and "11" stands for 16-bit halfword.

In the embodiment of the present invention, it is assumed that B and C are 512-bit vector data, but the present invention is applicable to any occasion where B and C are 32 multiples of bit width, and the width of the Mask register and the length relationship of vector B and C are Length _Mask =Length _B /8.

As shown in Figure 1, Figure 1 is a schematic structural diagram of a vector point accumulation network that supports fixed-floating point reconfigurable vector lengths according to an embodiment of the present invention. The vector point accumulation network includes sequentially connected parallel reconfigurable Multiplier part 1, floating-point exponent and mantissa preprocessing part 2, reconfigurable compressor part 3, floating-point exponent and mantissa post-processing/fixed-point operation part 4. in:

Parallel reconfigurable multiplier 1 receives vector data B, C and data options FBS, U as input, and performs vector multiplication operation according to the corresponding data format, obtains the result of vector B×C, and outputs it to floating-point exponent and mantissa Preprocessing part 2;

The floating-point exponent and mantissa preprocessing part 2 receives the multiplication result B×C and scalar data A of the parallel reconfigurable multiplier 1 as input, and completes the selection of the maximum value of the floating-point exponent, difference of exponent, shift alignment, complement conversion and Sticky bit compensation and other operations to obtain the processed vector result B×C and scalar result A, and output the processed result to the reconfigurable compressor part 3;

The reconfigurable compressor part 3 receives the floating-point exponent and the processing result of the mantissa preprocessing part 2, and compresses it to obtain a "sum string" (S) and a "carry string" (C), and outputs it to the floating-point exponent , Mantissa post-processing/fixed-point operation part 4;

The floating-point exponent and mantissa post-processing/fixed-point operation part 4 receives the "sum string" S and "carry string" C of the reconfigurable compressor part 3 for mantissa addition, and for the fixed-point format, directly performs result processing to obtain a fixed-point vector point accumulation Add the result; for the floating-point format, perform leading 1 judgment, normalized shift, normalized rounding, exponent adjustment, sign adjustment and other operations, and finally get the floating-point vector point accumulation result.

The vector point accumulation and addition network with configurable vector length supporting fixed-floating-point reconfigurable provided by the present invention will be described in detail below with reference to FIG. 2 to FIG. 9 . In terms of specific implementation, the present invention includes parallel, cascade, reconfigurable and configurable designs.

Parallel reconfigurable multiplier 1 uses 16 identical 32-bit reconfigurable multipliers 11, supports 8/16/32-bit fixed-point multiplication, 32-bit IEEE754 standard simple-precision floating-point multiplication, and 16 32-bit multipliers in parallel work, reaching a throughput of 16 x 32 bits. The 32-bit reconfigurable multiplier is composed of basic 8×8 multipliers, which can complete 8/16/32-bit signed/unsigned fixed-point multiplication and 32-bit compact simple-precision floating-point multiplication to obtain 512 (=16 ×32) bit multiplication result. The high-bit-width multiplier is composed of lower-bit-width multipliers, with an 8×8 multiplier as the basic unit, and four 8×8 multipliers are organized into a 16×16 multiplier according to a certain relationship. Four 16×16 multipliers are configured as a 32×32 multiplier according to a certain relationship.

As shown in FIG. 2, FIG. 2 is a schematic diagram of an 8×8 multiplier configured as a 16×16 multiplier according to an embodiment of the present invention, wherein the mathematical description of the 16-bit multiplier is shown in Formula 1 below:

A×B=(AH×2 ⁸ +AL)×(BH×2 ⁸ +BL) (Formula 1)

=AH×BH×2 ¹⁶ +(AH×BL+AL×BH)×2 ⁸ +AL×BL

Among them, AH/BH and AL/BL are the high and low 8 bits of 16-bit data A/B respectively. First, 4 8×8 multipliers work in parallel, and each 8×8 multiplier obtains 2 compression results through the Wallace compression tree; then the 8 compression results of the 4 multipliers are weighted and then enter together into 1 8-2 The compressor gets the final "sum string" S and "carry string" C; S and C get the upper 24 bits of the 16×16 multiplier through a 24-bit adder, and the other low 8 bits of the 16×16 multiplier come directly from AL The lower 8 bits of the ×BL multiplier, and the lower 8-bit carry output of the AL×BL multiplier is used as the carry input of the 24-bit multiplier. Finally, through a selector, when working in 8×8 mode, the selector outputs 16-bit results of AL×BL and AH×BL multipliers; when working in 16×16 mode, the selector outputs 24-bit adder The result of the result and the low 8-bit result of AL×BL form the 32-bit result of the 16×16 multiplier.

Fig. 3 has provided the array diagram that the 8 * 8 multipliers according to the embodiment of the present invention are organized into 16 * 16 multipliers, similarly four 16 * 16 multipliers can be combined to form a 32 * 32 multipliers according to the same method multiplier.

Provided above is the idea that the low-order multiplier is configured as a high-order multiplier, but when the multiplier of the present invention is implemented, all adopt the default saturation and truncation processing method, that is, the result of the 8×8 multiplier only takes the lower 8 bits, When the high bit has a result, the low 8 bits directly saturate and take the maximum/minimum value. Similarly, for 16×16 multiplication, the lower 16 bits are taken as the result; for 32×32 multiplication, the lower 32 bits are taken as the result.

As shown in Figure 1, the floating-point exponent and the mantissa operation part 2 include an exponent cascade comparator 21, an exponent difference array 22, a shift alignment unit 23, a complement conversion unit 24 and a sticky bit compensation unit 25; The exponent cascade comparator 21 is used to obtain the maximum value E _{max of} 17 floating-point exponents; the exponent difference array 22 is used to obtain the difference E _max -E i between each floating-point exponent E _i and the maximum value E _max of the floating-point exponent , the index difference is used to shift the shift distance of the alignment unit 23; the shift alignment unit 23 uses the output _Emax - _Ei of the index difference array 22 as a control signal, performs a right shift operation, and performs a right shift operation on the floating-point mantissa Alignment; the complement conversion unit 24 performs a negation operation on the floating-point mantissa after the specific shift, and the mantissa that needs to be negated is a floating-point mantissa whose sign bit is different from the sign bit of the largest floating-point index; the sticky bit compensation unit 25 performs one-bit compensation for the floating-point mantissa that is removed and the floating-point mantissa that needs to be complemented to obtain a 17-bit compensation unit.

时需要对相应移位后的浮点尾数进行求反操作；同时对移出去的ΔE_i位尾数进行Sticky补偿，当

(尾数需要求补)或者移出去的二进制位中含有1时需要进行Sticky补偿，即Sticky_i＝1。Sticky位补偿单元25统计出Sticky₀-Sticky₁₆中需要进行Sticky位补偿的个数Comp。整个浮点指数、尾数预处理部分输出512位向量尾数、32位标量尾数和5位Sticky补偿位Comp。The floating-point exponent and mantissa preprocessing part 2 obtains 16 floating-point multiplication results from the parallel reconfigurable multiplier part 1, and sequentially separates the floating-point exponent E ₀ -E ₁₅ , the mantissa M ₀ -M ₁₅ and the sign bit S ₀ -S ₁₅ . 16 floating-point multiplication result exponents E ₀ -E ₁₅ and the floating-point exponent E ₁₆ in the scalar register enter the cascaded exponent comparator 21 to obtain the maximum floating-point exponent E _max , and then obtain a floating-point value in turn through the index difference array 22 The difference ΔE _i between the exponent E _i and the maximum value E _max of the exponent, the exponent difference array is 17 parallel 8-bit subtractors. The shift alignment unit 23 uses 17 32-bit parallel shifters to perform simultaneously, the control signal of each shifter comes from the output ΔE _i of the index difference array 22, and the output of the shifter is given to the complement conversion unit 24, when

It is necessary to invert the corresponding shifted floating-point mantissa; at the same time, sticky compensation is performed on the shifted ΔE _i- bit mantissa, when

(The mantissa needs to be complemented) or when the shifted binary bit contains 1, sticky compensation needs to be performed, that is, Sticky _i =1. The sticky bit compensating unit 25 counts the number Comp of Sticky bit compensating among Sticky ₀ - Sticky ₁₆ . The entire floating-point exponent and mantissa preprocessing part outputs 512-bit vector mantissa, 32-bit scalar mantissa and 5-bit Sticky compensation bit Comp.

When working in the fixed-point mode, the floating-point exponent and mantissa preprocessing part 2 directly outputs the fixed-point result through another path, and the fixed-point data does not need any processing in this part.

As shown in FIG. 4 , FIG. 4 is a schematic diagram of a floating-point exponent and a mantissa preprocessing part in the vector point accumulation network according to an embodiment of the present invention, and a comparison of three exponents at a time to obtain a larger floating-point exponent network. In order to reduce the delay of the critical path, when performing cascade comparison of floating-point indices, three numbers are compared each time, and three 8-bit comparators work in parallel to generate corresponding flag bits, and then select and output 3 numbers according to the respective flag bits. the maximum value in .

级减少为级，减少了2级8位比较器的延时，增加了一些相应的控制逻辑，但控制逻辑延时大大小于8位比较器，总体上减少了级联指数比较器的延时。As shown in FIG. 5, FIG. 5 is a schematic diagram of the floating-point exponent and mantissa preprocessing part in the vector point accumulation network according to the embodiment of the present invention, and the cascaded exponent comparator network to obtain the maximum floating-point exponent. E ₀ -E ₁₆ are respectively input into the first-stage comparator array to obtain 6 "larger values"; then these 6 "larger values" enter the second and third-stage comparator arrays in turn, and finally obtain the maximum value of the floating-point index E _max . In this way the cascaded comparator consists of the original

level reduced to stage, the delay of the 2-stage 8-bit comparator is reduced, and some corresponding control logic is added, but the delay of the control logic is much smaller than that of the 8-bit comparator, and the delay of the cascaded exponent comparator is generally reduced.

时32位尾数需要进行求补操作；Sticky位补偿单元接收

和右移出的ΔE_i位作为控制信号，当

或者对右移出的ΔE_i位规约或操作为1时，进行补码补偿，即Sticky_i＝1，否则Sticky_i＝0。As shown in FIG. 6 , FIG. 6 is a schematic diagram of floating-point exponent and mantissa preprocessing part and floating-point mantissa processing in the vector point accumulation network according to an embodiment of the present invention. In order to keep the accuracy of the floating-point dot product calculation to meet the IEEE754 standard, a 7-bit mantissa extension is performed on the floating-point mantissa, and the 24-bit mantissa is left-shifted by 7 bits; 0, so that the 24-bit floating-point mantissa is extended to 32 bits. When shifting and aligning, the 32-bit mantissa is shifted to the right by ΔE _i bits, and the shifted ΔE _i bits are saved; when

When the 32-bit mantissa needs to be complemented; the Sticky bit compensation unit receives

and the right-shifted ΔE _i bit as a control signal, when

Alternatively, when the bits of ΔE _i shifted out from the right are reduced or operated to be 1, complementary code compensation is performed, that is, Sticky _i =1, otherwise Sticky _i =0.

As shown in FIG. 1 , the reconfigurable compressor part 3 completes 8/16/32-bit fixed-point and 32-bit floating-point mantissa compression, including a Mask masking unit 31 , a sign bit extension unit 32 and a reconfigurable compressor network 33 . Wherein, the Mask masking unit 31 receives the output of the floating-point exponent and the mantissa preprocessing part, and analyzes the value of the Mask register, and the Mask register controls whether the vector register participates in the dot product operation. When the M option is valid, only the value indicated by the Mask register being 1 enters the compressor network; when the M option is invalid, the Mask register has no effect on the dot product operation. The Mask register is 64 bits, and each bit indicates a byte of the vector register. The value of the scalar register and the sticky bit compensation Comp are not affected by the Mask register. After the data is masked by the Mask register, it enters the sign bit extension unit 32, and each 8-bit byte in the 512-bit vector register is an independent unit for 8-bit sign bit extension. When it is an unsigned fixed-point dot product operation (U option is valid), directly add 8 0s in the high order; when it is a signed fixed-point dot product operation (U option is invalid) or a floating-point dot product operation, compensate the 8-bit sign bit in the high order . After sign bit extension, the vector mantissa, scalar mantissa, and Comp compensation unit enter the reconfigurable compressor network 33 together, and the reconfigurable compressor network 33 supports 8/16/32 bit with/unsigned data compression, compressing 16/32 /64 32/16/8-bit data, 32-bit scalar data and Comp compensation units are compressed into "sum string" S and "carry string" C.

As shown in FIG. 7, FIG. 7 is a schematic diagram of the reconfigurable compressor part of the vector point accumulation network according to the embodiment of the present invention, 8/16/32-bit fixed-point, 32-bit floating-point reconfigurable compressor network. The 512-bit vector mantissa enters the first-stage compressor array after sign bit expansion, and is compressed by three layers of 32-bit compressors to obtain two compression results. When working in floating-point mode, the 2 outputs of the third layer 32-bit compressor, the value of the scalar register and the Sticky bit compensation Comp enter a 4-2 compressor to obtain the floating-point mantissa compression result; when working in 32-bit fixed-point mode, the sticky bit compensation Comp of the 4-2 compressor is 0, and the 32-bit fixed-point compression result is obtained. When it is a 16-bit fixed-point format, after three layers of 32-bit compressors, a 16-bit compressor and a 3-2 compressor are compressed together with the value of the scalar register to obtain a 16-bit fixed-point compression result. The 8-bit fixed-frame format is similar to the 16-bit fixed-point format.

As shown in FIG. 8 , FIG. 8 is a schematic diagram of a 32-bit sub-compressor in the reconfigurable compressor part of the vector point-accumulation-add network according to an embodiment of the present invention. The upper part of the figure is the compressor part, and the lower part is the sign bit extension part. The 32-bit compressor is composed of four 8-bit compressors and MUX connected in series. According to different data formats, MUX selects the carry or 0 of the low-bit selector to enter the high-bit compressor. If working in 8-bit mode, the 3 MUXs select 0 input respectively; if working in 16-bit mode, the 1st and 3rd MUX select low-order carry, and the 2nd MUX selects 0; if working in 32-bit mode, 3 Each MUX selects the low bit carry. The four 8-bit compressors in the sign bit extension part are respectively connected to the four 8-bit compressors in the compressor part, and receive the input of the extended sign bit, so as to ensure arithmetic equivalence when compressing data with different granularities.

As shown in Fig. 1, described floating-point exponent, mantissa post-processing/fixed-point number operation part 4 include mantissa addition unit 41, leading 0 prediction PZD 42, floating-point mantissa normalization shift unit 43, floating-point mantissa normalization Rounding unit 44, exponent correction unit 45, sign bit correction 46 and fixed-point result processing 47; the mantissa addition unit 41 adds the compressed S and C strings to obtain the mantissa addition result; the leading 0 prediction PZD 42 performs 0 and 1 pre-coding on the S and C strings entering the mantissa addition unit 41. The 0 and 1 coded strings are processed by the leading 0 judgment circuit to obtain the position of the leading 1, and the mantissa calculation results are shifted during the normalized shift. The distance of the bit, because the precoding may produce 1 bit error, the result after the shift will also be judged and corrected by the compensation circuit; the normalized shift unit 43 of the floating point mantissa adopts the shift obtained by leading 0 prediction PZD 42 The distance shifts the mantissa of the result to obtain a normalized floating-point mantissa result; the normalized floating-point mantissa rounding unit 44 rounds the normalized mantissa according to the Guard, Round, and Sticky bits; the exponent correction unit 45 And sign correction unit 46 carries out exponent adjustment and sign bit correction according to the output of PZD, the situation of normalized rounding and mantissa addition result, obtains final floating-point exponent and sign bit; Said fixed-point result processing unit 47 according to fixed-point instruction option , the result of the mantissa addition unit 41 is processed to obtain a fixed-point vector point accumulation result.

的值。当工作在定点格式时，定点结果处理47选择S+C结果，并进行后处理，得到向量定点点积累加结果。当工作在浮点格式时，根据S+C的结果符号位选择S+C或

的值，并控制符号位修正单元46完成浮点符号位修正。当S+C的符号位为负，选择

的值并对S_max取反作为最终结果的符号位；否则选择S+C的值，且最终结果的符号位与S_max一样。前导0预测PZD 42对进入尾数相加单元41的S、C串进行二进制预编码，此二进制串经前导0判断电路处理得到前导1的位置和规格化移位距离D_normal，控制浮点尾数规格化移位单元43规格化左移或右移的位数；由于预编码可能会产生一位误差，移位后的结果还要经过补偿电路判断并纠正误差。规格化移位完成后，浮点尾数规格化舍入单元44根据移位结果进行Guard/Round/Sticky位判断，完成舍入，在舍入的同时判断尾数结果是否需要进行二次舍入(SecondRound)；当舍入引起浮点尾数最高位产生进位时需要二次舍入，二次舍入会影响浮点的结果指数。指数修正单元45根据浮点最大指数E_max、规格化移位距离D_normal和是否二次舍入(SecondRound)完成浮点结果指数调整。Floating-point exponent, mantissa post-processing/fixed-point operand Part 4 utilizes fast composite adder to calculate S+C and

value. When working in a fixed-point format, the fixed-point result processing 47 selects the S+C result and performs post-processing to obtain a vector fixed-point accumulation result. When working in floating-point format, select S+C or

and control the sign bit correction unit 46 to complete the floating point sign bit correction. When the sign bit of S+C is negative, select

The value of S _max is reversed as the sign bit of the final result; otherwise, the value of S+C is selected, and the sign bit of the final result is the same as S _max . The leading 0 prediction PZD 42 performs binary precoding on the S and C strings entering the mantissa addition unit 41, and the binary string is processed by the leading 0 judging circuit to obtain the position of the leading 1 and the normalized shift distance D _normal to control the floating-point mantissa specification The normalization shift unit 43 standardizes the number of bits shifted left or right; because precoding may generate a one-bit error, the shifted result must be judged and corrected by the compensation circuit. After the normalized shift is completed, the floating-point mantissa normalized rounding unit 44 performs Guard/Round/Sticky bit judgment according to the shift result, completes rounding, and judges whether the mantissa result needs to be rounded twice (SecondRound) while rounding. ); When the rounding causes the highest bit of the floating-point mantissa to generate a carry, double rounding is required, and the double rounding will affect the floating-point result exponent. The exponent correction unit 45 completes the exponent adjustment of the floating-point result according to the maximum floating-point exponent E _max , the normalized shift distance D _normal and whether SecondRound is used.

As shown in Figure 9, Figure 9 is a schematic diagram of the parallel exponent correction unit in the floating-point exponent and mantissa post-processing/fixed-point operand part in the vector point accumulation network according to an embodiment of the present invention, which is normalized and shifted with the floating-point mantissa Unit 43 is done in parallel. Two 8-bit adders are used to calculate the values of E _max +D _normal and E _max +D _normal +1 respectively, and then the final exponential result is selected through the secondary rounding control logic (SecondRound). When double rounding is required, the mantissa needs to be shifted to the left by one bit after the first rounding is completed, and the mantissa of the floating-point result is E _max +D _normal +1. Using the method of exponential parallel adjustment, the original two 8-bit adders on the index adjustment path are reduced to one, which reduces the delay of the critical path and improves the performance of the entire system.

Based on the vector point accumulation network with configurable fixed-floating point reconfigurable vector length shown in Figures 1 to 9, the present invention also provides a data summation with reconfigurable fixed-floating point and configurable data length The method includes: 8/16/32-bit fixed-point data can be reconfigured, and the 8-bit fixed-point data is the basic unit; two 8-bit fixed-point data and corresponding control logic groups are reconstructed into 16-bit fixed-point data; four 8-bit fixed-point data The fixed-point data and the corresponding control logic are reconstructed into 32-bit fixed-point data; the fixed-floating point can be reconfigured, and after the floating-point mantissa is shifted and aligned, it is determined whether to complete the negation operation according to the sign bit; when the sign bit is 1, the floating-point mantissa is calculated On the contrary, the sign bit remains 1, and the floating-point sign bit and mantissa form new 32-bit data; when the sign bit is 0, the floating-point mantissa remains unchanged. After the floating-point mantissa is processed by the sign bit, the fixed-point data path can be multiplexed; the data length is configurable and realized through the Mask register; each bit of the Mask register controls a certain bit field of the vector data, and the participation is configured by configuring the value of the Mask register Operation data length.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (13)

1. support the configurable dot product of the reconfigurable vector length of the fixed and floating network that adds up for one kind, it is characterized in that, comprising:

Parallel restructural multiplier (1) is used to receive vector data B, C and data options FBS, U as input, and the execute vector multiply operation obtains multiplication result B * C of vector data B, C, and exports to floating-point index, mantissa's preprocessing part (2);

Floating-point index, mantissa's preprocessing part (2); Multiplication result B * the C and the scalar data A that are used to receive parallel restructural multiplier (1) are as input; Accomplish to select floating-point index maximal value, that index is asked is poor, displacement alignment, complement code are changed and sticky position compensating operation; Vector result B * C after obtaining handling and scalar result A, and export to restructural compressor reducer part (3);

Restructural compressor reducer part (3) is used to receive the result of floating-point index, mantissa's preprocessing part (2), and it is compressed, obtain " and string " (S) with " carry string " (C), and export to floating-point index, mantissa's aftertreatment/fixed-point operation part (4); And

Floating-point index, mantissa's aftertreatment/fixed-point operation part (4); Be used for " and string " S of being received from restructural compressor reducer part (3) and " carry string " C end of line of going forward side by side is counted addition, the result of mantissa of addition carried out aftertreatment obtain final dot product accumulation result.

2. the configurable dot product of the reconfigurable vector length of the support fixed and floating according to claim 1 network that adds up; It is characterized in that said parallel restructural multiplier (1) adopts 16 identical 32 restructural multipliers (11) group structure to form, and supports 8/16/32 fixed-point multiplication; 32 IEEE754 standards are simplified the single-precision floating point multiplication; 16 32 multiplier concurrent workings obtain 16 * 32=512 position multiplication result, reach 16 * 32 handling capacity.

3. the configurable dot product of the reconfigurable vector length of the support fixed and floating according to claim 2 network that adds up; It is characterized in that; Said parallel restructural multiplier (1) adopts 16 identical 32 restructural multipliers (11) group structure to form, and it is specifically organized the structure process and comprises:

AH/BH, AL/BL are respectively high and low 8 of 16 bit data A/B, at first 48 * 8 multiplier concurrent workings, and each 8 * 8 multiplier obtains 2 compression result through Wallace's compressed tree; Get into 1 8-2 compressor reducer after 8 of 4 multipliers compression result weights are alignd then together and obtain final " and string " S and " carry string " C; S and C obtain the high 24 of 16 * 16 multipliers through 24 totalizers, and directly from the least-significant byte of AL * BL multiplier, the least-significant byte carry of AL * BL multiplier output simultaneously is as the carry input of 24 multipliers for the other least-significant byte of 16 * 16 multipliers; At last, through 1 selector switch, when work is 8 * 8 patterns, 16 results of selector switch output AL * BL and AH * BL multiplier; When being operated in 16 * 16 patterns, 32 results of 16 * 16 multipliers that the result of 24 totalizers of selector switch output and the least-significant byte result of AL * BL constitute.

4. the configurable dot product of the reconfigurable vector length of the support fixed and floating according to claim 1 network that adds up; It is characterized in that; Said floating-point index, mantissa's operation part (2) comprise that index cascade comparer (21), index are asked poor array (22), be shifted alignment unit (23), complement code converting unit (24) and sticky position compensating unit (25), wherein:

Said index cascade comparer (21) is used to obtain 17 floating-point index maximal value E _Max

Said index is asked poor array (22), is used to obtain each floating-point index E _iWith floating-point index maximal value E _MaxDifference E _Max-E _i, this difference E _Max-E _iThe translocation distance of alignment unit (23) is used to be shifted;

Said displacement alignment unit (23) adopts index to ask the output E of poor array (22) _Max-E _iAs control signal, carry out right-shift operation, floating-point coefficient is alignd;

Said complement code converting unit (24) is used for floating-point coefficient after the specific displacement is carried out complementary operation, and the mantissa that need negate is sign bit S _iWith maximum floating-point exponent sign position S _MaxDifferent floating-point coefficients;

Said sticky position compensating unit (25), be used for to the floating-point coefficient that shifts out with need the floating-point coefficient of supplement sign indicating number to carry out a compensation, obtain 17 compensating units.

5. the configurable dot product of the reconfigurable vector length of the support fixed and floating according to claim 4 network that adds up; It is characterized in that; Said floating-point index, mantissa's operation part (2) are obtained 16 floating-point multiplication results, and are isolated the index E of floating-point successively from parallel restructural multiplier part (1) ₀-E ₁₅, the M of mantissa ₀-M ₁₅With sign bit S ₀-S ₁₅16 floating-point multiplication result exponent E ₀-E ₁₅With the floating-point index E in the scalar register ₁₆Get into cascade index comparator (21) and obtain maximum floating-point index E _Max, ask poor array (22) to obtain a floating-point index E successively through index then _iWith index maximal value E _MaxDifference DELTA E _i, it is 17 8 parallel subtracters that index is asked poor array; Displacement alignment unit (23) adopts 17 32 bit parallel shift units to carry out simultaneously, and the control signal of each shift unit is asked the output Δ E of poor array (22) from index _i, shift unit export to complement code converting unit (24), when mantissa needs supplement

The time need to the displacement after floating-point coefficient carry out complementary operation; Δ E to shifting out simultaneously _iPosition mantissa carries out the Sticky compensation, when mantissa needs supplement

Contain in the binary digit that perhaps shifts out at 1 o'clock, need carry out the Sticky compensation, i.e. Sticky _i=1; Sticky position compensating unit (25) counts Sticky ₀-Sticky ₁₆In need carry out Sticky position compensation number Comp.

6. the configurable dot product of the reconfigurable vector length of the support fixed and floating according to claim 1 network that adds up; It is characterized in that; Said restructural compressor reducer part (3) comprises Mask screen unit (31), sign bit expanding element (32) and restructural compressor reducer network (33); Wherein: Mask screen unit (31); Be used to receive the output of floating-point index, mantissa's preprocessing part (2), and analyze the value of Mask register, Mask register controlled vector registor is participated in the number that dot product adds up and operates; Data get into sign bit expanding element (32) after the shielding of Mask register, every octet is 1 independently unit in the 512 bit vector registers of sign bit expanding element (32), carry out the expansion of 8 bit sign positions; After the sign bit expansion; Vector data, scalar data, Comp compensating unit get into restructural compressor reducer network (33) together; Restructural compressor reducer network (33) is supported 8/16/32 to be had/the data without sign compression, and with 16/32/64 32/16/8 bit data and sign-extension bit, 32 scalar datas and sign-extension bit and Comp compensating unit boil down to " and string " S and " carry string " C.

7. the configurable dot product of the reconfigurable vector length of the support fixed and floating according to claim 1 network that adds up; It is characterized in that; " and string " S that said floating-point index, mantissa's aftertreatment/fixed-point operation part (4) are received from restructural compressor reducer part (3) carries out mantissa's addition with " carry string " C; For fixed point format, directly carry out result treatment and obtain fixed point vector dot product accumulation result; For floating-point format, carry out that leading 1 judgement, normalization shift, normalization are rounded off, index is adjusted and symbol adjustment operation, finally obtain floating point vector dot product accumulation result.

8. the configurable dot product of the reconfigurable vector length of the support fixed and floating according to claim 7 network that adds up; It is characterized in that; Said floating-point index, mantissa's aftertreatment/fixed-point number operation part (4) comprise mantissa's addition unit (41), leading 0 prediction PZD (42), floating-point coefficient normalization shift unit (43), floating-point coefficient's normalization round off unit (44), index amending unit (45), sign bit correction (46) and the result treatment (47) of fixing a point, wherein:

Said mantissa addition unit (41) is used for the S after the compression, C string are carried out addition, obtains mantissa's addition result;

Said leading 0 prediction PZD (42); Be used for the S, the C string that get into mantissa's addition unit (41) are carried out 0,1 precoding; This 0,1 coded strings is handled through leading 0 decision circuitry and is obtained leading 1 position; The distance that control mantissa result of calculation is shifted when normalization shift, because precoding may produce 1 bit error, the result after the displacement also will pass through compensating circuit and judge and rectification error;

Said floating-point coefficient normalization shift unit (43), the translocation distance that is used to adopt leading 0 prediction PZD (42) to obtain is shifted to resultant mantissa, obtains normalized result of floating-point coefficient;

The said floating-point coefficient normalization unit (44) that rounds off is used for according to Guard, Round, Sticky position normalized mantissa being rounded off;

Said index amending unit (45) and symbol amending unit (46), the output, normalization situation about rounding off and the mantissa's addition result that are used for according to PZD are carried out index adjustment and sign bit correction, obtain final floating-point exponential sum sign bit;

Said fixed point result treatment unit (47) is used for according to fixed point instruction option, and the result of mantissa's addition unit (41) is handled, and obtains fixed point vector dot product accumulation result.

9. the configurable dot product of the reconfigurable vector length of the support fixed and floating according to claim 8 network that adds up is characterized in that, said floating-point index, mantissa's aftertreatment/fixed-point operation part (4) utilize quick compound totalizer calculate respectively S+C with

Value, wherein: when being operated in fixed point format, fixed point result treatment (47) is selected S+C result, and carries out aftertreatment, obtains fixed point vector dot product accumulation result; When being operated in floating-point format, according to the outcome symbol position of S+C select S+C or

Value, and control character position amending unit (46) is accomplished the floating-point-sign position and is revised; When the sign bit of S+C for negative, select

Value and to S _MaxNegate is as the sign bit of net result; Otherwise select the value of S+C and the sign bit and the S of net result _MaxIdentical.

10. the configurable dot product of the reconfigurable vector length of the support fixed and floating according to claim 8 network that adds up; It is characterized in that; Said leading 0 prediction PZD (42) carries out the scale-of-two precoding to S, the C string that gets into mantissa's addition unit (41), and this binary string is handled through leading 0 decision circuitry and obtained leading 1 position and normalization shift distance B _Normal, control floating-point coefficient's normalization shift unit (43) denormalization left shift or the figure place that moves to right.

The network 11. the configurable dot product of the reconfigurable vector length of support fixed and floating according to claim 8 adds up; It is characterized in that; After normalization shift is accomplished; The floating-point coefficient normalization unit (44) that rounds off carries out the Guard/Round/Sticky position according to shift result and judges that completion is rounded off, and judges when rounding off whether the result of mantissa need carry out secondary round off (SecondRound); Cause that when rounding off floating-point coefficient's most significant digit needs secondary to round off when producing carry, secondary rounds off can influence the result exponent of floating-point.

The network 12. the configurable dot product of the reconfigurable vector length of support fixed and floating according to claim 8 adds up is characterized in that said index amending unit (45) is according to floating-point maximal index E _Max, the normalization shift distance B _NormalWhether secondary round off (SecondRound) accomplish the adjustment of floating point result index.

The network 13. the configurable dot product of the reconfigurable vector length of support fixed and floating according to claim 12 adds up is characterized in that, said index amending unit (45) adopts two 8 totalizers to calculate E respectively _Max+ D _NormalAnd E _Max+ D _Normal+ 1 value is selected final index result through the secondary steering logic (SecondRound) that rounds off then; When the needs secondary rounded off, mantissa also need move to left one after the completion of once rounding off, and floating point result mantissa is E _Max+ D _Normal+ 1.

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