CN102508037B - A testing system and method for equivalent resistance of a bit line gating device - Google Patents

Abstract

A test system and its method of the equivalent resistance of the gating device of bit line, this system includes four consecutive bit lines, every bit line connects a gating device, four gating devices are the same, four said gating devices are respectively: the first gating device, the second gating device, the third gating device and the fourth gating device are used for controlling the bit lines of the memory cells to be in parallel, and each memory cell is adjacent to two adjacent bit lines, and the method further comprises the following steps: the device comprises a gating control device, a high-level supply device, a low-level supply device, a first voltage testing device, a second voltage testing device, a first current testing device, a resistance testing device and a calculating unit. According to the embodiment of the invention, the reading and writing operation of the storage unit is realized by selecting four continuous bit lines, and the bit lines at two ends are selected as the voltage test ends of the gating device, so that the equivalent resistance of the gating device can be accurately obtained, the performance of the gating device can be evaluated, and the accuracy of the reading and writing operation of the storage unit is further improved.

Description

A testing system and method for equivalent resistance of a bit line gating device

technical field

The invention relates to the technical field of testing, in particular to a testing system and method for equivalent resistance of a bit line gating device.

Background technique

In a traditional memory, memory cells are arranged in an array by rows and columns, and each memory cell can be positioned through a combination of word lines and bit lines, and read and write operations can be performed on the memory cells. The gating device is an important part that connects the read signal and the word line and bit line. The required gating device unit is controlled by a set of gating control signals. The gating device unit drives the corresponding word line and bit line, and the read and write signals It is transmitted to the gated bit line to realize the read and write operations on the memory cells located on the corresponding word line and bit line. As shown in Figure 1, it is a schematic diagram of reading and writing operations on memory cells in the prior art, including bit lines 101, bit lines 102, bit lines 103, bit lines 104, memory cells 105, memory cells 106, and memory cells 107. , storage unit 108, storage unit 109, gating device unit 111, gating device unit 112, gating device unit 113, gating device unit 114, gating control device 110, low level providing means 115 and high level providing device 116. When the memory cell 107 is read and written, the gate control device 110 is used to gate the gate device unit 112 and the gate device unit 113 simultaneously, and then gate the bit line 102 and the bit line 103 adjacent to the memory cell 107 to realize Read and write operations on the storage unit 107.

It can be seen that the read and write operations to the storage unit are realized by gating the two bit lines adjacent to the storage unit, as shown in FIG. 1, by gating the two bit lines adjacent to the storage unit 107 Implement read and write operations on the storage unit. However, to realize the read and write operation of the storage unit by this method, on the one hand, it is impossible to judge the performance of the relevant gating device in the operation process, and then the accuracy of the operation result cannot be judged; During the write operation, the voltage and current signals are generally weak. The voltage is between tens of millivolts and tens of microvolts, and the current is between tens of picoamperes and several microamperes. Usually, it needs to be amplified hundreds to tens of thousands of times to meet the A /D conversion requirements, when the accuracy of read and write operations cannot be guaranteed, there may be a huge difference between the amplified signal and the actual signal, which greatly affects the accuracy of read and write operations. Therefore, accurate acquisition of the equivalent resistance value of the gating device is crucial to the accuracy of read and write operations.

Contents of the invention

In view of this, the present invention provides a testing system and method for the equivalent resistance of a bit line gating device, to overcome the defect that the accuracy of read and write operations cannot be guaranteed in the prior art, and to accurately obtain the equivalent resistance of the gating device, Improve the accuracy of read and write operations.

To this end, the embodiments of the present invention provide the following technical solutions:

A test system for the equivalent resistance of a bit line gating device, comprising four continuous bit lines, each bit line is connected to a gating device, the four gating devices are the same, and the four gating devices are respectively: the first The gating device, the second gating device, the third gating device and the fourth gating device, a plurality of storage units, each storage unit is connected to two adjacent bit lines, and further includes:

The gating control device is connected to the four gating devices respectively, and is used to open the four gating devices at the same time;

a high-level providing device, connected to the third gating device, for providing a high-level voltage to the third gating device;

A low-level providing device, connected to the second gating device, for providing a low-level voltage to the second gating device;

a first voltage testing device, connected to the first gating device, for testing the voltage at the port of the first gating device;

A second voltage testing device, connected to the fourth gating device, for testing the voltage at the port of the fourth gating device;

a first current testing device for testing the current flowing through the third gating device;

resistance testing means for testing the resistance of memory cells connected to the bit line connected to the second gating means and the bit line connected to the third gating means;

a calculation unit, configured to calculate according to the high-level voltage, the low-level voltage, the voltage at the port of the first gating device, the voltage at the port of the fourth gating device, the current, and the resistance The equivalent resistance of the bit line gating device.

Preferably, the calculation unit is specifically configured to calculate the equivalent resistance R by the following formula:

$\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{\sqrt{{\mathrm{<span\; class="notranslate">\; m</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; ;</span>$

Wherein, m=I×R _cell +V4-V3, n=I, p=-(V1-V2)×R _cell , V1 is the voltage at the port of the first gating device, and V2 is the low-level voltage , V3 is the high-level voltage, V4 is the voltage at the port of the fourth strobe device, I is the current flowing through the third strobe device, and R _cell is the resistance of the memory cell.

Preferably, the low-level providing means is specifically configured to provide a zero-level voltage to the second gating means.

Preferably, the system also includes:

The second current testing device is used for testing the current Ileak flowing through the memory cell connected to the bit line connected to the third gating device and the bit line connected to the fourth gating device.

Preferably, the system also includes:

The third current testing device is used for testing the current Ibit flowing through the second gating device.

Preferably, both the first voltage testing device and the second voltage testing device include:

A pre-amplification circuit for amplifying the differential mode of the port voltages of the first voltage testing device and the second voltage testing device;

a high-pass filter for removing low-frequency interference in the port voltages of the first voltage testing device and the second voltage testing device;

a low-pass filter for removing high-frequency interference in the port voltages of the first voltage testing device and the second voltage testing device;

a main amplifying circuit, configured to amplify port voltages of the first voltage testing device and the second voltage testing device;

The notch circuit is used for blocking the voltage signal of a specific frequency in the port voltages of the first voltage testing device and the second voltage testing device.

Preferably, the trap circuit includes:

The 50Hz notch circuit is used to block the voltage signal with a frequency of 50Hz in the port voltages of the first voltage testing device and the second voltage testing device.

A method for testing the equivalent resistance of a bit line gating device, comprising four continuous bit lines, each bit line connected to a gating device, the four gating devices are the same, and the four gating devices include a first gating device device, a second gating device, a third gating device and a fourth gating device, a plurality of storage units, each storage unit is connected to two adjacent bit lines, the method includes:

Simultaneously open the four gating devices;

providing a high-level voltage to the third gating device, and providing a low-level voltage to the second gating device;

testing the voltage at the port of the first gating device, testing the voltage at the port of the fourth gating device;

testing the current flowing through the third gating means;

testing the resistance of the memory cells connected to the bit line connected to the second gating device and the bit line connected to the third gating device;

calculating the bit line selection according to the high-level voltage, the low-level voltage, the voltage at the port of the first strobe device, the voltage at the port of the fourth strobe device, the current, and the resistance The equivalent resistance of the pass-through device.

Preferably, the calculation of the equivalent resistance of the gating device includes:

The equivalent resistance R of the gating device is calculated by the following formula:

$\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{\sqrt{{\mathrm{<span\; class="notranslate">\; m</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; ;</span>$

Wherein, m=I×R _cell +V4-V3, n=I, p=-(V1-V2)×R _cell , V1 is the voltage at the port of the first gating device, and V2 is the low-level voltage , V3 is the high-level voltage, V4 is the voltage at the port of the fourth strobe device, I is the current flowing through the third strobe device, and R _cell is the resistance of the memory cell.

Preferably, the providing the low-level voltage to the second gating device includes:

A zero-level voltage is provided to the second gating means.

Preferably, the method also includes:

A current Ileak flowing through the memory cells connected to the bit line connected to the third gating means and the bit line connected to the fourth gating means is tested.

Preferably, the method also includes:

The current Ibit flowing through the second gating means is tested.

Preferably, said testing the voltage of the port of the first gating device by using the first voltage testing device, testing the voltage of the port of the fourth gating device by using the second voltage testing device, and further comprising:

amplifying the differential mode mode in the port voltages of the first voltage testing device and the second voltage testing device;

removing low frequency interference in the port voltages of the first voltage testing device and the second voltage testing device;

removing high frequency interference in the port voltages of the first voltage testing device and the second voltage testing device;

amplifying port voltages of the first voltage testing device and the second voltage testing device;

Blocking a voltage signal of a specific frequency in the port voltages of the first voltage testing device and the second voltage testing device.

Preferably, the blocking the voltage signal of a specific frequency in the port voltage of the first voltage testing device and the second voltage testing device includes:

blocking the voltage signal with a frequency of 50 Hz in the port voltages of the first voltage testing device and the second voltage testing device.

The embodiment of the present invention realizes the reading and writing operation of the storage unit by selecting four consecutive bit lines, and selects the bit lines at both ends as the voltage test terminals of the gating device, so that the equivalent resistance of the gating device can be accurately obtained, and the gating device can be accurately obtained. The advantages and disadvantages of the performance of the device are evaluated, thereby improving the accuracy of reading and writing operations on the storage unit. In addition, the embodiments of the present invention improve the accuracy of the voltage test results by amplifying and filtering the weak voltage signal at the voltage test terminal of the gating device, and further improve the accuracy of reading and writing operations on the storage unit.

Description of drawings

FIG. 1 is a schematic diagram of performing read and write operations on a storage unit in the prior art;

2 is a schematic structural diagram of an equivalent resistance testing system for a bit line gating device according to an embodiment of the present invention;

3 is a schematic structural diagram of a voltage testing device for processing voltage signals according to an embodiment of the present invention;

4 is a flow chart of a method for testing equivalent resistance of a bit line gating device according to an embodiment of the present invention;

Fig. 5 is a flow chart of processing voltage signals according to an embodiment of the present invention.

Detailed ways

In order to enable those skilled in the art to better understand the solutions of the embodiments of the present invention, the embodiments of the present invention will be further described in detail below in conjunction with the drawings and implementations. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As shown in Figure 2, it is a schematic structural diagram of the equivalent resistance testing system of the bit line gating device according to the embodiment of the present invention, including four continuous bit lines: bit line 201, bit line 202, bit line 203, bit line 204, each The bit line is connected to one gating device, and the four gating devices are the same, and the four gating devices are respectively: the first gating device 210, the second gating device 211, the third gating device 212 and the fourth gating device Device 213, a plurality of storage units: storage unit 205, storage unit 206, storage unit 207, storage unit 208, each storage unit is connected to two adjacent bit lines, the system also includes: gate control device 09 , a high level providing device 216 , a low level providing device 215 , a first voltage testing device 214 , a second voltage testing device 217 , a resistance testing device 219 , a first current testing device 218 and a calculation unit 220 . in:

The gating control device 209 is respectively connected with four gating devices, that is, is connected with the first gating device 210, the second gating device 211, the third gating device 212 and the fourth gating device 213, for simultaneously opening The four gating devices.

The high-level providing device 216 is connected with the third gating device 212, and is used for providing a high-level voltage to the third gating device 212. In the embodiment of the present invention, the high-level voltage is a read and write operation voltage.

The low level providing device 215 is connected with the second gating device 211 and is used for providing the low level voltage to the second gating device 211 .

The first voltage testing device 214 is connected to the first gating device 210 for testing the voltage at the port of the first gating device 210;

The second voltage testing device 217 is connected to the fourth gating device 213, and is used to test the voltage at the port of the fourth gating device 213;

The first current testing device 218 is used to test the current flowing through the third gating device 212;

Resistance testing device 219, for testing the resistance of memory cell 206 connected to the bit line 202 connected to the second gating device 211 and the bit line 203 connected to the third gating device 212;

The calculation unit 220 is configured to calculate the equivalent resistance of the bit line gating device according to the high level voltage, the low level voltage, the voltage at the port of the first gating device 210 , the voltage at the port of the fourth gating device 213 , the current and the resistance.

Specifically, the calculation unit can calculate the equivalent resistance R of the gating device through the following formula:

$\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{\sqrt{{\mathrm{<span\; class="notranslate">\; m</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; ;</span>$

Among them, m=I×R _cell +V4-V3, n=I, p=-(V1-V2)×R _cell , V1 is the voltage at the port of the first gating device 210, V2 is the low-level voltage, and V3 is High level voltage, V4 is the voltage at the port of the fourth gating device 213 , I is the current flowing through the third gating device 212 , and R _cell is the resistance of the storage unit 206 .

It should be noted that the low-level providing device 215 can provide a zero-level voltage to the second gating device 211 , at this time, V2 is zero, and p=-V1×R _cell in the above formula.

In other embodiments of the present invention, the system may further include a second current testing device for testing the current flowing through the storage current connected to the bit line 203 connected to the third gating device 212 and the bit line 204 connected to the fourth gating device 213. The current Ileak of the unit 207 .

In other embodiments of the present invention, the system may further include a third current testing device for testing the current Ibit flowing through the second gating device 211 .

It should be noted that both the first voltage testing device 214 and the second voltage testing device 217 may include a structure 300 as shown in FIG. 3 , including:

A preamplifier circuit 301, configured to amplify the differential mode of the port voltages of the first voltage testing device and the second voltage testing device;

A high-pass filter 302, configured to remove low-frequency interference in the port voltages of the first voltage testing device and the second voltage testing device;

A low-pass filter 303, configured to remove high-frequency interference in the port voltages of the first voltage testing device and the second voltage testing device;

a main amplifying circuit 304, configured to amplify port voltages of the first voltage testing device and the second voltage testing device;

The notch circuit 305 is configured to block voltage signals of a specific frequency in the port voltages of the first voltage testing device and the second voltage testing device.

Specifically, the notch circuit 305 may adopt a 50Hz notch circuit, which is used to block the voltage signal with a frequency of 50Hz in the port voltages of the first voltage testing device and the second voltage testing device.

The embodiment of the present invention adopts a high-precision voltage testing device, which first effectively amplifies the weak signal through the preamplifier circuit, then eliminates unnecessary noise through the two-stage filter circuit, and then performs secondary amplification through the main amplifying circuit until Finally, the high-gain and low-noise amplification processing of the entire signal is completed, which effectively improves the accuracy of read and write operations.

Correspondingly, an embodiment of the present invention also provides a method for testing the equivalent resistance of a gating device, the flow chart of which is shown in Figure 4, including the following steps:

Step 401: Turn on four gating devices at the same time.

Step 402: providing a high-level voltage to the third gating device, and providing a low-level voltage to the second gating device;

Specifically, a zero-level voltage may be provided to the second gating means.

Step 403: Test the voltage at the port of the first gating device, and test the voltage at the port of the fourth gating device.

It should be noted that the measured voltage at the port of the first gating device and the voltage at the port of the fourth gating device can be processed as follows, as shown in the flow chart in Figure 5, including the following steps:

Step 501: Amplify the differential mode of the port voltages of the first voltage testing device and the second voltage testing device;

Step 502: removing low-frequency interference in the port voltages of the first voltage testing device and the second voltage testing device;

Step 503: removing high-frequency interference in the port voltages of the first voltage testing device and the second voltage testing device;

It should be noted that step 503 can also be performed before step 502;

Step 504: amplify the port voltages of the first voltage testing device and the second voltage testing device;

Step 505: blocking the voltage signal of a specific frequency in the port voltage of the first voltage testing device and the second voltage testing device;

Specifically, a 50 Hz trap circuit may be used to block the voltage signal with a frequency of 50 Hz in the port voltages of the first voltage testing device and the second voltage testing device.

The embodiment of the present invention improves the accuracy of the voltage test result and further improves the accuracy of reading and writing operations on the storage unit by amplifying and filtering the weak voltage signal at the voltage test terminal of the gating device.

Step 404: Test the current flowing through the third gating device.

Step 405: Test the resistance of the memory cell connected to the bit line connected to the second gating device and the bit line connected to the third gating device.

Step 406: Calculate the equivalent resistance of the bit line gate device according to the high-level voltage, the low-level voltage, the voltage at the port of the first gate device, the voltage at the port of the fourth gate device, the current and the resistance.

Specifically, the equivalent resistance R of the gating device can be calculated by the following formula:

$\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{\sqrt{{\mathrm{<span\; class="notranslate">\; m</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; ;</span>$

Among them, m=I×R _cell +V4-V3, n=I, p=-(V1-V2)×R _cell , V1 is the voltage of the port of the first gating device, V2 is the low level voltage, and V3 is the high level voltage level voltage, V4 is the voltage at the port of the fourth gating device, I is the current flowing through the third gating device, and R _cell is the resistance of the memory cell.

It should be noted that the method may also include the following steps:

testing the current Ileak flowing through the memory cell connected to the bit line connected to the third gating device and the bit line connected to the fourth gating device;

The current Ibit flowing through the second gating means is tested.

The embodiment of the present invention realizes the reading and writing operation of the storage unit by selecting four consecutive bit lines, and selects the bit lines at both ends as the voltage test terminals of the gating device, so that the equivalent resistance of the gating device can be accurately obtained, and the gating device can be accurately obtained. The advantages and disadvantages of the performance of the device are evaluated, thereby improving the accuracy of reading and writing operations on the storage unit. In addition, the embodiments of the present invention meet the requirements of signal A/D conversion by amplifying and filtering the weak voltage signal at the voltage test terminal of the gating device, improve the accuracy of the voltage test result, and further improve the performance of the storage unit. Accuracy of read and write operations.

The embodiments of the present invention have been described in detail above, and the present invention has been described using specific implementation methods herein. The descriptions of the above embodiments are only used to help understand the method and equipment of the present invention; meanwhile, for those of ordinary skill in the art, According to the idea of the present invention, there will be changes in the specific implementation and scope of application. To sum up, the contents of this specification should not be construed as limiting the present invention.

Claims (14)

1. A test system for the equivalent resistance of a bit line gating device, comprising four continuous bit lines, each bit line is connected to a gating device, and the four gating devices are identical, and the four gating devices are respectively: The first gating device, the second gating device, the third gating device and the fourth gating device, a plurality of storage units, each storage unit is connected to two adjacent bit lines, and further includes: The gating control device is connected to the four gating devices respectively, and is used to open the four gating devices at the same time; a high-level providing device, connected to the third gating device, for providing a high-level voltage to the third gating device; A low-level providing device, connected to the second gating device, for providing a low-level voltage to the second gating device; a first voltage testing device, connected to the first gating device, for testing the voltage at the port of the first gating device; A second voltage testing device, connected to the fourth gating device, for testing the voltage at the port of the fourth gating device; a first current testing device for testing the current flowing through the third gating device; resistance testing means for testing the resistance of memory cells connected to the bit line connected to the second gating means and the bit line connected to the third gating means; a calculation unit, configured to calculate according to the high-level voltage, the low-level voltage, the voltage at the port of the first gating device, the voltage at the port of the fourth gating device, the current, and the resistance The equivalent resistance of the bit line gating device. 2. The system of claim 1, wherein: The calculation unit is specifically used to calculate the equivalent resistance R by the following formula: $\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{\sqrt{{\mathrm{<span\; class="notranslate">\; m</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; ;</span>$ Wherein, m=I×R _cell +V4-V3, n=I, p=-(V1-V2)×R _cell , V1 is the voltage at the port of the first gating device, and V2 is the low-level voltage , V3 is the high-level voltage, V4 is the voltage at the port of the fourth strobe device, I is the current flowing through the third strobe device, and R _cell is the resistance of the memory cell. 3. The system of claim 1, wherein: The low-level providing means is specifically configured to provide a zero-level voltage to the second gating means. 4. The system according to claim 1 or 3, further comprising: The second current testing device is used for testing the current Ileak flowing through the memory cell connected to the bit line connected to the third gating device and the bit line connected to the fourth gating device. 5. The system according to claim 1 or 3, further comprising: The third current testing device is used for testing the current Ibit flowing through the second gating device. 6. The system according to claim 1 or 3, wherein the first voltage testing device and the second voltage testing device both comprise: A pre-amplification circuit for amplifying the differential mode of the port voltages of the first voltage testing device and the second voltage testing device; a high-pass filter for removing low-frequency interference in the port voltages of the first voltage testing device and the second voltage testing device; a low-pass filter for removing high-frequency interference in the port voltages of the first voltage testing device and the second voltage testing device; a main amplifying circuit, configured to amplify port voltages of the first voltage testing device and the second voltage testing device; The notch circuit is used for blocking the voltage signal of a specific frequency in the port voltages of the first voltage testing device and the second voltage testing device. 7. The system according to claim 6, wherein the notch circuit comprises: The 50Hz notch circuit is used to block the voltage signal with a frequency of 50Hz in the port voltages of the first voltage testing device and the second voltage testing device. 8. A method for testing the equivalent resistance of a bit line gating device, characterized in that, four continuous bit lines, each bit line is connected to a gating device, the four gating devices are the same, and the four gating devices It includes a first gating device, a second gating device, a third gating device and a fourth gating device, a plurality of memory cells, each of which is connected to two adjacent bit lines, including: Simultaneously open the four gating devices; providing a high-level voltage to the third gating device, and providing a low-level voltage to the second gating device; testing the voltage at the port of the first gating device, testing the voltage at the port of the fourth gating device; testing the current flowing through the third gating means; testing the resistance of the memory cells connected to the bit line connected to the second gating device and the bit line connected to the third gating device; calculating the bit line selection according to the high-level voltage, the low-level voltage, the voltage at the port of the first strobe device, the voltage at the port of the fourth strobe device, the current, and the resistance The equivalent resistance of the pass-through device. 9. The method according to claim 8, wherein said calculating the equivalent resistance of said gating device comprises: The equivalent resistance R of the gating device is calculated by the following formula: $\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; =</span>\frac{\sqrt{{\mathrm{<span\; class="notranslate">\; m</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; \&times;</span>\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; ;</span>$ Wherein, m=I×R _cell +V4-V3, n=I, p=-(V1-V2)×R _cell , V1 is the voltage at the port of the first gating device, and V2 is the low-level voltage , V3 is the high-level voltage, V4 is the voltage at the port of the fourth strobe device, I is the current flowing through the third strobe device, and R _cell is the resistance of the memory cell. 10. The method according to claim 8, wherein the providing a low-level voltage to the second gating device comprises: A zero-level voltage is provided to the second gating device. 11. The method according to claim 8 or 10, further comprising: A current Ileak flowing through the memory cells connected to the bit line connected to the third gating means and the bit line connected to the fourth gating means is tested. 12. The method according to claim 8 or 10, further comprising: The current Ibit flowing through the second gating means is tested. 13. The method according to claim 8 or 10, wherein a first voltage testing device is used to test the voltage at the port of the first gating device, and a second voltage testing device is used to test the port of the fourth gating device voltage, and also includes: amplifying the differential mode mode in the port voltages of the first voltage testing device and the second voltage testing device; removing low frequency interference in the port voltages of the first voltage testing device and the second voltage testing device; removing high frequency interference in the port voltages of the first voltage testing device and the second voltage testing device; amplifying port voltages of the first voltage testing device and the second voltage testing device; Blocking a voltage signal of a specific frequency in the port voltages of the first voltage testing device and the second voltage testing device. 14. The method according to claim 13, wherein the blocking the voltage signal of a specific frequency in the port voltage of the first voltage testing device and the second voltage testing device comprises: blocking the voltage signal with a frequency of 50 Hz in the port voltages of the first voltage testing device and the second voltage testing device.

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