CN102495821A - Delay analysis method for FPGA (field programmable gate array) programmable interconnection lines - Google Patents
Delay analysis method for FPGA (field programmable gate array) programmable interconnection lines Download PDFInfo
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Abstract
The invention provides a delay analysis method for FPGA (field programmable gate array) programmable interconnection lines, which is applicable to the technical field of super-large-scale integrated circuits. In an embodiment of the invention, a programmable interconnection line network of an integral FPGA chip is constructed into an RC (resistance and capacitance) delay network, delay of each path is stored on a node of a terminal of the path after delay of all paths is computed, and accordingly, when delay of the paths is computed, computation speed can be greatly increased, and complexity of time series analysis is reduced.
Description
Technical field
The invention belongs to the very large scale integration technology field, relate in particular to a kind of method of FPGA programmable interconnection delay Analysis.
Background technology
Since 1984 came out, FPGA (field programmable gate array) had become the most general a kind of module in the Design of Digital Circuit field.FPGA is mainly by input/output module (I/O Block; IOB), programmed logical module (Configurable Logic Block; CLB), programmable interconnect resource (Programmable Interconnect Resource; PI) and several most of institutes such as memory module constitute, the user can connect into these modules the digital display circuit with required function through the mode of programming.
Wherein, the programmable interconnect resource has occupied the most area of FPGA, and the path delay on the interconnection line is directly restricting the clock frequency of FPGA, affects the performance of whole fpga chip.Therefore, the delay data of FPGA programmable interconnection is an important parameter of the whole FPGA performance of assessment.
Summary of the invention
In order to address the above problem, the purpose of the embodiment of the invention is to provide a kind of method of FPGA programmable interconnection delay Analysis.
The embodiment of the invention is achieved in that a kind of FPGA programmable interconnection delay Analysis method, said method comprising the steps of:
Extract the basic delay unit in the FPGA programmable interconnection, and set up the equivalent RC model of every kind of basic delay unit;
Divide the able to programme basic interconnecting unit that is comprised among the FPGA, and analyze the included basic delay unit of each basic interconnecting unit able to programme and the annexation of each basic delay unit;
Analyze the annexation of each basic interconnecting unit able to programme in the fpga chip;
According to selected path; Analyze the included able to programme basic interconnecting unit in this path; According to the annexation of the included basic delay unit of basic interconnecting unit able to programme annexation, each basic interconnecting unit able to programme each other, each basic delay unit and the time-delay of the basic pairing RC model of delay unit, calculate total time-delay in this path.
Further, said basic delay unit comprises MUX, phase inverter and line.
Further, FPGA basic interconnecting unit able to programme is divided into the inner interconnecting unit of CLB, the inner interconnecting unit of IOB according to the logical block at its place.
Further, it is characterized in that the step of the annexation of each basic interconnecting unit able to programme is specially in the said analysis fpga chip:
Basic configuration point, input and output, functional configuration information, coordinate information, the annexation each other of MUX in each basic interconnecting unit are described in the programmable interconnection resource.
Further, the method for building up of the RC model of line comprises: according to divide a kind of interconnection line model of each layer definition based on the interconnection line kind of domain cabling level; With the unit length that L0 carries model as line, the line that makes up unit length carries the RC model; In the software model in the coordinate distance of unit and the corresponding domain the true length of line have a fixing conversion ratio between the two; When the calculating line carries time-delay; Virtual length based on required computing line in this conversion ratio and the software model; Can converse the true length of required computing line on physical layout, thereby carry the RC model, converse the corresponding RC delay model of this section line structure according to corresponding line.
In an embodiment of the present invention; The programmable interconnection network struction of whole fpga chip has been become a RC time delay network; And after the time-delay that calculates all paths, the time-delay of every paths is kept on the node of this Trail termination, like this in the calculating path time-delay; Can improve computing velocity greatly, reduce the complexity of time series analysis.
Description of drawings
Fig. 1 is the process flow diagram of the method for the FPGA programmable interconnection delay Analysis that provides of the embodiment of the invention;
Fig. 2 is the synoptic diagram in the Interconnect Delay path that provides of the embodiment of the invention;
Fig. 3 is the MUX electrical block diagram that the embodiment of the invention provides;
Fig. 4 is the RC illustraton of model of the metal-oxide-semiconductor that provides of the embodiment of the invention;
Fig. 5 is the RC illustraton of model of the phase inverter that provides of the embodiment of the invention;
Fig. 6 is the RC illustraton of model of the lead that provides of the embodiment of the invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Structure according to FPGA programmable interconnection resource; Interconnection line is carried out the rational and effective cutting; Define the appropriate syntax form simultaneously and describe the logical connection structure of the FPGA programmable interconnection after cutting apart; Construct the hierarchy type RC network model of FPGA programmable interconnection, adopt the supporting time series analysis software of researching and developing voluntarily can calculate the time-delay of the inner any paths of whole FPGA at last.
Fig. 1 shows the flow process of the method for the FPGA programmable interconnection delay Analysis that the embodiment of the invention provides, and details are as follows:
In step S101, extract the basic delay unit in the FPGA programmable interconnection, and set up the equivalent RC model of every kind of basic delay unit.
In the interconnection line resource of FPGA, basic delay unit can be divided into three kinds: a, switch MUX MUX, can control the gating paths through collocation point; B, phase inverter can be used to change phase place and increase subordinate's driving; C, line connect each unit component.
For the delay model of switch MUX MUX, in the interconnection line resource of FPGA, switch MUX MUX is the switch as the gating paths of collocation point control, and is as shown in Figure 2.And switch MUX MUX generally is made up of 2 grades of transistor switches, and transistor as shown in Figure 3 (NMOS or PMOS) is controlled whether conducting of interconnection line as the switch of collocation point gating.So, at first need set up delay model to single metal-oxide-semiconductor.
(1) in transistorized delay model, we adopt the modeling of typical ∏ type RC network, and this model has been proved to be it and has had very good effect.The RC model of NMOS pipe is as shown in Figure 4, resistance and electric capacity when R, C represent transistorized conducting respectively.
On this basis, we can describe the time-delay mould MUX type of switch MUX with the delay model of 2 grades of metal-oxide-semiconductors.The sub-size of different metal-oxide-semiconductors just has different model, and a switch MUX MUX the inside has 2 kinds of sized tube again, so can obtain the switch MUX MUX delay model of many kinds.For the ease of using, can the delay model of various different switch MUX MUX be put together with the form of cell library, put down in writing as follows:
MUX_NAME?：mux_1
resistance1?R1
resistance2?R2
capacitance1 C1
capacitance2 C2
The explanation of key word and grammer is as follows in the form:
The title of MUX represented in l MUX_NAME key word, and this can distinguish dissimilar MUX according to the size of metal-oxide-semiconductor among the MUX, and mux_1 representes the name of a MUX thereafter, separated by ": " in the middle of both.
L resistance1 and resistance2 represent the first order of this MUX and the equivalent RC resistance of second level metal-oxide-semiconductor, and R1 and R2 represent resistance value, separate with the space between the two; Capacitance1 and capacitance2 represent the first order of this MUX and the equivalent RC electric capacity of second level metal-oxide-semiconductor, and C1 and C2 represent capacitance, separate with the space between the two.
Like this, when utilizing analysis software to analyze the time-delay of certain paths, under the situation of the known MUX type of using, just can the call unit storehouse inside the resistance, the parameter of electric capacity of corresponding equivalent electrical circuit.
(2) the RC delay model of phase inverter is as shown in Figure 5.For the ease of using, be described below with software code:
INV_NAME?：inv_1
resistance?R
capacitance C
The explanation of key word and grammer is as follows in the form:
The type of phase inverter represented in l INV_NAME key word, can distinguish according to the size of metal-oxide-semiconductor in the phase inverter, and inv_1 is the name of the phase inverter of reality, separates with ": " in the middle of both.
L resistance representes the equivalent RC resistance of phase inverter, and R representes resistance value; Capacitance representes the RC equivalent capacity of phase inverter, and C representes capacitance.
(3) the RC delay model of lead is as shown in Figure 6.
In the ICR interconnect resource of FPGA, lead is used for connecting each several part configurable switch resource and programmed logical module.Generally in small-scale circuit, the time-delay of lead is negligible, but inner at the FPGA of high integration, this part time-delay can not be ignored.Therefore, we also can adopt the RC model of unit length (0.1um) to describe the time-delay of lead.Simple point can adopt lump RC model, but result of study shows that the degree of accuracy of this model is not high, so we adopt improved distributed RC model T3 pattern type, and is as shown in Figure 6.For the ease of using, be described below with software code:
LINE_NAME?：cs_line_1
Resistance R
capacitance C
The explanation of key word and grammer is as follows in the form:
The type of line represented in l LINE_NAME key word, can divide different line models according to different types of cabling in the actual domain, and cs_line_1 representes the name of line, separates with ": " in the middle of both.
L resistance representes the equivalent RC resistance of line, and R representes resistance value; Capacitance representes the RC equivalent capacity of line, and C representes capacitance.
In step S102, divide the able to programme basic interconnecting unit that is comprised among the FPGA, and analyze the included basic delay unit of each basic interconnecting unit able to programme and the annexation of each basic delay unit.
In the main description FPGA interconnection line resource, basic configuration point, input and output, functional configuration information, coordinate information, the annexation each other of MUX in each basic interconnecting unit.
Because FPGA inside all is the unit of many repeatabilities, as CLB, IOB etc., therefore just can be in to the interconnection line piece modeling of their peripheries based on these basic unit.The interconnection line piece of every type of basic logic unit correspondence can be used as an elementary cell of interconnection line and describes; When describing these interconnected elementary cells; Need to describe the input and output of the inner MUX of these interconnecting units, the functional description of collocation point correspondence and the output of MUX and be connected to the next stage input end through those phase inverters, we can define similarly some syntax formats:
CELL INC_CLB
// input and output of selecting 1 selector switch for one 8 are described
MUX_1?（A1，A2，A3，A4，A5，A6，A7，A8?—>?Z1）
……………..
……………..
The functional description of // corresponding collocation point
if（cfg_1=8’b00000001；cfg_2=4’b0001）?Z1=A1；
if（cfg_1=8’b00000010；cfg_2=4’b0010）?Z1=A2；
if（cfg_1=8’b00000100；cfg_2=4’b0100）?Z1=A3；
if（cfg_1=8’b00001000；cfg_2=4’b1000）?Z1=A4；
if（cfg_1=8’b00010000；cfg_2=4’b0001）?Z1=A5；
if（cfg_1=8’b00100000；cfg_2=4’b0010）?Z1=A6；
if（cfg_1=8’b01000000；cfg_2=4’b0100）?Z1=A7；
if（cfg_1=8’b10000000；cfg_2=4’b1000）?Z1=A8；
…………….
……………..
INV_1 INV_2?（Z1）；
…………….
……………..
The explanation of key word and grammer is as follows in the form:
L CELL key word, the title of indication interconnection line elementary cell, INC_CLB is exactly the name of unit, separates with the space between the two;
L MUX_1 (A1, A2, A3, A4, A5, A6, A7, A8-> Z1) represent the kind of a MUX and the description of input and output thereof.MUX_1 representes the type of this MUX, a kind of MUX delay model among its corresponding step S101, and A1 representes the input of MUX to A8, middlely separates with ", "; Z1 representes output, input with export between separate with "-> ".
L if (cfg_1=8 ' b00000001; Cfg_2=4 ' b0001) Z1=A1; Represent the functional description that is input to output that each collocation point is corresponding.With the if beginning, the value of first order metal-oxide-semiconductor switch among the value representation MUX of cfg_1 in the bracket, cfg_2 representes the value of second level metal-oxide-semiconductor switch, and the value of corresponding position is 1 expression switch conduction, and 0 expression switch cuts out.
L INV_1 INV_2 (Z1); The output Z1 of expression MUX outputs to next stage through two-stage phase inverter INV_1 and INV_2.Here the progression of phase inverter can be arbitrarily, the delay model of said phase inverter among the corresponding step S101 of phase inverter INV_1 and phase inverter INV_2.
The description of some syntax formats through top definition, we can know the load that through which collocation point of MUX can arrive output and output terminal in the inner input of an interconnecting unit.
In step S103, analyze the annexation of each basic interconnecting unit able to programme in the fpga chip.
On the basis of above these interconnecting units, we can build the Interconnect Delay network of whole fpga chip through the description to coordinates logo, line kind and the annexation thereof of these unit.
In step S104; According to selected path; Analyze the included able to programme basic interconnecting unit in this path; According to the annexation of the included basic delay unit of basic interconnecting unit able to programme annexation, each basic interconnecting unit able to programme each other, each basic delay unit and the time-delay of the basic pairing RC model of delay unit, calculate total time-delay in this path.
After placement-and-routing, just can utilize the Interconnect Delay network of structure to calculate all path delay.When choosing the path, we are with the phase inverter of the large-size separated point as two paths, and in the time-delay in the path before calculating phase inverter, it is just passable just only need to be used as its load to this phase inverter; And in the time-delay in the path after calculating phase inverter, the prime driving that just need be used as it to this phase inverter just.In addition, in the influence of calculating the next door branch road, the effective capacitance that only needs to consider this branch road gets final product.Like this, in the path that all split, can set up a tree-like time delay network of RC, calculate the time-delay of every paths then through the Elmore time-delay method according to the model of the basic delay unit that extracts among the step S101.
After the time-delay that calculates all paths, the time-delay of every paths is kept on the node of this Trail termination, be convenient to software and in follow-up time series analysis process, delay analysis fast carried out in a certain or some paths and calculated.
For the ease of understanding, we carry out detailed explanation to the XC2V1000 chip of Virtex-II series to the interconnection line RC network time-delay modeling process of its inside, specifically see also figure
The XC2V1000 chip internal has MUX unit in 8, inverter module in 4, and line unit kind in 6 is extracted the RC parameter of their corresponding RC delay models respectively to these unit.
(1) modeling of programmable interconnect spider lines is described
Extract all interconnection line unit kinds of XC2V1000 chip internal, elementary cells such as INC_CLB, INC_IOL, INC_IOB, INC_BRAM, INC_MUL, INC_DMI are arranged, these all interconnection line unit are described.Then, with the form of coordinate, whole interconnection line time delay network is described based on these basic interconnection line unit.
(2) calculating path time-delay
According to the result after the placement-and-routing, take out the RC tree network of every paths, just can calculate the time-delay of any paths.Utilize the time-delay of Elmore time-delay formula calculating path, be kept on the node of Trail termination source, be convenient to follow-up time series analysis and use calculating resulting time-delay.In time series analysis, can add up the time-delay of each paths on the path of concrete certain bar analysis and multiply by a scale-up factor K (generally getting 0.69), just can obtain a path delay more accurately.
Below be this method result of calculation and SPICE emulation comparative result.
| N TYPE | The model calculation result of patent of the present invention | The operation result that adopts the SPICE emulator to obtain | Two kinds of results' deviation ratio |
| 2 | 326.8ps | 273.2 ps | 19.6% |
| 3 | 468.2 ps | 403.6 ps | 16.0% |
| 4 | 616.2 ps | 540.9ps | 13.9% |
| 5 | 757.8 ps | 673.1 ps | 12.6% |
Explain: under the technology of 0.15um, N representes the number of MUX MUX, and unit is ps.
Adopt this method; Compare through Theoretical Calculation and SPICE simulation result, the result finds that this method delay time error can be controlled in certain scope; And with respect to the SPICE simulation velocity sooner, more effective, can be applicable to the delay Analysis of any a FPGA programmable interconnection.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. a FPGA programmable interconnection delay Analysis method is characterized in that, said method comprising the steps of:
Extract the basic delay unit in the FPGA programmable interconnection, and set up the equivalent RC model of every kind of basic delay unit;
Divide the able to programme basic interconnecting unit that is comprised among the FPGA, and analyze the included basic delay unit of each basic interconnecting unit able to programme and the annexation of each basic delay unit;
Analyze the annexation of each basic interconnecting unit able to programme in the fpga chip;
According to selected path; Analyze the included able to programme basic interconnecting unit in this path; According to the annexation of the included basic delay unit of basic interconnecting unit able to programme annexation, each basic interconnecting unit able to programme each other, each basic delay unit and the time-delay of the basic pairing RC model of delay unit, calculate total time-delay in this path.
2. FPGA programmable interconnection delay Analysis method according to claim 1 is characterized in that said basic delay unit comprises MUX, phase inverter and line.
3. FPGA programmable interconnection delay Analysis method according to claim 1 is characterized in that, FPGA basic interconnecting unit able to programme is divided into the inner interconnecting unit of CLB, the inner interconnecting unit of IOB according to the logical block at its place.
4. FPGA programmable interconnection delay Analysis method according to claim 1 is characterized in that the step of the annexation of each basic interconnecting unit able to programme is specially in the said analysis fpga chip:
Basic configuration point, input and output, functional configuration information, coordinate information, the annexation each other of MUX in each basic interconnecting unit are described in the programmable interconnection resource.
5. FPGA programmable interconnection delay Analysis method according to claim 2 is characterized in that the method for building up of the RC model of line comprises: according to divide a kind of interconnection line model of each layer definition based on the interconnection line kind of domain cabling level; With the unit length that L0 carries model as line, the line that makes up unit length carries the RC model; In the software model in the coordinate distance of unit and the corresponding domain the true length of line have a fixing conversion ratio between the two; When the calculating line carries time-delay; Virtual length based on required computing line in this conversion ratio and the software model; Can converse the true length of required computing line on physical layout, thereby carry the RC model, converse the corresponding RC delay model of this section line structure according to corresponding line.
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| CN105824680A (en) * | 2015-01-07 | 2016-08-03 | 展讯通信（上海）有限公司 | Memory compiler timing sequence simulation method |
| CN106712751A (en) * | 2016-11-25 | 2017-05-24 | 深圳市紫光同创电子有限公司 | Interconnection apparatus, field-programmable gate array device and signal transmission control method thereof |
| CN107967704A (en) * | 2016-10-20 | 2018-04-27 | 上海复旦微电子集团股份有限公司 | A kind of fpga chip domain line display methods |
| CN108267685A (en) * | 2018-01-17 | 2018-07-10 | 郑州云海信息技术有限公司 | A kind of method based on timing path verification FPGA interface sequential |
| CN109583005A (en) * | 2018-10-16 | 2019-04-05 | 复旦大学 | GRMFPGA interconnects the calculation method of gauze delay |
| CN111812490A (en) * | 2019-04-12 | 2020-10-23 | 上海复旦微电子集团股份有限公司 | Method for testing signal transmission delay in FPGA chip |
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| CN103810446A (en) * | 2012-11-15 | 2014-05-21 | 中国科学院研究生院 | Physical unclonable function circuit based on on-chip global interconnection random delay network |
| CN105808471A (en) * | 2014-12-31 | 2016-07-27 | 京微雅格（北京）科技有限公司 | FPGA (Field Programmable Gate Array) chip time delay information storage method and device, and FPGA chip time delay information access method and device |
| CN105808471B (en) * | 2014-12-31 | 2018-09-11 | 京微雅格（北京）科技有限公司 | Storage, access method and the device of fpga chip delayed data |
| CN105824680A (en) * | 2015-01-07 | 2016-08-03 | 展讯通信（上海）有限公司 | Memory compiler timing sequence simulation method |
| CN107967704A (en) * | 2016-10-20 | 2018-04-27 | 上海复旦微电子集团股份有限公司 | A kind of fpga chip domain line display methods |
| CN106712751A (en) * | 2016-11-25 | 2017-05-24 | 深圳市紫光同创电子有限公司 | Interconnection apparatus, field-programmable gate array device and signal transmission control method thereof |
| CN108267685A (en) * | 2018-01-17 | 2018-07-10 | 郑州云海信息技术有限公司 | A kind of method based on timing path verification FPGA interface sequential |
| CN109583005B (en) * | 2018-10-16 | 2022-11-18 | 复旦大学 | Calculation Method of GRMFPGA Internet Delay |
| CN109583005A (en) * | 2018-10-16 | 2019-04-05 | 复旦大学 | GRMFPGA interconnects the calculation method of gauze delay |
| CN111812490A (en) * | 2019-04-12 | 2020-10-23 | 上海复旦微电子集团股份有限公司 | Method for testing signal transmission delay in FPGA chip |
| CN111812490B (en) * | 2019-04-12 | 2023-04-28 | 上海复旦微电子集团股份有限公司 | Method for testing signal transmission delay in FPGA chip |
| CN112731823A (en) * | 2019-10-28 | 2021-04-30 | 深圳市国微电子有限公司 | FPGA interconnection line circuit and FPGA interconnection line delay reduction method |
| CN114722770A (en) * | 2021-01-06 | 2022-07-08 | 上海复旦微电子集团股份有限公司 | Method and equipment for creating delay model of FPGA circuit and obtaining delay |
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| CN114661531B (en) * | 2022-02-28 | 2023-08-29 | 成都市硅海武林科技有限公司 | Fine-granularity self-repairing circuit and method for FPGA |
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