CN102495270A - Satellite reception control signal detection circuit - Google Patents
Satellite reception control signal detection circuit Download PDFInfo
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- CN102495270A CN102495270A CN2011104434627A CN201110443462A CN102495270A CN 102495270 A CN102495270 A CN 102495270A CN 2011104434627 A CN2011104434627 A CN 2011104434627A CN 201110443462 A CN201110443462 A CN 201110443462A CN 102495270 A CN102495270 A CN 102495270A
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Abstract
The invention discloses a satellite reception control signal detection circuit which comprises a comparator, a triode whose base electrode is connected with a reverse direction terminal of the comparator, a first current source/resistor whose positive terminal is connected with an emitter electrode of the triode and negative terminal is connected with a positive direction terminal of the comparator, and a second current source/resistor whose positive terminal is connected with a reverse direction terminal of the comparator and negative terminal is connected with a collector electrode of the triode. According to the invention, a system circuit is more concise and easy to maintain, total number of devices is reduced substantially, and the circuit is suitable for mass production.
Description
Technical field
The present invention relates to a kind of satellite and receive the control signal testing circuit.
Background technology
High-low pressure control signal system in the satellite television receiving system that exists at present is used for the control between satellite television receiver and tuner or other equipment.Generally be made up of a plurality of discrete devices, its component number is many, reliability is not high.Said high-low pressure control signal is meant the control signal of being sent by satellite television receiver; Can be low-voltage or high voltage; Low-voltage is meant a voltage less than a fixed voltage VREF; High voltage is meant a voltage greater than this fixed voltage VREF, generally this fixed voltage VREF can be 14V to the arbitrary magnitude of voltage between 15.5V, representative value is 14.75V.General said low-voltage modal value is 13V or 14V, and the high voltage modal value is 18V.Can go to realize different functions through this control system.And can being used for IC chip, scheme provided by the invention comes this control function of more succinct realization.
Summary of the invention
The present invention seeks in order to provide a kind of satellite to receive the control signal testing circuit, with height voltage control system in the more stable realization DVB, make circuit system more succinctly for ease of maintenaince, the device sum significantly reduces and is fit to produce in enormous quantities.
For achieving the above object; First technical scheme that the present invention adopts is: a kind of satellite receives the control signal testing circuit, and it triode, anode that comprises that a comparer, base stage link to each other with the backward end of comparer links to each other with the emitter of triode and first current source/resistance that negative terminal links to each other with the forward end of comparer, second current source/resistance that anode links to each other with the backward end of comparer and negative terminal links to each other with the collector of triode.
On the basis of first technical scheme, further comprise attached technical scheme:
It is for have the chip of VDD pin, VSS pin, ZENER pin at least, and peripheral circuit then comprises the mu balanced circuit between VDD pin and VSS pin, the stabilivolt that links to each other with the ZENER pin simultaneously.
The anode of said first current source/resistance links to each other with the VDD pin simultaneously, and negative terminal then links to each other with the ZENER pin simultaneously, and the negative terminal of second current source/resistance links to each other with the VSS pin simultaneously.
Second technical scheme that the present invention adopts is: a kind of satellite receives the control signal testing circuit, and current source, second and third PMOS parallelly connected with PMOS pipe that it comprises triode that a comparer, base stage link to each other with the backward end of comparer, is made up of second resistance and PMOS pipe manages and managed and the 2nd NMOS manages the current mirror of forming by a NMOS.
On the basis of second technical scheme, further comprise attached technical scheme:
The collector of said triode connects the VSS pin, and the ZENER pin connects first resistance and stabilivolt.
The resistance of said first resistance is adjustable.
Because the technique scheme utilization, the present invention compared with prior art has advantage:
Height Control of Voltage in the more stable realization DVB, make circuit system more succinctly for ease of maintenaince, the device sum significantly reduces and be fit to produce in enormous quantities.
Description of drawings
Fig. 1 is the circuit diagram of the first embodiment of the present invention;
Fig. 2 is the circuit diagram of the second embodiment of the present invention.
Embodiment
Below in conjunction with embodiment the present invention is further described:
Embodiment one: as shown in Figure 1; It is first embodiment that a kind of satellite provided by the invention receives the control signal testing circuit; It is for having the chip U1 of VDD pin, VSS pin, ZENER pin at least, and internal circuit comprises that triode PNP1, anode that a comparator C OMP1, base stage link to each other with the backward end of comparator C OMP1 link to each other with the emitter of triode PNP1 and the first current source i1 that negative terminal links to each other with the forward end of comparator C OMP1, the second current source i2 that anode links to each other with the backward end of comparator C OMP1 and negative terminal links to each other with the collector of triode PNP1.Peripheral circuit then comprises the mu balanced circuit between VDD pin and VSS pin, the stabilivolt Z1 that links to each other with the ZENER pin.Wherein the anode of the first current source i1 links to each other with the VDD pin simultaneously, and negative terminal then links to each other with the ZENER pin simultaneously.The negative terminal of the second current source i2 links to each other with the VSS pin simultaneously.
The electric signal VCC that sends from receiver imports from the VDD pin; Make low comparatively stable voltage difference of voltage of VDD pin of voltage ratio chip U1 of the VSS pin of chip U1 again through a mu balanced circuit, this voltage difference just as the power end (VDD pin) of chip U1 and the supply voltage of (VSS pin).The ZENER pin of chip U1 meets a stabilivolt Z1, and the ZENER pin is as high low voltage signal input end.The first current source i1 is for stabilivolt Z1 provides a WV, and the reverse pressure drop of establishing stabilivolt Z1 is VZ.Triode PNP1 is the parasitic PNP pipe of CMOS integrated circuit technology, and the second current source i2 provides working current for it, and establishing the emitter of triode PNP1 and the forward voltage drop of base stage is VEB.When the end in the same way of comparator C OMP1 equated with backward end voltage, the output OUT1 of comparator C OMP1 reached overturn point, promptly when VDD-VEB=VZ, i.e. and VDD=VEB+VZ.The high-low pressure control signal VCC that sends when satellite television receiver is during greater than VEB+VZ, and OUT1 is a low level, and the high-low pressure control signal VCC that sends when satellite television receiver is during less than VEB+VZ, and OUT1 is a high level.Just can reach the purpose of other circuit of control thus through OUT1.General VEB is 0.75V, and getting VZ is 14V, just can obtain the VREF magnitude of voltage of 14.75V.
Obviously, it is understandable that first and second current source i1, the i2 in the present embodiment can use two resistance (or claiming the 3rd, the 4th resistance) to substitute, also can realize the object of the invention.
Embodiment two: as shown in Figure 2; It is that a kind of satellite provided by the invention receives second embodiment that the control signal testing circuit combines current source circuit; Roughly similar with first example structure; It is for having the chip U1 of VDD pin, VSS pin, ZENER pin at least, the current source that internal circuit comprises triode PNP1 that a comparator C OMP1, base stage link to each other with the backward end of comparator C OMP1, is made up of second resistance R 2 and PMOS pipe P1, manages P2, P3 and manages N1 and the 2nd NMOS manages the current mirror that N2 forms by a NMOS with second and third parallelly connected PMOS of PMOS pipe P1.Wherein the collector of triode PNP1 connects the VSS pin, and the ZENER pin connects first resistance R 1 and stabilivolt Z1.
The electric signal VCC that sends from receiver imports from the VDD pin; Make low comparatively stable voltage difference of voltage of VDD pin of voltage ratio chip U1 of the VSS pin of chip U1 again through a mu balanced circuit, this voltage difference just as the power end (VDD pin) of chip U1 and the supply voltage of (VSS pin).The ZENER pin of chip U1 meets first resistance R, 1 to one stabilivolt Z1, and the ZENER pin is as high low voltage signal input end.Resistance R 2 and PMOS pipe P1 form current source; Current mirror to the two PMOS pipe P2 that produces and the 3rd PMOS pipe P3; The source-drain current of the 2nd PMOS pipe P2 is made as i1; This electric current is flowed through first resistance R 1 to stabilivolt Z1, and for stabilivolt Z1 provides a WV, the reverse pressure drop of establishing stabilivolt Z1 is VZ.The one NMOS pipe N1 and the 2nd NMOS pipe N2 form current mirror, and current mirror to the two NMOS pipe N2 with the 3rd PMOS pipe P3 is made as i2.Triode PNP1 is the parasitic PNP pipe of CMOS integrated circuit technology, and the purpose that adopts this triode PNP1 is the temperature characterisitic for compensation voltage stabilizing pipe Z1, and current i 2 is for it provides working current, and establishing the emitter of PNP1 and the forward voltage drop of base stage is VEB.When the end in the same way of comparator C OMP1 equated with backward end voltage, the output OUT1 of comparator C OMP1 reached overturn point, promptly when VDD-VEB=VZ+i1R1, i.e. and VDD=VEB+VZ+i1R1.The high-low pressure control signal VCC that sends when satellite television receiver is during greater than VEB+VZ+i1R1, and OUT1 is a low level, and the high-low pressure control signal VCC that sends when satellite television receiver is during less than VEB+VZ+i1R1, and OUT1 is a high level.Just can reach the purpose of other circuit of control through OUT1.General VEB is 0.75V, and getting VZ is 14V, as i1 fixedly the time, just can adjust the VREF magnitude of voltage as long as regulate the size of first resistance R 1, and ten minutes is flexible.The effect of diode D1, D2 is the electrostatic discharge protective circuit as the ZENER pin.
Certainly the foregoing description only is explanation technical conceive of the present invention and characteristics, and its purpose is to let the people who is familiar with this technology can understand content of the present invention and enforcement according to this, can not limit protection scope of the present invention with this.The all spirit of main technical schemes is done according to the present invention equivalent transformation or modification all should be encompassed within protection scope of the present invention.
Claims (6)
1. a satellite receives the control signal testing circuit, it is characterized in that it comprises: the triode (PNP1) that a comparer (COMP1), base stage link to each other with the backward end of comparer (COMP1), anode link to each other with the emitter of triode (PNP1) and first current source (i1)/resistance that negative terminal links to each other with the forward end of comparer (COMP1), second current source (i2)/resistance that anode links to each other with the backward end of comparer (COMP1) and negative terminal links to each other with the collector of triode (PNP1).
2. satellite according to claim 1 receives the control signal testing circuit; It is characterized in that: it is for have the chip (U1) of VDD pin, VSS pin, ZENER pin at least; Peripheral circuit then comprises the mu balanced circuit between VDD pin and VSS pin, the stabilivolt (Z1) that links to each other with the ZENER pin simultaneously.
3. satellite according to claim 2 receives the control signal testing circuit; It is characterized in that: the anode of said first current source (i1)/resistance links to each other with the VDD pin simultaneously; Negative terminal then links to each other with the ZENER pin simultaneously, and the negative terminal of second current source (i2)/resistance links to each other with the VSS pin simultaneously.
4. a satellite receives the control signal testing circuit, it is characterized in that it comprises: the triode (PNP1) that a comparer (COMP1), base stage link to each other with the backward end of comparer (COMP1), the current source of being made up of second resistance (R2) and PMOS pipe (P1), manage second and third parallelly connected PMOS of (P1) with a PMOS and manage (P2, P3) and manage (N1) and the 2nd NMOS manages the current mirror that (N2) forms by a NMOS.
5. satellite according to claim 4 receives the control signal testing circuit, and it is characterized in that: the collector of said triode (PNP1) connects the VSS pin, and the ZENER pin connects first resistance (R1) and stabilivolt (Z1).
6. satellite according to claim 5 receives the control signal testing circuit, and it is characterized in that: the resistance of said first resistance (R1) is adjustable.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110443462.7A CN102495270B (en) | 2011-12-27 | 2011-12-27 | Satellite reception control signal detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110443462.7A CN102495270B (en) | 2011-12-27 | 2011-12-27 | Satellite reception control signal detection circuit |
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| Publication Number | Publication Date |
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| CN102495270A true CN102495270A (en) | 2012-06-13 |
| CN102495270B CN102495270B (en) | 2014-08-13 |
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| CN201110443462.7A Active CN102495270B (en) | 2011-12-27 | 2011-12-27 | Satellite reception control signal detection circuit |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86105980A (en) * | 1986-09-09 | 1988-03-23 | 顾涵森 | Bioelectric signal measuring apparatus |
| JPH10233816A (en) * | 1997-02-21 | 1998-09-02 | Sharp Corp | Digital satellite receiver |
| US5974095A (en) * | 1995-09-26 | 1999-10-26 | Sharp Kabushiki Kaisha | Digital satellite broadcasting receiver |
| CN101060347A (en) * | 2006-04-17 | 2007-10-24 | 阿尔卑斯电气株式会社 | AM and FM broadcast receiving circuit |
| JP2008206359A (en) * | 2007-02-22 | 2008-09-04 | Mitsumi Electric Co Ltd | Current limiting circuit and integrated circuit device using the same |
| CN201146499Y (en) * | 2008-01-15 | 2008-11-05 | 青岛海信电器股份有限公司 | Polarization mode selection circuit and satellite receiver containing the same |
| CN101393466A (en) * | 2008-10-30 | 2009-03-25 | 上海交通大学 | Fully integrated low-noise power system in RF receiver chip |
| CN201886372U (en) * | 2010-09-25 | 2011-06-29 | 苏州华芯微电子股份有限公司 | Band-gap reference voltage detection circuit |
-
2011
- 2011-12-27 CN CN201110443462.7A patent/CN102495270B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86105980A (en) * | 1986-09-09 | 1988-03-23 | 顾涵森 | Bioelectric signal measuring apparatus |
| US5974095A (en) * | 1995-09-26 | 1999-10-26 | Sharp Kabushiki Kaisha | Digital satellite broadcasting receiver |
| JPH10233816A (en) * | 1997-02-21 | 1998-09-02 | Sharp Corp | Digital satellite receiver |
| CN101060347A (en) * | 2006-04-17 | 2007-10-24 | 阿尔卑斯电气株式会社 | AM and FM broadcast receiving circuit |
| JP2008206359A (en) * | 2007-02-22 | 2008-09-04 | Mitsumi Electric Co Ltd | Current limiting circuit and integrated circuit device using the same |
| CN201146499Y (en) * | 2008-01-15 | 2008-11-05 | 青岛海信电器股份有限公司 | Polarization mode selection circuit and satellite receiver containing the same |
| CN101393466A (en) * | 2008-10-30 | 2009-03-25 | 上海交通大学 | Fully integrated low-noise power system in RF receiver chip |
| CN201886372U (en) * | 2010-09-25 | 2011-06-29 | 苏州华芯微电子股份有限公司 | Band-gap reference voltage detection circuit |
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| CN102495270B (en) | 2014-08-13 |
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