CN102487005A - Method for enhancing n channel electronic activity - Google Patents
Method for enhancing n channel electronic activity Download PDFInfo
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- CN102487005A CN102487005A CN2010105684201A CN201010568420A CN102487005A CN 102487005 A CN102487005 A CN 102487005A CN 2010105684201 A CN2010105684201 A CN 2010105684201A CN 201010568420 A CN201010568420 A CN 201010568420A CN 102487005 A CN102487005 A CN 102487005A
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 230000000694 effects Effects 0.000 title abstract description 8
- 230000002708 enhancing effect Effects 0.000 title abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005280 amorphization Methods 0.000 claims abstract description 7
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 238000000137 annealing Methods 0.000 claims description 24
- -1 silicon ion Chemical class 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract description 25
- 125000006850 spacer group Chemical group 0.000 abstract description 6
- 238000002513 implantation Methods 0.000 abstract description 3
- 239000002344 surface layer Substances 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000000465 moulding Methods 0.000 description 5
- 229910021334 nickel silicide Inorganic materials 0.000 description 4
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910001453 nickel ion Inorganic materials 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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Abstract
The invention provides a method for enhancing n channel electronic activity. The method comprises the following steps that: an offset spacer is formed around a polysilicon gate above a substrate that is at the position of an n channel; a main spacer is formed; source and drain implantation is carried out; the main spacer is removed; a tension force layer is deposed on the surface layer of the substrate; the tension force layer on the surface layer of the substrate is removed; amorphization processing is carried out on the surface layer of the substrate; and nickle silicide is respectively formed on the top, the source electrode and the drain electrode of the polysilicon gate. According to the invention, a tension force layer is directly applied on a polysilicon gate, wherein a protection layer of a main spacer of the polysilicon gate has been removed; therefore, a technical bottleneck of a tensile stress of a n channel in the prior art can be solved, so that activities of electrons in the n channel can be effectively enhanced.
Description
Technical field
The present invention relates to a kind of nMO SFET (n metallic oxide semiconductor field effect transistor; N NMOS N-channel MOS N field-effect transistor) processing method is specifically related to the active method of n channel electrons among a kind of nMOSFET of enhancing.
Background technology
At present, along with updating of processing technology, the processing of integrated circuit has got into the epoch of 65/45 nanometer (nm) technology, and nickel silicide (NiSi) is just becoming the selection material that contact is used.As majority carrier, thereby raceway groove is the n type to nMOSFET with electronics.Along with the size of MOSFET constantly reduces, the someone adopts following method to increase the electron mobility of n raceway groove, shown in Fig. 1-5: around polysilicon gate 101, form compensation side wall 102 (offset spacer) protective layer, as shown in Figure 1; Form master wall 105 (main spacer) in said compensation side wall 102 outsides, as shown in Figure 2; Carry out the source, leak to implant, form source electrode 103 and drain electrode 104, as shown in Figure 3, then silicon chip surface is carried out annealing in process, with activation grid and source, drain electrode; Have the silicon nitride layer 106 of tension force at silicon chip top layer deposit one deck, as shown in Figure 4, the lattice at stretching n raceway groove place improves the electronics operating rate; And then carry out annealing in process, and the lattice structure at n raceway groove place is fixed, the tensile stress to the n raceway groove (tensile stress) that silicon nitride layer 106 is introduced is maintained and remembers; Get rid of the silicon nitride layer of the superiors; And, form nickel silicide through annealing then to the top of polysilicon gate 101, source electrode and drain electrode sputtering deposit metallic nickel respectively, and nickel silicon (NiSi) 107, as shown in Figure 5.The forming process of nickel silicide to the source, leak silicon consumption less, and just be the maximum zone of doping content, thereby very favourable for reducing whole contact resistance near the silicon on surface.The follow-up processing steps such as deposit moulding that carry out ground floor inter-level dielectric oxide are not in addition given unnecessary details at this.At this moment the lattice structure in the n raceway groove compare when not applying tensile stress looser, so can be through said method so that the mobility of the electronics in the n raceway groove (mobility) gets a promotion, the electronically active in the n raceway groove is enhanced.
But; The method of technique scheme is limited for the raising of the electron mobility in the n raceway groove; Specifically, because the existence of master wall 105 protective layers around the polysilicon gate of moulding, silicon nitride layer can not be directly to the polysilicon gate effect; These master wall 105 protective layers have been accepted the tensile stress from silicon nitride layer 106 of major part, and the tensile stress that causes the n raceway groove to form is limited.In addition, even if can continue to increase the tension force of silicon nitride layer, the crack also appears in polysilicon gate edge more easily along with the increase of tension force, if the crack produces the end product quality that will have a strong impact on nMOSFET.That is to say that the limited tensile stress that 106 of silicon nitride layers can provide has been accepted greatly by master wall 105 protective layers, and then causes the lifting of the electron mobility in the n raceway groove to run into bottleneck.
In the above-mentioned prior art, utilize nickel silicon 107 is used in transistorized top, source electrode and drain electrode, in order that the finished product transistor has more low current impedance.The purpose of master wall 105 protective layers that post forming forms around polysilicon is that break-through is leaked in the source that causes in order to prevent sputtering deposit metallic nickel generation diffusion in the subsequent technique.
Also has a kind of in addition method that prevents the nickel ion diffusion in the prior art; Be the silicon chip amorphous method, wherein a kind of method is that silicon ion is implanted technology (Si ion implantation, Si I.I.); This silicon ion is implanted technology specifically; Be before the sputtering deposit metallic nickel, at first implanted silicon ion on silicon chip makes silicon chip surface decrystallized.Make sputtering deposit in the subsequent technique in the source, the metallic nickel of drain electrode can not spread in substrate, just can not leak break-through in the generation source yet.
Summary of the invention
In view of this; The lifting that the present invention is directed to the electron mobility in the n raceway groove in the prior art runs into the technical problem of bottleneck; Provide a kind of and shell of tension is acted directly on the polysilicon gate, improved this shell of tension the tensile stress in the n raceway groove through exempting the processing step of master wall protective layer; And then improved the mobility of n channel electrons, strengthened the active method of n channel electrons.
For achieving the above object, technical scheme provided by the invention is following:
A kind of active method of n channel electrons that strengthens may further comprise the steps:
Form the compensation side wall around the polysilicon gate above the substrate of n raceway groove position;
Form the master wall in the said compensation side wall outside;
Carry out the source, leak and implant;
Get rid of said master wall;
At underlayer surface deposit one deck shell of tension;
Substrate is carried out annealing in process;
Get rid of the said shell of tension of underlayer surface;
Underlayer surface is carried out amorphisation;
Top, source electrode and drain electrode at said polysilicon gate form nickle silicide respectively.
Preferably, the tension force of said shell of tension is the 1.0-2.0 giga pascals.
Preferably, the pressure of reaction cavity is controlled at the 1-7 holder during said shell of tension deposit.
Preferably, said shell of tension is silicon nitride layer or silicon oxide layer.
Preferably, said shell of tension adopts gas ions chemical gas-phase deposition enhanced or the deposit of accurate normal pressure chemical gas-phase deposition method, and the temperature during said shell of tension deposit is 400-550 degree centigrade.
Preferably, the said annealing in process after the step of underlayer surface deposit one deck shell of tension is specially spike annealing or laser annealing.
Preferably, the treatment temperature of the said annealing in process after the step of underlayer surface deposit one deck shell of tension is 900-1200 degree centigrade.
Preferably, in the said step of getting rid of said master wall, specifically be to adopt the method for plasma etching or wet etching to remove said master wall.
Preferably, said underlayer surface being carried out amorphisation, specifically is to adopt to substrate surface implanted silicon ion or germanium ion or nitrogen ion.
Preferably, the degree of depth to substrate surface implanted silicon ion or germanium ion or nitrogen ion is the 150-250 nanometer.
In the technique scheme, giga pascals is GPa; Holder is Torr, and 1 holder approximates 1.316 * 10
-3Atmospheric pressure or 133.322 Pascals.
In the technique scheme, spike annealing English is spike anneal, and laser annealing English is laser anneal, and these two kinds of annealing way can make the wafer cooling immediately that is rapidly heated then.
The active method of enhancing n channel electrons of the present invention has following beneficial effect:
The active method of enhancing n channel electrons of the present invention; Be utilized in substrate (silicon chip) top layer deposit one deck shell of tension; And shell of tension acted directly on the polysilicon gate of having removed the master wall; Make it more directly produce tensile stress, improve the technical bottleneck of the tensile stress of n raceway groove in the prior art, thereby effectively strengthened the activity of electronics in the n raceway groove thereby overcome to n raceway groove on the substrate.
Description of drawings
Fig. 1-the 5th strengthens the active method flow sketch map of n channel electrons in the prior art;
Fig. 6-the 12nd, the active method flow sketch map of enhancing n channel electrons of the present invention.
Embodiment
The active method of enhancing n channel electrons of the present invention; Utilization acts directly on shell of tension (silicon nitride layer) on the polysilicon gate of having removed the master wall; More directly the n raceway groove is produced tensile stress; Overcome and improved the technical bottleneck of the tensile stress of n raceway groove in the prior art, thereby effectively strengthened the activity of electronics in the n raceway groove.
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
Embodiment 1
Fig. 6-12 has shown the active method of a kind of n of enhancing channel electrons of the present invention, specifically comprises the steps:
One, forming on every side of the polysilicon gate above the silicon chip substrate of n raceway groove position 201 compensates side wall 202, and be as shown in Figure 6.The material of said compensation side wall 202 is silicon dioxide or silicon nitride or their combination; With silicon dioxide is example, and the generation method of said compensation side wall 202 is through to wafer deposition silicon dioxide, utilizes dry etch process to anti-carve then, after polysilicon exposes, stops to anti-carve obtaining.Owing to using ion sputtering, used anisotropic etching instrument fallen most silicon dioxide in the said process, so do not need mask; What anti-carve removal is not whole silicon dioxide, has kept a part of silicon dioxide around the polysilicon gate.
Two, form master wall 205 (material of compensation side wall 205 is silicon dioxide or silicon nitride or their combination, and its preparation method is with the forming method of above-mentioned compensation side wall 202) in said compensation side wall 202 outsides, as shown in Figure 7.
Three, carry out source, leakage implantation, form source electrode shown in Figure 7 203 and drain electrode 204, as shown in Figure 8, afterwards silicon chip is carried out annealing in process, with activation source, drain electrode.
Four, adopt plasma etching or wet etching, get rid of said master wall 205, as shown in Figure 9, only remaining said compensation side wall 202 is in said polysilicon gate 201 outer periphery.
Five, adopt gas ions chemical gas-phase deposition enhanced PECVD or accurate normal pressure chemical vapor deposition SACVD method, at silicon chip top layer deposit one deck silicon nitride layer 206, promptly shell of tension is shown in figure 10.Temperature during deposit is 400-550 degree centigrade; The tension force of the said silicon nitride layer 206 that deposit goes out is 1.0-2.0 giga pascals (GPa), makes the lattice structure at n raceway groove place obtain stretching, and becomes looser.The pressure of reaction chamber is controlled at 1-7 holder (Torr) during these silicon nitride layer 206 deposits.Certainly, in other embodiment, above-mentioned silicon nitride layer also can replace with silicon oxide layer, and it can play the effect that tensile stress is provided for the n raceway groove equally.
Six, adopt spike annealing or laser annealing, under 900-1200 degree centigrade, silicon chip is carried out annealing in process, make the lattice structure at stretched said n raceway groove place obtain fixing and memory.
Seven, get rid of the said silicon nitride layer 206 on silicon chip top layer, shown in figure 11.
Eight, shown in figure 11, at this moment amorphisation is carried out on the silicon chip top layer, promptly to silicon chip surface implanted silicon ion (Si
+), implantation depth is the 150-250 nanometer.Certainly, in other embodiment, the above-mentioned ion processing silicon ion (Si that implants to silicon chip surface
+) outside, also can be germanium ion (Ge
+) or nitrogen ion (N
+), it all can be decrystallized with silicon chip surface.
Nine, to top, source electrode and the drain electrode difference sputtering deposit metallic nickel of polysilicon gate 201,, form nickel silicon 207 at above-mentioned position then through twice annealing, shown in figure 12.Before the annealing in process of said nickel silicon 207 is still continued to use silicon chip is stepped back the similar double annealing technology of processing, but annealing temperature there has been obvious reduction (＜600 ℃), so just significantly reduces the destruction to the established ultra shallow junction of device.From the angle of kinetics of diffusion, short annealing time can suppress ions diffusion effectively.Therefore, spike annealing (spike anneal) is applicable to the annealing process first time in the above-mentioned nickel silicide moulding twice annealing.
Next be the subsequent process steps such as deposit moulding of carrying out ground floor inter-level dielectric oxide, do not give unnecessary details at this.
Utilization of the present invention acts directly on shell of tension on the polysilicon gate of having removed the master wall; More directly the n raceway groove is produced tensile stress; Then; Utilization is carried out amorphisation with silicon chip surface, forms the method for nickel silicon afterwards again, the spreading of nickel ion in the silicon chip of nickel silicon that effectively prevented moulding.Method of the present invention acts directly on the silicon chip of having removed the master wall with shell of tension under the prerequisite of having avoided the nickel ion diffusion, and the lattice structure of the n raceway groove position that more directly stretched has effectively strengthened the activity of electronics in the n raceway groove.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.
Claims (10)
1. one kind strengthens the active method of n channel electrons, it is characterized in that, may further comprise the steps:
Form the compensation side wall around the polysilicon gate above the substrate of n raceway groove position;
Form the master wall in the said compensation side wall outside;
Carry out the source, leak and implant;
Get rid of said master wall;
At underlayer surface deposit one deck shell of tension;
Substrate is carried out annealing in process;
Get rid of the said shell of tension of underlayer surface;
Underlayer surface is carried out amorphisation;
Top, source electrode and drain electrode at said polysilicon gate form nickle silicide respectively.
2. method according to claim 1 is characterized in that, the tension force of said shell of tension is the 1.0-2.0 giga pascals.
3. method according to claim 1 is characterized in that, the pressure of reaction cavity is controlled at the 1-7 holder during said shell of tension deposit.
4. according to the arbitrary described method of claim 1-3, it is characterized in that said shell of tension is silicon nitride layer or silicon oxide layer.
5. method according to claim 4 is characterized in that, said shell of tension adopts gas ions chemical gas-phase deposition enhanced or the deposit of accurate normal pressure chemical gas-phase deposition method, and the temperature during said shell of tension deposit is 400-550 degree centigrade.
6. method according to claim 1 is characterized in that, the said annealing in process after the step of underlayer surface deposit one deck shell of tension is specially spike annealing or laser annealing.
7. method according to claim 6 is characterized in that, the treatment temperature of the said annealing in process after the step of underlayer surface deposit one deck shell of tension is 900-1200 degree centigrade.
8. method according to claim 1 is characterized in that, in the said step of getting rid of said master wall, specifically is to adopt the method for plasma etching or wet etching to remove said master wall.
9. method according to claim 1 is characterized in that, said underlayer surface is carried out amorphisation, specifically is to adopt to substrate surface implanted silicon ion or germanium ion or nitrogen ion.
10. method according to claim 9 is characterized in that, is the 150-250 nanometer to the degree of depth of substrate surface implanted silicon ion or germanium ion or nitrogen ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105684201A CN102487005A (en) | 2010-12-01 | 2010-12-01 | Method for enhancing n channel electronic activity |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105684201A CN102487005A (en) | 2010-12-01 | 2010-12-01 | Method for enhancing n channel electronic activity |
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| CN102487005A true CN102487005A (en) | 2012-06-06 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465517A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1892998A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure or element |
| CN1925159A (en) * | 2005-08-30 | 2007-03-07 | 株式会社东芝 | Semiconductor device and method of fabricating same |
| US20070254461A1 (en) * | 2006-04-28 | 2007-11-01 | Andy Wei | Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same |
-
2010
- 2010-12-01 CN CN2010105684201A patent/CN102487005A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1892998A (en) * | 2005-07-06 | 2007-01-10 | 台湾积体电路制造股份有限公司 | Method of forming semiconductor structure or element |
| CN1925159A (en) * | 2005-08-30 | 2007-03-07 | 株式会社东芝 | Semiconductor device and method of fabricating same |
| US20070254461A1 (en) * | 2006-04-28 | 2007-11-01 | Andy Wei | Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465517A (en) * | 2013-09-23 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN104465517B (en) * | 2013-09-23 | 2017-08-25 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
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