CN102480272B - 射频放大器 - Google Patents
射频放大器 Download PDFInfo
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- CN102480272B CN102480272B CN201110384941.6A CN201110384941A CN102480272B CN 102480272 B CN102480272 B CN 102480272B CN 201110384941 A CN201110384941 A CN 201110384941A CN 102480272 B CN102480272 B CN 102480272B
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Abstract
本发明涉及高功率射频放大器,特别涉及多赫蒂放大器电路,本发明的示例性实施例包括具有工作频率的集成射频放大器(1200),该放大器包括第一和第二多赫蒂放大器(1201a,1201b),每个多赫蒂放大器包括主器件和峰值器件,主器件和峰值器件通过相应的相移元件在各自的输入和输出处连接的主器件和峰值器件,相移元件配置为在工作频率下提供90度的相移,其中放大器(1200)的输入(1202)连接到第一多赫蒂放大器(1201a)的主器件的输入,放大器的输出(1205)连接到第一和第二多赫蒂放大器(1201a,1201b)的峰值器件的输出,第一多赫蒂放大器(1201a)的峰值器件输入通过相移元件(1204)连接到第二多赫蒂放大器(1201b)的主器件输入,该相移元件配置为在工作频率下提供90度的相移。
Description
技术领域
本发明涉及高功率射频放大器,具体但不排他地涉及多赫蒂(Doherty)放大器电路。
背景技术
多赫蒂型放大器由于其在处理多载波无线通信系统中常用的可变功率水平时具有更高的效率,被广泛用于无线通信中的功率放大器。多赫蒂放大器包括主放大器和峰值放大器,主放大器处理直到某一转变点的功率水平,在功率水平处于转变点之上且直至多赫蒂放大器饱和点时,峰值放大器将其功率加到加载上。主放大器和峰值放大器典型地按不同类运行,且相比于类似设定的单级AB类放大器或A类放大器,它们能够一起传递经改善的补偿(back-off)功率水平效率。
WO 2008/062371更详细地描述了多赫蒂放大器的原理,并披露这样的实施例,其中并联配置多路放大器以允许在高功率下具有更宽的射频带,从而减少调谐问题。
高功率射频放大器,例如多赫蒂放大器以及单端AB类放大器,易于表现出电记忆效应,这种效应在1GHz及以上频率的高功率射频放大器中尤其存在问题。这些记忆效应起因于电源和放大器的功率器件之间存在的寄生电感,以及起因于放大器电流消耗(跟随输入信号调制的包络)的强度和变化速度。这种寄生电感可能作为电源网络的一部分存在。在更高调制频率下,由于这种记忆效应,会趋向于出现更大的失真。由于峰值放大器运行在C类模式中,多赫蒂放大器易于表现出更高的记忆效应。
A.Khanifar等人发表的″Bias Circuit Topologies for Minimizationof RF Amplifier Memory Effects″,33 European Microwave Conference,Munich 2003,pp 1349-1352中披露了一种用于处理射频放大器中记忆效+应的电路技术,该技术中,在偏置网络传递函数中设置传输零点,通过利用去耦电容器的串联谐振属性形成器件输出的传输零点。
单端AB类放大器和多赫蒂放大器的工作频带尤其受限于匹配网络,匹配网络可能要求50和100之间的阻抗变换系数。O.Pitzalis和R.Gilson在″Broad-Band Microwave Class-C Transistor Amplifiers″,IEEETransactions on Microwave Theory and Techniques,Vol.MTT-21,No.11,November 1973中披露了用于宽带输入和输出匹配结构的大信号晶体管表征和设计的技术。工作在GHz范围的传统多赫蒂放大器中的高功率(100到300W)分立功率器件典型的需要高阻抗变换系数,这往往限制了放大器的带宽。此外,根据Bode-Fano理论:
其中,ω1,ω2是频率的下限和上限,Γ是反射系数,RL、Cds是功率器件的最佳负载电阻和寄生输出电容(例如,漏极到源极电容)。例如,如US7078976中所述,如果工作频率下的Cds阻抗与RL相当,则其可以用作集总元件多赫蒂组合器的一部分,这使得Cds的负面效应得以最小化。
根据下述关系式,由四分之一波长阻抗变换器实现的两个阻抗ZL和Zo的给定阻抗变换系数会限制在所需工作频率fo和反射系数Γm下的可用带宽Δf:
例如,如果150W器件输出下的阻抗变换系数是50,即从1Ω变换到50Ω,则该器件的输出在3%的效率损失下允许低于7%的带宽。
根据阻抗变换理论,可以通过引入无限数目的变换步骤来提高带宽。但是,使用超过3个的变换步骤不会带来显著的带宽改善,反而使得匹配网络的相位-频率响应更加依赖于频率,这进一步限制了其中可以通过峰值器件有效调制主器件负载线(load line)的频带。
传统的多赫蒂放大器具有用于阻抗匹配的分布式传输线,这种分布式传输线在设计为运行在1GHz频率下时,比运行在2GHz频率下时要求大约2倍的面积。这是由于传输线所需要的物理尺寸在较低频率下变得更大。这就对射频放大器,特别是用于移动通信设备的射频放大器(可以使用从0.4到2.7GHz的射频带的较低部分)的小型化带来了问题。如US 7443264中所述,在较高介电常数电路板上用于1GHz的四分之一波长50Ω微带线可以占用大约5mm×37mm的面积,该面积在要求使用较低阻抗的情况下可能需要加倍乃至更大。US 7443264进一步披露了紧凑型阻抗变换电路,该电路包括并行导线键合(parallel wire bonds)和MOS电容器的组合。
由具有50W以上功率水平的分立功率器件构成的传统多赫蒂放大器还倾向于具有较窄的相对射频带宽,对于由分别额定为100W的两个器件构成的传统多赫蒂放大器来说,相对射频带宽典型的在7%左右。但是,例如由于在把主器件和峰值器件的输出连接到多赫蒂组合器的阻抗匹配中需要更高的变换系数,带宽甚至可以更小。因此,由分立功率器件构成的高功率传统多赫蒂放大器在250W左右或更高的输出功率水平下不能输出超过10%的工作带宽。对于更高的功率输出水平,可用的带宽变得更为受限。
US 7119623披露了用于高功率半导体放大器元件的输出电路,其中电感和电容配置为补偿半导体放大器元件的输出电容,以抑制放大器的输出信号中不想要的谐波。US 7078976披露了具有集成输出多赫蒂组合器的高功率多赫蒂器件,该多赫蒂组合器包括配置为仿真(artificial)传输线的电容和电感,该组合器直接连接到主器件和峰值器件的输出,结果,在具有补偿LC网络的情况下允许最多40%的宽工作频带。这种具有特定LC值的补偿网络也可用于将电源连接到器件漏极,从而允许具有低电记忆效应的宽带视频解耦。
例如在WO 2008/062371中披露的,已经证明LDMOS技术的集成多赫蒂放大器在2GHz下,可以表现出高达20%的相对带宽。带宽受限于输入功率分割网络,而输出网络允许30%的带宽,这一点已经例如在US 7078976中以及在J.Qureshi等人的″A Wide-Band 20W LMOS Doherty PowerAmplifier″,International Microwave Symposium,May 23-28 2010,Anaheim,California中有更详细的描述。
在1GHz下,类似的方法需要在7到16nH范围内的电感值。由于需要大量的面积,难以以集成的方式实现这些取值。输入也会趋向于产生约15%的受限带宽。
根据上文给出的Bode-Fano关系式,基于FET的RF功率放大器(例如基于LDMOS技术)的输入阻抗的高Q因数倾向于限制放大器的工作带宽。其中,串联RC表示FET器件(例如LDMOS、MOS、GaAs FET、或PHEMT)的等效输入网络:
典型的LDMOS器件在2GHz下表现出6左右的Q因数,在1GHz下表现出12左右的Q因数。结果,如下表所示,输入网络在1GHz下的带宽非常窄,而所需要的带宽可能是200MHz或更多。
含有一对这种器件的集成多赫蒂放大器的输入网络运行也受限于大约相同的带宽,这是由于输入功率分配网络的阻抗变换属性导致的。虽然会导致功率增益的损失,但是可以通过在这些器件的输入处引入阻性损耗来部分地改善带宽。如上所述,增加阻性终端以改善带宽对于典型应用来说可能导致大约5dB的功率损失。
本说明书中,对于已发表文献的列举或讨论不应被必然认为是承认这些文献是现有技术的一部分或者属于公知常识。
发明内容
本发明的目的是解决一个或多个上述问题。
根据本发明的第一方面,提供了一种具有工作频率的集成射频放大器,该放大器包括第一和第二多赫蒂放大器,每个多赫蒂放大器包括主器件和峰值器件,主器件和峰值器件通过相应的相移元件在各自的输入和输出处连接,相移元件配置为在工作频率下提供90度的相移,
其中,放大器的输入连接到第一多赫蒂放大器的主器件的输入,放大器的输出连接到第一和第二多赫蒂放大器的峰值器件的输出,第一多赫蒂放大器的峰值器件的输入通过相移元件连接到第二多赫蒂放大器的主器件的输入,该相移元件配置为在工作频率下提供90度的相移。
连接到第一和第二多赫蒂放大器的主器件和峰值器件的输入和输出的相移元件优选地配置为提供负相移。连接第一多赫蒂放大器的峰值器件输入与第二多赫蒂放大器的主器件输入的相移元件优选的配置为提供正相移。
这种构造的放大器通过将会在阻性终端中损失的功率转向另一多赫蒂放大器输入以对该功率进行重复利用,从而解决了上述功率增益损失的问题。从而,能够提高放大器的整体增益。
放大器的每个主器件和峰值器件可以包括场效应晶体管(FET)、双极结型晶体管(BJT)、异质结双极晶体管(HBT)或高电子迁移率晶体管/异质场效应晶体管(HEMT/HFET)。
放大器可以扩展为包括一个或多个另外的多赫蒂放大器,其中每个另外的放大器电路具有峰值器件输出和主器件输入,峰值器件输出连接到放大器输出,主器件输入通过相移元件连接到在前(preceding)的多赫蒂放大器的峰值器件输入,该相移元件配置为在工作频率下提供同样为90度、但与主器件和峰值器件之间的多赫蒂输入处所使用的相移符号相反的相移。通过添加这种另外的多赫蒂放大器可以进一步的重复利用会损失的功率,尽管每个附加放大器对于该功率损耗具有递减的效果。结果,多赫蒂放大器的优选数量是2或3,并且优选地为4或更少。
连接每个多赫蒂放大器的主器件输出和峰值器件输出的相移元件可以包括串联连接到主器件和峰值器件输出的一对电感,以及在连接该对电感的中间节点与放大器的地平面连接之间连接的电容。
连接每个多赫蒂放大器的主器件输入与峰值器件输入的相移元件可以包括含有电感的低通滤波器。通过与主器件和峰值器件的栅极电阻和电容相结合,该电感提供了在放大器的工作频率下所要求的90度相移。
连接第一多赫蒂放大器的峰值器件输入与第二多赫蒂放大器的主器件输入的相移元件可以包括高通滤波器,其包括分别连接在放大器的地平面连接和一电容相对两端之间的一对电感。
应注意到,低通滤波器可以用高通滤波器代替,反之亦然。
通过将高通和低通滤波器元件相结合,并共同用作在多赫蒂放大器之间对功率进行引导的链路,使得相对于现有的方案允许宽带群时延和减小输入功率损耗。
具有集成射频放大器的电路可以包括电源网络,其中每个多赫蒂放大器的主器件和峰值器件的输出端子通过电源线电路连接到电源网络,该电源线电路配置为在多赫蒂放大器的工作频率下提供相移,该电源线电路优选地包括一对耦合导体。导体可以是相互磁耦合和电耦合的电感的形式。导体之间的相互耦合大大强于例如每个导体与地平面之间的耦合。电源线电路可选地可以包括具有特性阻抗的分布式传输线或分布式传输线的等效集总元件。电源线电路优选地提供高“偶”模式传播特性阻抗和低“奇”模式传播特性阻抗。
使用根据本发明的电源线电路的一个优势是能减小整体的电源线电感,结果,可以减小记忆效应。
电源线电路可以包括一对相互耦合的电感和在连接该对电感的节点与地连接之间连接的电容,其中电源线电路形成为分布式传输线的等效集总元件。该对电感可以设置为平行的键合导线,或者可选地设置为形成在基板上并由电介质层隔开的一对导体。该对导体和电介质层在某些实施例中可以在基板上形成为环状。
电源线电路可以可选地包括多个相互耦合的电感对以及在各电感对之间连接的电容。电感对可以设置为在基板上形成并由电介质层隔开的导体堆叠。
电源线电路可以包括四分之一波长传输线的等效集总元件。因此,电源线电路可以包括:
第一并行磁耦合电感对;
与第一并行电感对串联连接的第二并行磁耦合电感对;和
在每个并行电感对的节点之间的电容。
电源线电路可以包括平行布置并经由键合焊盘串联电连接的一对导线键合,其中键合焊盘提供容性接地。电源线电路可以直接连接到主放大器或峰值放大器的漏极连接。
附图说明
下面通过示例性实施例的方式并参照附图来更详细地描述本发明,在附图中:
图1是单端放大器的示意性电路图,其具有通过传输线连接的电源;
图2是单端放大器的示意性电路图,其具有通过低记忆效应电源线连接的电源;
图3是多赫蒂放大器的示意性电路图,其具有通过低记忆效应电源线连接到峰值放大器的电源;
图4是集总元件电路图,其表示在图3的多赫蒂放大器的主放大器和峰值放大器输出之间的阻抗匹配网络;
图5a是宽带传输线电源线电路的等效集总元件的示意图,该宽带传输线电源线电路包括一对耦合的导线键合连接,该对导线键合连接平行排列并通过容性接地的键合焊盘串联连接;
图5b是图5a的传输线电路的示意性电路图;
图5c是图5b的传输线的可选实施例的示意图,其包括在衬底上由电介质层隔离的宽边耦合导体;
图6a是配置为提供四分之一波长相移的电源传输线的示意图;
图6b是图6a的电源传输线的示意性电路图;
图6c是可选电源传输线的示意图,该电源传输线的形式为由电介质层隔离的宽边耦合导体对的交错堆叠;
图7是一示例性多赫蒂放大器的示意性透视图,其包括不同管芯上的主器件、峰值器件和电源;
图8是布置为宽带工作的另一示例性多赫蒂放大器的示意性透视图;
图9a是多赫蒂放大器的示意性电路图,其在放大器的主器件和峰值器件之间具有输入相移元件;
图9b是多赫蒂放大器的示意性电路图,其在放大器的主器件和峰值器件之间具有可选输入相移元件;
图10a是图9b的多赫蒂放大器的主器件和峰值器件之间的相移作为频率函数的仿真曲线图;
图10b是图9b的多赫蒂放大器的主器件和峰值器件的峰值栅电压作为频率函数的仿真曲线图;
图11是通过集总元件传输线串联连接的多个多赫蒂放大器的示意性电路图,其中集总元件传输线包括低通和高通相移元件链路;
图12是包括第一和第二多赫蒂放大器的集成多赫蒂放大器电路的示意性电路图,其中第一和第二多赫蒂放大器具有通过输入相移元件连接的输入;
图13是针对根据本发明实施例的集成多赫蒂放大器,功率增益作为输出功率函数的仿真曲线图;
图14是针对根据本发明实施例的集成多赫蒂放大器,功率增加效率作为输出功率函数的仿真曲线图;
图15是包括第一和第二多赫蒂放大器的可选集成多赫蒂放大器电路的示意性电路图,其中第一和第二多赫蒂放大器具有通过输入相移元件连接的输入;
图16是包括第一和第二多赫蒂放大器的另一可选集成多赫蒂放大器电路的示意性电路图,其中第一和第二多赫蒂放大器具有通过输入相移元件连接的输入;和
图17是布置为宽带工作的另一可选示例性多赫蒂放大器的示意性透视图。
具体实施方式
图1所示是一示例性单端放大器100的示意性电路图。放大器100包括放大器件管芯(die)101和输出阻抗匹配电路103,放大器件管芯101具有输入连接102,输出阻抗匹配电路103连接在器件管芯101和输出连接104之间。电源105通过电源线106连接到输出阻抗匹配电路103,电源线106包括低通LC电路108和四分之一波长传输线109。
图2中所示是放大器200的示意性电路图,放大器200包括通过电源线电路206连接到有源器件管芯201的电源205。有源器件201的漏极或集电极端子通过集成电源线206连接到电源205。电源线206优选地设置在与集成多赫蒂器件相同的半导体管芯上,该集成多赫蒂器件包括一对这样的有源器件,假设电源205在与有源器件201的公共端子(源极或发射极)相同的位置连接到参考平面或地平面。放大器200包括具有输入连接202和输出连接204的放大器件管芯201。电源线电路206可以通过一个或多个串联连接的磁耦合并行电感L对来表示,并在电感的节点之间具有电容C。电源线电路206配置为提供一定的电长度以在放大器200的工作频率下在放大器件管芯201和电源205的输出端子之间提供四分之一波长相移。相比于使用图1的电源线电路106,使用电源线电路206对于放大器件管芯具有最小的电感属性和较低的记忆效应的优点。电源线电路206直接连接到放大器件管芯201的漏极端子211和源极端子212。
图3所示是一示例性集成多赫蒂放大器件300的示意性电路图。放大器件300包括主放大器301和峰值放大器302,它们设置在作为集成电路封装一部分的单个管芯上。主放大器301和峰值放大器302的输出303、304通过多赫蒂组合器网络305连接,该多赫蒂组合器网络305包括一对电感,这对电感的每一侧容性接地。组合器网络305的等效电路以图4的示意性电路图来示出,图4示出了构成网络305的每个LC电路提供了45度的相移,从而在主放大器和峰值放大器的输出303、304之间共提供了90度(四分之一波长)相移。
电源307通过电源线电路306连接到峰值器件302的输出(或漏极连接)304和源极连接308。电源线电路与图2的电源线电路206类似。
如同传统的多赫蒂放大器,图3中的多赫蒂放大器300具有连接到主放大器301的第一输入311和连接到峰值放大器302的第二输入312。施加到第一和第二输入311、312上的信号相对于彼此具有90度相移。
图5a所示是在基板500上具有一对导线键合连接501、502的示例性电源线电路的示意图。第一导线键合连接501设置在第一键合焊盘503和第二键合焊盘504之间。第二导线键合连接502设置在第二键合焊盘504和第三键合焊盘505之间。容性连接506设置在第二键合焊盘504和地连接508之间。通过连接在第二键合焊盘504的相对两端处,第一和第二导线键合连接501、502在电气上串联连接且在物理上并行布置。该并行结构允许导线键合连接501、502之间的磁耦合507。
图5b以示意性电路图的形式示出了图5a的电源线电路,其中导线键合连接501、502被表示为一对耦合电感,以及容性连接506被表示为连接在这两个电感之间的接地电容。
图5c示出了电源线电路的可选实施例,该电源线电路具有屏蔽宽边(broadside)耦合导体带510a、510b,以代替图5a中的耦合键合导线501、502。导体带510a、510b设置在基板511上并被电介质层512隔开。在所示实施例中,导体带510a、510b设置为基板511上的环堆叠形式。如同图5a的键合导线的实施例,导体带510a、510b串联连接,并在导体带510a、510b彼此连接的位置处具有接地的容性连接512。这种布置的优点是导体带比键合导线实施例占用基板511上更少的垂直空间。通过向堆叠添加更多的导体带,可以向图5c的实施例添加其他的导体带,同时使得电源线电路所占用的整体空间的变化最小,其中每个附加的导体带通过另外的电介质层与之下的导体带隔开。
图6a示例性示了用作图3的集成多赫蒂放大器的电源线电路的示例性传输线601。传输线601连接到电源602,并提供连接到多赫蒂放大器的主放大器件或峰值放大器件管芯的漏极和电源连接的输出连接605、606。传输线601形成为一对平行导电板603、604,该对导电板在图6b的示意性电路图中呈现为串联连接的并行电感对,电感对中的电感之间具有电容连接。并行电感在图6b中也表示为磁耦合,如同图5a和5b的电源线电路的导线键合连接501、502和图5c的导体带实施例。
图6c示出了电源传输线的另一示例性实施例,其中多对导体613、614布置为堆叠形式。这种结构由于堆叠中相邻导体之间具有更强的负磁耦合,因而提供了较低的等效电感。这减小了传输线的感性阻抗,并允许更快变化的电流流过电源602和放大器615之间的线路。
图7示出了示例性多赫蒂放大器700的主要部件的示例性透视图。多赫蒂放大器700包括实施为LDMOS集成电路的主放大器件管芯701和峰值放大器件管芯702。第一输入703连接到主放大器701,第二输入704连接到峰值放大器702。电源705、电源线706和输出阻抗匹配电路元件707设置在独立的管芯708上。电源线705形成为上述关于图5a和5b所描述的形式。
导线键合连接709将电源线706连接到主放大器701的漏极连接710。另外,导线键合连接712通过管芯708上提供容性接地的键合焊盘711,将主放大器701的漏极连接710连接到峰值放大器702的漏极连接713。另外,多个导线键合连接714a、714b通过提供容性接地的另一键合焊盘715将漏极连接713连接到输出引线连接716。
多赫蒂放大器700的所有部件布置在公用的基板或法兰盘(flange)717上,公用基板或法兰盘717可以提供用以连接到各接地电容以及主放大器和峰值放大器701、702的源极连接的公共地平面。
根据本发明实施例的集成多赫蒂放大器包括图7所示类型的多个多赫蒂放大器级。这种集成多赫蒂放大器的输入连接可以分布在各主放大器和峰值放大器之间,这在下面将更详细的描述。
多赫蒂放大器电路的主器件和峰值器件可以包括FET、BJT、HBT或HEMT器件。
电源优选地通过设置为使得前向和返回供电电流通过磁耦合彼此紧密耦合的传输线连接到例如由公共基板717提供的参考地平面。
图8示出了单个多赫蒂放大器单元的可选实施例,其配置有例如用于宽带视频应用的宽带输入和输出网络。放大器800具有与图7所示的实施例类似的结构,但是具有将电源807连接到峰值器件802的漏极端子713的宽边耦合传输线806,以代替图7所示实施例的导线键合连接。还示出了到主器件和峰值器件的输入偏置电压连接。
在上述类型的多个主器件和峰值器件在单个封装中并行布置的情况下,峰值器件的输出优选地直接连接到或通过具有合适特性阻抗的等效集总元件连接到封装的输出端子,该等效集总元件的串联(series)和分路(shunt)元件可以由导线键合连接构成的电容和电感组成。
在包含多个并联主器件和峰值器件的实施例中,所有的主器件和峰值器件输入优选地通过两个独立的簇组合结构(cluster combinestructure)组合在一起,每对主器件和峰值器件连接在两个独立的输入端子处,从而使得所有器件具有统一的驱动信号。簇功率组合器可以与集成多赫蒂放大器的主器件和峰值器件布置在相同的管芯上,或者可以设置在独立的基板上以允许宽带输入阻抗变换。
电源线优选地包括一个或多个具有实质上相同的特性阻抗Zo的模块,并配置为提供相移,这些模块串联连接以使得在放大器工作频带的中心处总相移等于90度。通过电源线提供的相移可选地可以是90(2n+1)度,其中n是正整数。构成电源线的单个模块的特性阻抗优选地等于主器件的最佳负载阻抗。
集成多赫蒂放大器电源的地端子优选地在与主器件和峰值器件通过他们的公共端子连接到公共地平面的相同位置处,通过电源传输线连接到公共地平面。
图9a和9b示例性示出了FET/LDMOS多赫蒂放大器电路的两个可选输入网络。在每种情况中,输入网络通过连接在主器件和峰值器件之间的低通相移元件,在放大器的主器件和峰值器件的输入之间提供90度相移。可以根据放大器的工作频率所要求的信号幅度和相位,来选择元件Lt、Ct和Rt的值。
图10a和10b中所示是针对图9b的放大器电路,主器件和峰值器件之间的相移仿真曲线(图10a)以及主器件和峰值器件的峰值栅极电压仿真曲线(图10b)。从图10a中可见,低通相移元件对于90度+/-20度的相移允许超过40%的带宽(在1.6和2.4GHz之间)。主器件和峰值器件的峰值栅极RF电压在该频率范围上的变化均小于1V。
图11所示是在主器件和峰值器件之间连接有低通相移元件1101a-1101c的多赫蒂放大器电路链,其中多赫蒂放大器电路的输入通过高通相移元件1102a、1102b彼此串联连接。低通相移元件1101a-1101c提供-90度的相移,而高通相移元件1102a、1102b提供+90度的相移。这种组合允许具有最小输入功率损耗的宽带群时延。
图12示出了集成多赫蒂放大器1200的示例性实施例的示意性电路图,该集成多赫蒂放大器1200包括两个具有公共输入1202的多赫蒂放大器1201a、1201b。公共输入1202通过第一放大器1201a的低通相移元件1203a连接到第一多赫蒂放大器1201a的主器件的输入,以及通过连接第一和第二多赫蒂放大器1201a、1201b的输入的高通相移元件1204连接到第二多赫蒂放大器1201b的主器件的输入。多赫蒂放大器1201a、1201b的输出连接到公共输出1205以及连接到负载阻抗1206。
图13和14示出了针对超过20%带宽范围的示例性集成多赫蒂放大器,作为输出功率的函数的仿真功率增益(图13)和功率增加效率(图14)曲线图。在图示结果中,带宽范围在1.8和2.2GHz之间。在直到40dBm的输出功率范围内功率增益基本保持恒定在大约15dB,而功率增加效率增加到大约60%。
图15是图12中所示集成多赫蒂放大器电路的可选集成多赫蒂放大器电路的示意性电路图,该电路也包括输入通过输入相移元件连接的第一和第二多赫蒂放大器。在该实施例中,电压偏置输入电路被示出为连接到第一和第二多赫蒂放大器的峰值器件输入。附加电容器Ct设置在每个多赫蒂放大器的峰值器件输入处。包括元件Ls、Cs的附加LC电路连接在第一和第二多赫蒂放大器的输出与地之间,每个LC电路的中点节点连接到电源电路。栅极偏置和电源电压分别通过电感Lt和Ls连接到每个多赫蒂放大器的有源器件。
图16是包括第一和第二多赫蒂放大器的另一可选集成多赫蒂放大器电路的示意性电路图,其中第一和第二多赫蒂放大器的输入通过输入相移元件连接,其中,通过用宽带耦合器代替图12和15的电路中的电感,来提供每个多赫蒂放大器的输入处的相移元件。
图17是布置为宽带工作的另一可选示例性多赫蒂放大器的示意性透视图,其中在峰值器件的漏极端子与放大器的输出引线之间设置了另外的后匹配元件。
其他的实施例也落在本发明的范围内,并由所附权利要求限定。
参考文献
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Claims (11)
1.一种具有工作频率的集成射频放大器(1200),所述集成射频放大器包括第一多赫蒂放大器(1201a)和第二多赫蒂放大器(1201b),每个多赫蒂放大器包括主器件和峰值器件,主器件和峰值器件通过相应的相移元件在各自的输入和输出处连接,所述相移元件配置为在工作频率下提供90度的相移,
其中所述集成射频放大器(1200)的输入(1202)连接到所述第一多赫蒂放大器(1201a)的主器件的输入,所述集成射频放大器的输出(1205)连接到所述第一多赫蒂放大器(1201a)和第二多赫蒂放大器(1201b)的峰值器件的输出,以及所述第一多赫蒂放大器(1201a)的峰值器件输入通过相移元件(1204)连接到所述第二多赫蒂放大器(1201b)的主器件输入,该相移元件(1204)配置为在工作频率下提供90度的相移,但与每个多赫蒂放大器中主器件和峰值器件之间的多赫蒂输入处的相移元件所提供的相移符号相反的相移。
2.根据权利要求1所述的具有工作频率的集成射频放大器,包括:一个或多个另外的多赫蒂放大器电路,每个另外的多赫蒂放大器电路具有峰值器件输出和主器件输入,所述峰值器件输出连接到集成射频放大器输出,所述主器件输入通过相移元件连接到在前多赫蒂放大器的峰值器件输入,该相移元件配置为在工作频率下提供90度的相移。
3.根据权利要求2所述的具有工作频率的集成射频放大器,其中多赫蒂放大器的数量是4或者更少。
4.根据前述权利要求任一项所述的具有工作频率的集成射频放大器,其中连接每个多赫蒂放大器的主器件输出与峰值器件输出的相移元件包括一对电感,电感连接在连接该对电感的节点和所述集成射频放大器的地连接之间。
5.根据前述权利要求1至3任一项所述的具有工作频率的集成射频放大器,其中连接每个多赫蒂放大器的主器件输入和峰值器件输入的相移元件包括低通滤波器,该低通滤波器包括电感以及所述主器件和峰值器件的栅电阻和电容。
6.根据前述权利要求1至3任一项所述的具有工作频率的集成射频放大器,其中连接所述第一多赫蒂放大器的峰值器件输入与所述第二多赫蒂放大器的主器件输入的相移元件(1204)包括高通滤波器,该高通滤波器包括一对电感(L),电感分别连接在所述集成射频放大器的地连接和一电容(C)的相对两端之间。
7.一种射频放大器电路,包括电源网络和根据前述权利要求任一项的具有工作频率的集成射频放大器(1200),其中,每个多赫蒂放大器的主器件和峰值器件的输出端子通过电源线电路(306)连接到所述电源网络,该电源线电路(306)包括形成电感的一对相互耦合的导体,以及在连接该对导体的节点和地连接之间连接的电容。
8.根据权利要求7的射频放大器电路,其中,所述电源线电路(306)包括四分之一波长传输线的等效集总元件。
9.根据权利要求8的射频放大器电路,其中,所述电源线电路(306)包括:
第一并行磁耦合导体对;
与所述第一并行磁耦合导体对串联的第二并行磁耦合导体对;和
在每个并行导体对的节点之间的电容。
10.根据权利要求9的射频放大器电路,其中,所述电源线电路包括并行布置并经由键合焊盘(504)串联电连接的磁耦合导体对(501,502),所述键合焊盘提供接地的容性连接(506)。
11.根据权利要求7至10中任一项所述的射频放大器电路,其中所述电源线电路(705)连接到所述主器件(701)或所述峰值器件(702)的漏极连接(710)。
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