CN102480225B - DC voltage supply - Google Patents

Abstract

The invention provides a direct current voltage supply device which comprises a voltage detection unit, an enabling signal processing unit, a latch unit, a control unit and a voltage conversion unit. The voltage detection unit receives and detects the direct current input voltage to generate an input voltage state signal. The enabling signal processing unit receives the input voltage state signal and the enabling signal and determines the state of the enabling signal according to the input voltage state signal. When the enable signal is invalid, the latch unit latches the enable signal to keep an invalid state. The control unit receives the enabling signal to generate a control signal. When the control signal is valid, the voltage conversion unit receives and converts the direct current input voltage into direct current output voltage for output, and when the control signal is invalid, the voltage conversion unit stops receiving the direct current input voltage. Therefore, when the direct current input voltage is unstable, the power supply for the main circuit of the server is stopped, so that the main circuit is prevented from generating misoperation due to the unstable power supply, and the protection effect is effectively achieved.

Description

DC voltage supply

technical field

The invention relates to a voltage protection device, and in particular to a voltage supply device capable of cutting off the DC power supply when the DC voltage is unstable.

Background technique

Generally speaking, a server system provides an operating voltage through a power supply. The current power supply first receives the alternating current (AC) voltage of 100V-230V, and then converts the above alternating current (DC) voltage into a direct current (DC) voltage (such as 12V) through the transformer inside the power supply. As the working voltage of the server system. At this time, all the protection of 12V is done in the power supply.

However, the future trend is that the server system no longer provides the operating voltage via the AC voltage, but directly provides the operating voltage directly from the DC voltage (eg 12V) provided by the end customer. At this point, the server system cannot use a power supply, but is replaced by a DC board. However, the above-mentioned DC board should still have all the protection functions of the power supply, that is, over voltage protection (OVP) and under voltage protection (UVP). Because, how to make the DC board also achieve the over-voltage protection and low-voltage protection of the power supply will be a problem that needs to be solved.

Contents of the invention

The present invention provides a DC voltage supply device, which includes a voltage detection unit, an enable signal processing unit, a latch unit, a control unit and a voltage conversion unit. The voltage detection unit receives and detects the DC input voltage to generate an input voltage state signal, wherein the input voltage state signal is used to indicate a stable state of the DC input voltage. The enable signal processing unit is coupled to the voltage detection unit, receives the input voltage state signal and the enable signal, and determines the state of the enable signal according to the input voltage state signal. When the DC input voltage is stable, the enable signal is valid, and the DC input voltage When unstable, the enable signal is invalid. The latch unit is coupled to the enable signal processing unit, and when the enable signal is invalid, the latch unit latches the enable signal to remain in an invalid state. The control unit is coupled to the enable signal processing unit and the latch unit, and receives the enable signal to generate a control signal. When the enable signal is valid, the control signal is valid, and when the enable signal is invalid, the control signal is invalid. The voltage conversion unit is coupled to the control unit. When the control signal is valid, the voltage conversion unit receives the DC input voltage and converts the DC input voltage into a DC output voltage for output. When the control signal is invalid, the voltage conversion unit stops receiving the DC input voltage.

In an embodiment of the present invention, the voltage detection unit includes a voltage dividing circuit and a comparator. The voltage divider circuit receives the DC input voltage and divides the DC voltage to generate a voltage divider signal. The comparator is coupled to the voltage dividing circuit, receives and compares the divided voltage signal and the first reference voltage signal to generate an input voltage state signal.

In an embodiment of the present invention, the voltage dividing circuit includes a first resistor and a second resistor. The first end of the first resistor receives a DC input voltage, and the second end of the first resistor generates a divided voltage signal. The first terminal of the second resistor is coupled to the second terminal of the first resistor, and the second terminal of the second resistor is coupled to the ground terminal.

In an embodiment of the present invention, the positive input terminal of the comparator receives the divided voltage signal, and the negative input terminal of the comparator receives the first reference voltage signal.

In an embodiment of the present invention, the positive input terminal of the comparator receives the first reference voltage signal, and the negative input terminal of the comparator receives the divided voltage signal.

In an embodiment of the present invention, the enabling signal processing unit includes a first transistor and a voltage pull-up circuit. The gate terminal of the first transistor receives the input voltage state signal, and the source terminal of the first transistor is coupled to the ground terminal. The voltage pull-up circuit is coupled to the drain terminal of the first transistor, wherein when the DC input voltage is stable, the first transistor is not turned on, enabling the enable signal to be valid; when the DC input voltage is unstable, the first transistor is turned on, enabling the Invalid signal.

In an embodiment of the present invention, the voltage pull-up circuit includes a third resistor, a first capacitor and a fourth resistor. The first terminal of the third resistor is coupled to the DC input voltage, and the second terminal of the third resistor is coupled to the drain terminal of the first transistor and receives the enable signal. The first terminal of the first capacitor is coupled to the second terminal of the third resistor, and the second terminal of the first capacitor is coupled to the ground terminal. The first terminal of the fourth resistor is coupled to the second terminal of the third resistor, and the second terminal of the fourth resistor is coupled to the ground terminal.

In an embodiment of the present invention, the above-mentioned latch unit includes a delay unit and a first switch unit. The input end of the delay unit receives the second reference voltage signal for delaying the second reference voltage signal to generate a delayed voltage signal. The first switch unit is coupled to the delay unit, and receives and determines whether to latch the enable signal according to the delayed voltage signal and the enable signal, wherein when the enable signal is invalid, the first switch unit is activated to latch the enable signal to remain inactive state, when the enable signal is invalid, the first switch is not activated, and the latch unit does not act.

In an embodiment of the present invention, the delay unit includes a fifth resistor and a second capacitor. The first terminal of the fifth resistor receives the second reference voltage signal, and the second terminal of the fifth resistor generates a delayed voltage signal. The first terminal of the second capacitor is coupled to the second terminal of the fifth resistor, and the second terminal of the second capacitor is coupled to the ground terminal.

In an embodiment of the present invention, the above-mentioned first switch unit includes a second transistor and a third transistor. The drain terminal of the second transistor receives the delayed voltage signal, the source terminal of the second transistor is coupled to the ground terminal, and the gate terminal of the second transistor receives the enabling signal. The gate terminal of the third transistor is coupled to the drain terminal of the second transistor, the drain terminal of the third transistor is coupled to the gate terminal of the second transistor, and the source terminal of the third transistor is coupled to the ground terminal.

In an embodiment of the present invention, the voltage conversion unit includes a second switch unit and a voltage conversion circuit. The second switch unit is coupled to the control unit. When the control signal is valid, the second switch unit is turned on, and the DC input voltage is transmitted through the second switch unit. When the control signal is invalid, the second switch unit is not turned on, so that the voltage conversion unit Cutoff accepts DC input voltage. The voltage conversion circuit is coupled to the second switch unit, and when the second switch unit is turned on, it receives the DC input voltage and converts the DC input voltage into a DC output voltage for output.

In an embodiment of the present invention, the above-mentioned second switch unit includes a fourth transistor. The gate terminal of the fourth transistor receives the control signal, the drain terminal of the fourth transistor receives the DC input voltage, and the source terminal of the fourth transistor determines whether to transmit the DC input voltage through the source terminal of the fourth transistor according to the state of the control signal.

In an embodiment of the present invention, the above-mentioned DC voltage supply device further includes an enabling signal generating unit. The enabling signal generating unit is coupled to the enabling signal processing unit for generating the enabling signal.

In the present invention, the voltage detection unit detects the DC input voltage to generate an input voltage state signal to indicate the stable state of the DC input voltage. Next, the enabling signal processing unit determines the state of the enabling signal according to the input voltage state signal. Afterwards, when the enable signal is invalid, the latch unit is used to latch the enable signal to maintain an invalid state, so that the enable signal will not be changed. Next, the control unit generates a control signal to control the voltage conversion unit according to the enable signal, so as to determine whether to receive and convert the DC input voltage into a DC output voltage for the main circuit of the server. In this way, when the DC input voltage is unstable, the power supply to the main circuit of the server is stopped, so as to avoid the malfunction of the main circuit caused by the unstable power supply, and effectively achieve the protection function.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a block diagram of a voltage supply device for a DC board according to an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of the voltage supply device of the DC board shown in FIG. 1 .

FIG. 3 is another detailed circuit diagram of another DC board voltage supply device in FIG. 1 .

Description of main component symbols

100: DC voltage supply device

110: Voltage detection unit

120: enable signal processing unit

130: Latch unit

140: Control unit

150: Voltage conversion unit

160: enable signal generator

210, 310: voltage divider circuit

220, 320: Comparator

230, 330: voltage pull-up circuit

240, 340: delay unit

250, 260, 350, 360: switch unit

270, 370: Voltage conversion circuit

R1-R6: Resistors

C1-C3: capacitance

M1-M4: Transistors

VDD: DC input voltage

VD1: divided voltage signal

VS1: input voltage status signal

VS2: delayed voltage signal

Vref1, Vref2: reference voltage signal

GND: ground terminal

VE: enable signal

CS: control signal

V0: DC output voltage

Detailed ways

FIG. 1 is a DC voltage supply device according to an embodiment of the present invention. The DC voltage supply device of this embodiment is suitable for a server. Referring to FIG. 1 , the DC voltage supply device 100 includes a voltage detection unit 110 , an enable signal processing unit 120 , a latch unit 130 , a control unit 140 and a voltage conversion unit 150 .

The voltage detection unit 110 receives and detects the DC input voltage VDD to generate an input voltage state signal VS1 , wherein the input voltage state signal VS1 is used to indicate a stable state of the DC input voltage VDD. The enable signal processing unit 120 is coupled to the voltage detection unit 110 , receives the input voltage state signal VS1 and the enable signal VE, and determines the state of the enable signal VE according to the input voltage state signal VS1 . For example, when the input voltage state signal VS1 is at a low logic level “0”, it means that the DC input voltage VDD is in a stable state, and the enable signal processing unit 120 adjusts the enable signal VE to a high logic level “1”. , to make the enable signal VE effective; when the input voltage state signal VS1 is at a high logic level "1", it indicates that the DC input voltage VDD is in an unstable state, and the enable signal processing unit 120 will adjust the enable signal VE to a low logic level Bit "0" makes the enable signal VE invalid.

The latch unit 130 is coupled to the enable signal processing unit 120 , and when the enable signal VE is invalid, the latch unit 130 latches the enable signal VE to keep the enable signal VE in an invalid state. The control unit 140 is coupled to the enable signal processing unit 120 and the latch unit 130 , receives the enable signal VE and generates the control signal CS accordingly. For example, when the enable signal VE is valid, that is, the enable signal VE is at a high logic level "1", the control unit 140 will adjust the control signal CS to a high logic level "1", so that the control signal CS is valid. And output, when the enable signal VE is invalid, that is, the enable signal VE is at a low logic level "0", the control unit 140 will adjust the control signal CS to a low logic level "0", making the control signal CS invalid and output. In this embodiment, the control unit 140 is, for example, an ISL6115 chip.

The voltage conversion unit 150 is coupled to the control unit 140 for determining whether to provide the DC input voltage VDD as the DC output voltage V0 according to the control signal CS. For example, when the control signal CS is at a high logic level "1", that is, the control signal is valid, the voltage conversion unit 150 receives the DC input voltage VDD, and converts the DC input voltage VDD into a DC output voltage V0 for output. When the signal CS is at the low logic level “0”, that is, the control signal CS is invalid, and the voltage conversion unit 150 is turned off to receive the DC input voltage VDD.

In this way, the DC voltage supply device 100 of this embodiment can stop supplying power to the main circuits of the server when the DC input voltage VDD is in an unstable state, so as to avoid malfunctions of the main circuits caused by unstable power, and Effectively achieve the role of protection.

In addition, the DC voltage supply device 100 of this embodiment further includes an enabling signal generator 160 . The enable signal generator 160 is coupled to the enable signal processing unit 120 for generating the enable signal VE to the enable signal processing unit 120 . Wherein, the enable signal VE is generated by the enable signal generator 160 when the motherboard (not shown) is connected to the DC voltage supply device 100, or is generated by the enable signal generator 160 according to the power-on signal when the motherboard is turned on. and convert it to generate.

Hereinafter, a more detailed circuit will be used to illustrate the DC voltage supply device 100 .

FIG. 2 is a detailed circuit diagram of the DC voltage supply device 100 in FIG. 1 . Please refer to FIG. 2 , the voltage detection unit 110 includes a voltage dividing circuit 210 and a comparator 220 . The voltage divider circuit 210 receives the DC input voltage VDD, and divides the DC input voltage VDD to generate a voltage divider signal VD1. Wherein, the voltage dividing circuit 210 includes resistors R1 and R2. A first end of the resistor R1 receives a DC input voltage VDD, and a second end of the resistor R1 generates a divided voltage signal VD1. The first terminal of the resistor R2 is coupled to the second terminal of the resistor R1, and the second terminal of the resistor R2 is coupled to the ground terminal GND. That is, the voltage divider circuit 210 divides the DC input voltage VDD through the resistors R1 and R2 to generate the divided voltage signal VD1 .

The comparator 220 is coupled to the voltage dividing circuit 210 , receives and compares the voltage dividing signal VD1 and the reference voltage signal Vref1 to generate the input voltage state signal VS1 . In this embodiment, the first input terminal (for example, a positive input terminal) of the comparator 220 receives the divided voltage signal VD1, the second input terminal (for example, a negative input terminal) of the comparator 220 receives the reference voltage signal Vref1, and the comparator The output terminal of 220 generates the input voltage status signal VS1.

The enabling signal processing unit 120 includes a transistor M1 and a voltage pull-up circuit 230 . The gate terminal of the transistor M1 receives the input voltage state signal VS1 , and the source terminal of the transistor M1 is coupled to the ground terminal GND. Wherein, the transistor M1 may be an NMOS transistor.

The voltage pull-up circuit 230 is coupled to the drain terminal of the transistor M1, receives the enable signal VE, and determines the state of the enable signal VE according to whether the transistor M1 is turned on or not. For example, when the DC input voltage VDD is in a stable state, that is, the input voltage state signal VS1 is a low logic level “0” and is transmitted to the gate terminal of the transistor M1, so that the transistor M1 is not turned on, and the voltage pull-up circuit 230 The enable signal VE will be kept at a high logic level "1", and the enable signal VE is valid. When the DC input voltage VDD is in an unstable state, that is, the input voltage state signal VS1 is at a high logic level "1" and Transfer to transistor M1, so that transistor M1 is turned on. At this moment, since the transistor M1 is turned on, the enable signal VE is pulled down to a low logic level “0”, and the enable signal VE is invalid.

In addition, the voltage pull-up circuit 230 includes resistors R3 and R4 and a capacitor C1. A first terminal of the resistor R3 is coupled to the DC input voltage VDD, and a second terminal of the resistor R3 is coupled to the drain terminal of the transistor M1, and receives the enable signal VE. A first end of the capacitor C1 is coupled to a second end of the resistor R3, and a second end of the capacitor C1 is coupled to the ground terminal GND. The first terminal of the resistor R4 is coupled to the second terminal of the resistor R3, and the second terminal of the resistor R4 is coupled to the ground terminal GND.

The latch unit 130 includes a delay unit 240 and a switch unit 250 . The input end of the delay unit 240 receives the reference voltage signal Vref2 for delaying the reference voltage signal Vref2 to generate a delayed voltage signal VS2. In addition, the delay unit 240 includes a resistor R5 and a capacitor C2. A first end of the resistor R5 receives the reference voltage signal Vref2, and a second end of the resistor R5 generates a delayed voltage signal VS2. The first terminal of the capacitor C2 is coupled to the second terminal of the resistor R5, and the second terminal of the capacitor C2 is coupled to the ground terminal GND.

The switch unit 250 is coupled to the delay unit 240, receives and determines whether to latch the enable signal VE according to the delay voltage signal VS2 and the enable signal VE, wherein when the enable signal VE is invalid, the switch unit 250 is activated to latch enable Signal VE remains inactive. In addition, the switch unit 250 includes transistors M2 and M3. The drain terminal of the transistor M2 receives the delayed voltage signal VS2 , the source terminal of the transistor M2 is coupled to the ground terminal GND, and the gate terminal of the transistor M2 receives the enable signal VE. The gate terminal of the transistor M3 is coupled to the drain terminal of the transistor M2, the drain terminal of the transistor M3 is coupled to the gate terminal of the transistor M2, and the source terminal of the transistor M3 is coupled to the ground terminal GND.

The voltage conversion unit 150 includes a switch unit 260 and a voltage conversion circuit 270 . The switch unit 260 is coupled to the control unit 140. When the control signal CS is valid, the switch unit 260 is turned on, and the DC input voltage VDD is transmitted through the switch unit 260. When the control signal CS is invalid, the switch unit 260 is not turned on, so that the voltage conversion unit 150 is cut off to receive the DC input voltage VDD. The voltage conversion circuit 270 is coupled to the switch unit 260 , and when the switch unit 260 is turned on, it receives the DC input voltage VDD and converts the DC input voltage VDD into a DC output voltage V0 for output.

In addition, the switch unit 260 includes a transistor M4. The gate terminal of the transistor M4 receives the control signal CS, the drain terminal of the transistor M4 receives the DC input voltage VDD, and the transistor M4 determines whether the source terminal of the transistor M4 transmits the DC input voltage VDD according to the state of the control signal CS.

In terms of overall circuit operation, firstly, the DC input voltage VDD is divided by the resistors R1 and R2 of the voltage divider circuit 210 to generate a divided voltage signal VD1, which is input to the first input terminal (positive input terminal) of the comparator 220 . Next, when the first input terminal (positive input terminal) of the comparator 220 receives the divided voltage signal VD1 , it will be compared with the reference voltage signal Vref1 received by the second input terminal (negative input terminal) of the comparator 220 .

Generally speaking, when the DC input voltage VDD is working normally and stably (that is, no over voltage state occurs), the divided voltage signal VD1 generated by the voltage dividing circuit 210 will be smaller than the reference voltage signal Vref1. Therefore, when the voltage of the divided voltage signal VD1 is lower than the reference voltage signal Vref1 , the output terminal of the comparator 220 will generate the input voltage state signal VS1 with a low logic level “0”. Next, the input voltage state signal VS1 of the low logic level “0” is transmitted to the gate terminal of the transistor M1 of the enabling signal processing unit 120, so that the transistor M1 is not turned on. Since the transistor M1 is not turned on, the voltage pull-up circuit 230 adjusts the enable signal VE it receives to a high logic level “1”, and transmits it to the gate terminal of the transistor M2 of the latch unit 130 and the control unit 140 respectively. .

Since the reference voltage signal Vref 2 is delayed by the delay unit 240, the enable signal VE with a high logic level “1” is transmitted to the gate terminal of the transistor M2 one step earlier than the delayed voltage signal VS 2 generated by the delay unit 240, so that Transistor M2 is turned on. Since the transistor M2 is turned on, the gate terminal of the transistor M3 is coupled to the ground terminal GND, so that the transistor M3 is not turned on, and the latch unit 130 does not function (that is, the latch unit 130 does not operate), so that The enable signal VE is still at the high logic level “1”, which indicates that the enable signal VE is valid.

Next, when the control unit 140 receives the enable signal VE with a high logic level “1”, it generates a control signal CS with a high logic level “1” to the gate terminal of the transistor M4 to turn on the transistor M4 . Since the transistor M4 is turned on, the voltage conversion circuit 270 receives the DC input voltage VDD through the source terminal of the transistor M4 and converts the DC input voltage VDD into a DC output voltage V0 to provide the main circuit of the server for operation.

In addition, once the DC input voltage VDD jitters, the divided voltage signal VD1 also jitters accordingly, resulting in an overvoltage state. Therefore, when the voltage of the divided voltage signal VD1 is greater than the reference voltage signal Vref1 , the output terminal of the comparator 220 will generate the input voltage state signal VS1 with a high logic level “1”. Next, the input voltage state signal VS1 of the high logic level “1” is transmitted to the gate terminal of the transistor M1 of the enabling signal processing unit 120 , so that the transistor M1 is turned on. Since the transistor M1 is turned on, the ground terminal GND will be output through the transistor M1, so that the voltage pull-up circuit 230 adjusts the received enable signal VE to a low logic level “0”, and transmits them to the transistors of the latch unit 130 respectively. The gate terminal of M2 is connected with the control unit 140 .

At this time, the gate terminal of the transistor M2 receives the enable signal VE of the low logic level “0”, so that the transistor M2 is not turned on. Since the transistor M2 is not turned on, the delay voltage signal VS2 generated by the delay unit 240 is transmitted to the gate terminal of the transistor M3, and the transistor M3 is turned on, so that the latch unit 130 latches the enable signal VE to a low logic level. Bit "0" to keep inactive. Afterwards, the control unit 140 receives the enable signal VE of the low logic level “0”, generates the control signal CS of the low logic level “0” accordingly, and transmits the control signal CS to the gate terminal of the transistor M4, so that Transistor M4 is non-conductive. Since the transistor M4 is not turned on, the voltage conversion circuit 270 cannot receive the DC input voltage VDD through the transistor M4, so that the voltage conversion unit 150 is cut off from receiving the DC input voltage VDD, so as to cut off the power supply to the main circuit of the server. In this way, the DC voltage supply device 100 of this embodiment can effectively latch the overvoltage state and cut off the power supplied to the main circuit when the DC input voltage VDD is in an overvoltage state, thereby protecting the main circuit.

In addition, in this embodiment, the enable signal processing unit 120 further includes a filter circuit 280 for receiving the input voltage state signal VS1 to filter noise in the input voltage state signal VS1 . The filter circuit 280 includes a resistor R6 and a capacitor C3 , the coupling relationship of which is shown in FIG. 2 , so it will not be repeated here.

In addition, FIG. 3 is a detailed circuit diagram of another DC voltage supply device in FIG. 1 . The implementation of voltage detection unit 110, enable signal processing unit 120, latch unit 130, control unit 140, voltage conversion unit 150, and enable signal generator 160 in FIG. The implementation manners of the signal processing unit 120 , the latch unit 130 , the control unit 140 , the voltage conversion unit 150 and the enable signal generator 160 will not be repeated here. The difference between Fig. 3 and Fig. 2 is: the first input end of the comparator 220 in Fig. 2 is a positive input end, the second input end of the comparator 220 is a negative input end, and the first input end of the comparator 320 in Fig. 3 The input terminal is a negative input terminal, and the second input terminal of the comparator 320 is a positive input terminal.

In terms of overall circuit operation, first, the DC input voltage VDD is divided by the resistors R1 and R2 of the voltage divider circuit 310 to generate a divided voltage signal VD1, which is input to the first input terminal (negative input terminal) of the comparator 320 . Next, when the first input terminal (negative input terminal) of the comparator 320 receives the divided voltage signal VD1 , it will be compared with the reference voltage signal Vref1 received by the second input terminal (positive input terminal) of the comparator 320 .

Generally speaking, when the DC input voltage VDD works normally and stably (that is, no under voltage state occurs), the divided voltage signal VD1 generated by the voltage dividing circuit 310 will be greater than the reference voltage signal Vref1. Therefore, when the voltage of the divided voltage signal VD1 is lower than the reference voltage signal Vref1 , the output terminal of the comparator 320 will generate the input voltage state signal VS1 with a low logic level “0”. Next, the input voltage state signal VS1 of the low logic level “0” is transmitted to the gate terminal of the transistor M1 of the enable signal processing unit 120 , so that the transistor M1 is not turned on. Since the transistor M1 is not turned on, the voltage pull-up circuit 230 adjusts the received enabling signal VE to a high logic level “1”, and transmits it to the gate terminal of the transistor M2 of the latch unit 130 and the control unit respectively. 140.

Since the reference voltage signal Vref2 is delayed by the delay unit 340, the smart signal VE with a high logic level “1” is transmitted to the gate terminal of the transistor M2 one step earlier than the delayed voltage signal VS2 generated by the delay unit 340, so that the transistor M2 conducts Pass. Since the transistor M2 is turned on, the gate terminal of the transistor M3 is coupled to the ground terminal GND, so that the transistor M3 is not turned on, and the latch unit 130 does not function, so that the enabling signal VE is still at a high logic level “1” ”, indicating that the enable signal VE is valid.

Next, when the control unit 140 receives the enable signal VE with a high logic level “1”, it generates a control signal CS with a high logic level “1” to the gate terminal of the transistor M4 to turn on the transistor M4 . Since the transistor M4 is turned on, the voltage conversion circuit 370 receives the DC input voltage VDD through the source terminal of the transistor M4 and converts the DC input voltage VDD into a DC output voltage V0 to provide the main circuit of the server for operation.

In addition, once the DC input voltage VDD jitters, the divided voltage signal VD1 also jitters accordingly, resulting in a low voltage state. Therefore, when the voltage of the divided voltage signal VD1 is greater than the reference voltage signal Vref1 , the output terminal of the comparator 320 will generate the input voltage state signal VS1 with a high logic level “1”. Next, the input voltage state signal VS1 of the high logic level “1” is transmitted to the gate terminal of the transistor M1 of the enabling signal processing unit 120 , so that the transistor M1 is turned on. Since the transistor M1 is turned on, the ground terminal GND will be output through the transistor M1, so that the voltage pull-up circuit 330 adjusts the received enabling signal VE to a low logic level “0”, and transmits them to the transistors of the latch unit 130 respectively. The gate terminal of M2 is connected with the control unit 140 .

At this time, the gate terminal of the transistor M2 receives the enable signal VE of the low logic level “0”, so that the transistor M2 is not turned on. Since the transistor M2 is not turned on, the delay voltage signal VS2 generated by the delay unit 340 will be transmitted to the gate terminal of the transistor M3, and the transistor M3 will be turned on, so that the latch unit 130 will latch the enable signal VE to low logic level "0" to maintain an inactive state. Afterwards, the control unit 140 receives the enable signal VE of the low logic level “0”, generates the control signal CS of the low logic level “0” accordingly, and transmits the control signal CS to the gate terminal of the transistor M4, so that Transistor M4 is non-conductive. Since the transistor M4 is not turned on, the voltage conversion circuit 370 cannot receive the DC input voltage VDD through the transistor M4, so that the voltage conversion unit 150 is cut off from receiving the DC input voltage VDD, so as to cut off the power supply to the main circuit of the server. In this way, the DC voltage supply device 100 of this embodiment can effectively latch the low-voltage state and cut off the power supplied to the main circuit when the DC input voltage VDD is in a low-voltage state, thereby protecting the main circuit.

To sum up, in this embodiment, the voltage detection unit detects the DC input voltage to generate an input voltage state signal to indicate the stable state of the DC input voltage. Next, the enabling signal processing unit determines the state of the enabling signal according to the input voltage state signal. Afterwards, when the enable signal is invalid, the latch unit is used to latch the enable signal to maintain an invalid state, so that the logic level of the enable signal will not be changed. Next, the control unit generates a control signal to control the voltage conversion unit according to the enable signal, so as to determine whether to receive and convert the DC input voltage into a DC output voltage for the main circuit of the server. In this way, in this embodiment, when the DC input voltage is unstable (such as an overvoltage state or a low voltage state), the power supply to the main circuit of the server is stopped, so as to avoid malfunction of the main circuit caused by an unstable power supply, and Effectively achieve the role of protection.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention, and any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention.

Claims (13)

1. a direct voltage feeding mechanism, comprising:

One voltage detection unit, receives and detects a DC input voitage, and to produce an input voltage status signal, wherein this input voltage status signal is in order to indicate the stable state of this DC input voitage;

One activation signal processing unit, couple this voltage detection unit, receive this input voltage status signal and an enable signal, and according to this input voltage status signal, determine the state of this enable signal, when wherein this DC input voitage is stablized, this enable signal is effective, and when this DC input voitage is unstable, this enable signal is invalid;

One latch lock unit, couples this enable signal processing unit, and when this enable signal is invalid, this enable signal of this latch lock unit breech lock keeps disarmed state;

One control unit, couples this enable signal processing unit and this latch lock unit, receives this enable signal and produces according to this control signal, and when this enable signal is effective, this control signal is effective, and when this enable signal is invalid, this control signal is invalid; And

One voltage conversion unit, couple this control unit, when this control signal is effective, this voltage conversion unit receives this DC input voitage and this DC input voitage is converted to a VD output, when this control signal is invalid, this voltage conversion unit cut-off receives this DC input voitage.

2. direct voltage feeding mechanism according to claim 1, wherein this voltage detection unit comprises:

One bleeder circuit, receives this DC input voitage, and this direct voltage is carried out to dividing potential drop, to produce a voltage division signal;

One comparator, couples this bleeder circuit, and reception relatively this voltage division signal and one first reference voltage signal, to produce this input voltage status signal.

3. direct voltage feeding mechanism according to claim 2, wherein this bleeder circuit comprises:

One first resistance, its first end receives this DC input voitage, and its second end produces this voltage division signal; And

One second resistance, its first end couples the second end of this first resistance, and its second end couples earth terminal.

4. direct voltage feeding mechanism according to claim 2, wherein the positive input terminal of this comparator receives this voltage division signal, and the negative input end of this comparator receives this first reference voltage signal.

5. direct voltage feeding mechanism according to claim 2, wherein the positive input terminal of this comparator receives this first reference voltage signal, and the negative input end of this comparator receives this voltage division signal.

6. direct voltage feeding mechanism according to claim 1, wherein this enable signal processing unit comprises:

One the first transistor, its gate terminal receives this input voltage status signal, and its source terminal couples earth terminal; And

One voltage pull-up circuit, couple the drain electrode end of this first transistor, receive this enable signal, and according to this first transistor whether conducting determine the state of this enable signal, when wherein this DC input voitage is stablized, this not conducting of the first transistor, make this enable signal effective, when this DC input voitage is unstable, this first transistor conducting, makes this enable signal invalid.

7. direct voltage feeding mechanism according to claim 6, wherein this voltage pull-up circuit comprises:

One the 3rd resistance, its first end couples this DC input voitage, and its second end couples the drain electrode end of this first transistor, and receives this enable signal;

One first electric capacity, its first end couples the second end of the 3rd resistance, and its second end couples earth terminal; And

One the 4th resistance, its first end couples the second end of the 3rd resistance, and its second end couples earth terminal.

8. direct voltage feeding mechanism according to claim 1, wherein this latch lock unit comprises:

One delay cell, its input receives one second reference voltage signal, and postpones this second reference voltage signal, to produce delay voltage signal;

One first switch element, couple this delay cell, receive and according to this delay voltage signal and this enable signal, and whether determine this enable signal of breech lock, wherein, when this enable signal is invalid, this first switch element starts with this enable signal maintenance disarmed state of breech lock, when this enable signal is effective, this first switch element does not start, and this latch lock unit is failure to actuate.

9. direct voltage feeding mechanism according to claim 8, wherein this delay cell comprises:

One the 5th resistance, its first end receives this second reference voltage signal, and its second end produces this delay voltage signal; And

One second electric capacity, its first end couples the second end of the 5th resistance, and its second end couples earth terminal.

10. direct voltage feeding mechanism according to claim 8, wherein this first switch element comprises:

One transistor seconds, its drain electrode end receives this delay voltage signal, and its source terminal couples earth terminal, and its gate terminal receives this enable signal; And

One the 3rd transistor, its gate terminal couples the drain electrode end of this transistor seconds, and its drain electrode end couples the gate terminal of this transistor seconds, and its source terminal couples earth terminal.

11. direct voltage feeding mechanisms according to claim 1, wherein this voltage conversion unit comprises:

One second switch unit, couple this control unit, when this control signal is effective, this second switch cell conduction, this DC input voitage is transmitted via this second switch unit, when this control signal is invalid, this second switch not conducting of unit, makes this voltage conversion unit cut-off receive this DC input voitage; And

One voltage conversion circuit, couples this second switch unit, when this second switch cell conduction, receives this DC input voitage, and this DC input voitage is converted to this VD output.

12. direct voltage feeding mechanisms according to claim 11, wherein this second switch unit comprises:

One the 4th transistor, its gate terminal receives this control signal, and its drain electrode end receives this DC input voitage, and the 4th transistor determines whether by its source terminal, transmit this DC input voitage according to the state of this control signal.

13. direct voltage feeding mechanisms according to claim 1, also comprise:

One enable signal generation unit, couples this enable signal processing unit, in order to produce this enable signal.

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