CN102479707A - Transistor and manufacturing method thereof - Google Patents
Transistor and manufacturing method thereof Download PDFInfo
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- CN102479707A CN102479707A CN201010559189XA CN201010559189A CN102479707A CN 102479707 A CN102479707 A CN 102479707A CN 201010559189X A CN201010559189X A CN 201010559189XA CN 201010559189 A CN201010559189 A CN 201010559189A CN 102479707 A CN102479707 A CN 102479707A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000012774 insulation material Substances 0.000 claims description 19
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 10
- 238000005530 etching Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 230000035755 proliferation Effects 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a transistor and a manufacturing method thereof, wherein the method comprises the following steps: providing a semiconductor substrate on which an active layer is formed; forming buried layers with gaps between the active layers on the surfaces of the semiconductor substrates on two sides of the active layers; forming a first epitaxial layer with a level active layer on the surface of the buried layer and in the gap; forming a groove exposing the semiconductor substrate in the first epitaxial layer, wherein the groove is positioned between the buried layer and the active layer; forming a buried side wall with the thickness smaller than the depth of the groove in the groove; forming a second epitaxial layer on the surfaces of the buried side wall, the active layer and the first epitaxial layer; forming a gate structure on the surface of the second epitaxial layer above the active layer; and forming a source region and a drain region in the second epitaxial layer and the first epitaxial layer at two sides of the gate structure, wherein the source region and the drain region are positioned at two sides of the isolation side wall. The invention improves the short channel effect of the transistor and the performance of the device.
Description
Technical field
The present invention relates to semiconductor applications, particularly transistor and preparation method thereof.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device during semiconductor is made, and they are in various integrated circuits, and the doping type during according to main charge carrier and manufacturing is different, is divided into NMOS and PMOS transistor.
Prior art provides a kind of transistorized manufacture method.Please refer to Fig. 1 to Fig. 3, be the transistorized manufacture method cross-sectional view of prior art.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, form gate dielectric layer 101 and grid 102 on the said Semiconductor substrate 100, said gate dielectric layer 101 constitutes grid structure with grid 102.
Continuation is carried out oxidation technology with reference to figure 1, forms the oxide layer 103 that covers said grid structure.
Then, please refer to Fig. 2, in the Semiconductor substrate of grid structure both sides, form light doping section 104, said light doping section 104 injects through ion and forms.
Then, please refer to Fig. 3, on the Semiconductor substrate of grid structure both sides, form the side wall 105 of grid structure.Carry out source/drain region heavy doping and inject (S/D), in the Semiconductor substrate 100 of grid structure both sides, form source region 106 and drain region 107.
, publication number can find more information in being the one Chinese patent application of CN101789447A about prior art.
Find that in reality the transistor short-channel effect that existing method is made is obvious, the performance of device is undesirable.
Summary of the invention
The problem that the present invention solves has provided a kind of transistor and preparation method thereof, and said method has been improved transistorized short-channel effect, has improved the performance of device.
For addressing the above problem, the invention provides a kind of transistorized manufacture method, comprising:
Semiconductor substrate is provided, and said semiconductor substrate surface is formed with active layer, and the material of said active layer is identical with the material of said Semiconductor substrate;
Semiconductor substrate surface in said active layer both sides forms buried layer, has the gap between said buried layer and the said active layer;
In said buried layer surface and gap, form first epitaxial loayer, said first epitaxial loayer flushes with said active layer;
In said first epitaxial loayer, form the groove that exposes said Semiconductor substrate, said groove is between said buried layer and said active layer;
In said groove, form and bury side wall, the said degree of depth of burying the thickness of side wall less than said groove;
Form second epitaxial loayer on said surface of burying side wall, active layer and first epitaxial loayer;
Second epi-layer surface above said active layer forms grid structure;
In second epitaxial loayer of said grid structure both sides with in first epitaxial loayer, form source region and drain region, said source region and drain region are positioned at said isolation side walls both sides.
Alternatively, being positioned at said thickness range of burying second epitaxial loayer of side wall top is 10～300 nanometers.
Alternatively, the material of said buried layer is the insulation material.
Alternatively, the thickness range of said buried layer is 5～100 dusts.
Alternatively, said material of burying side wall is the insulation material.
Alternatively, said thickness range of burying side wall is 3～30 nanometers.
Alternatively, the width range of said groove is 3～30 nanometers.
Alternatively, said insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
Alternatively, the thickness range that is positioned at second epitaxial loayer on said active layer surface is 20～100 nanometers.
Alternatively, the thickness range of said active layer is 0.05～0.2 micron.
Correspondingly, the present invention also provides a kind of transistor, comprising:
Semiconductor substrate, said semiconductor substrate surface is formed with active layer, and the material of said active layer is identical with the material of said Semiconductor substrate;
Buried layer is positioned at the semiconductor substrate surface of said active layer both sides, has the gap between said buried layer and the said active layer;
First epitaxial loayer is positioned at said buried layer surface and gap, and said first epitaxial loayer flushes with said active layer;
Groove is positioned at said first epitaxial loayer, and said groove and exposes said Semiconductor substrate between said buried layer and said active layer;
Bury side wall, be positioned at said groove, the said degree of depth of burying the thickness of side wall less than said groove;
Second epitaxial loayer is positioned at said surface of burying side wall, active layer and first epitaxial loayer;
Grid structure is positioned at second epi-layer surface of said active layer top;
The source region is positioned at said second epitaxial loayer and first epitaxial loayer of burying side wall one side.
The drain region is positioned at said second epitaxial loayer and first epitaxial loayer of burying the side wall opposite side.
Alternatively, being positioned at said thickness range of burying second epitaxial loayer of side wall top is 10～300 nanometers.
Alternatively, the material of said buried layer is the insulation material.
Alternatively, the thickness range of said buried layer is 5～100 dusts.
Alternatively, said material of burying side wall is the insulation material.
Alternatively, said thickness range of burying side wall is 3～30 nanometers.
Alternatively, the width range of said groove is 3～30 nanometers.
Alternatively, said insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
Alternatively, the thickness range that is positioned at second epitaxial loayer on said active layer surface is 20～100 nanometers.
Alternatively, the thickness range of said active layer is 0.05～0.2 micron.
Compared with prior art, the present invention has the following advantages:
The Semiconductor substrate that is formed with active layer at first is provided; The semiconductor substrate surface of said active layer both sides form with said active layer between have the buried layer in gap, first epitaxial loayer that formation flushes with said active layer in said buried layer surface and gap then; Then in said first epitaxial loayer, form the groove that exposes said Semiconductor substrate, said groove is between said buried layer and said active layer; In said groove, form the bury side wall of thickness then less than the degree of depth of said groove; Form second epitaxial loayer on said surface of burying side wall, active layer and first epitaxial loayer; The said side wall of burying is isolated follow-up source region that in second epitaxial loayer of grid structure both sides and in first epitaxial loayer, forms and drain region; Thereby saidly bury the dopant ion horizontal proliferation that side wall can prevent source region and drain region; Thereby improve transistorized short-channel effect, and because said source region and drain region are positioned at first epitaxial loayer and second epitaxial loayer of buried layer top, thereby the junction capacitance between said source region and drain region and the Semiconductor substrate reduced; Reduce junction leakage, improved the performance of device.
Description of drawings
Fig. 1～Fig. 3 is the transistor fabrication method cross-sectional view of prior art;
Fig. 4 is a transistor fabrication method flow sketch map of the present invention;
Fig. 5～Figure 15 is the transistor fabrication method cross-sectional view of one embodiment of the invention.
Embodiment
The transistorized short-channel effect that existing method is made is obvious, and the performance of device is undesirable.Development along with semiconductor technology; Ultra shallow junction technology is applied to make source region and drain region; Ion horizontal proliferation between source region and the drain region is more serious, thereby makes that described short-channel effect is more obvious, and source region and drain region and bigger junction capacitance and the junction leakage of Semiconductor substrate existence; Thereby reduced the response speed of device, influenced the performance of device.
In order to address the above problem, the inventor proposes a kind of transistorized manufacture method, please refer to transistor fabrication method flow sketch map of the present invention shown in Figure 4, and said method comprises:
Step S1 provides Semiconductor substrate, and said semiconductor substrate surface is formed with active layer, and the material of said active layer is identical with the material of said Semiconductor substrate;
Step S2, the semiconductor substrate surface in said active layer both sides forms buried layer, has the gap between said buried layer and the said active layer;
Step S3 forms first epitaxial loayer in said buried layer surface and gap, said first epitaxial loayer flushes with said active layer;
Step S4 forms the groove that exposes said Semiconductor substrate in said first epitaxial loayer, said groove is between said buried layer and said active layer;
Step S5 forms in said groove and buries side wall, the said degree of depth of burying the thickness of side wall less than said groove;
Step S6 forms second epitaxial loayer on said surface of burying side wall, active layer and first epitaxial loayer;
Step S7, second epi-layer surface above said active layer forms grid structure;
Step S8 forms source region and drain region in second epitaxial loayer of said grid structure both sides with in first epitaxial loayer, said source region and drain region are positioned at said isolation side walls both sides.
To combine concrete embodiment that technical scheme of the present invention is carried out detailed explanation below.
For explanation better, technical scheme of the present invention please refer to the transistor fabrication method cross-sectional view of the one embodiment of the invention of Fig. 5～shown in Figure 15.
At first, please refer to Fig. 5, Semiconductor substrate 200 is provided, said semiconductor substrate surface 200 is formed with active layer 201, and the material of said active layer 201 is identical with the material of said Semiconductor substrate 200.
As an embodiment, the material of said Semiconductor substrate 200 is a silicon.In other embodiment, the material of said Semiconductor substrate 200 can also be other semiconductor material such as germanium, germanium silicon.
In the present embodiment, the thickness range of said active layer 201 is 0.05～0.2 micron.As an embodiment, said active layer 201 forms through the etching semiconductor substrate.Particularly, the said manufacture method that includes said active layer 201 comprises:
The said Semiconductor substrate 200 of partial etching forms active layer 201 on remaining Semiconductor substrate 200 surfaces.
As other embodiment, the manufacture method of said active layer 201 can also for:
Surface deposition epitaxial loayer in said Semiconductor substrate 200;
The said epitaxial loayer of partial etching forms said active layer 201.
Then, please refer to Fig. 6, form buried layer 202 on the surface of the Semiconductor substrate 200 of said active layer 201 both sides.The material of said buried layer 202 is the insulation material, and said insulation material is silica, silicon nitride, carborundum or silicon oxynitride.As preferred embodiment, said insulation material is a silica, and it can utilize oxidation technology or chemical vapor deposition method to make.
Said buried layer 202 is used for the source region of follow-up formation and drain region and 200 isolation of said Semiconductor substrate, thereby reduces the junction capacitance between said source region and drain region and the said Semiconductor substrate 200.
As preferred embodiment, the thickness range of said buried layer 202 is 5～100 dusts.
Then, please refer to Fig. 7, along the thickness direction of said active layer 201, the said buried layer 202 of etching forms the gap between said active layer 201 and buried layer 202.
Said etching technics can be dry etch process or wet-etching technology, and said etching technics is identical with prior art, and the known technology as those skilled in the art does not elaborate at this.
Said gap is used to expose the Semiconductor substrate 200 of below, thereby can in follow-up processing step, can carry out epitaxial deposition process.
As an embodiment, the width range in said gap is 10 nanometers～1 micron.
Then, please refer to Fig. 8, in the surface of said buried layer 202 and gap, form first epitaxial loayer 203, said first epitaxial loayer 203 flushes with said active layer 201.The material of said first epitaxial loayer 203, crystal orientation and resistivity and said Semiconductor substrate 200 are basic identical.As an embodiment, said first epitaxial loayer 203 utilizes epitaxial deposition process to make.Said epitaxial deposition process is identical with existing epitaxial deposition process, as those skilled in the art's known technology, does not do explanation at length at this.
Then, please refer to Fig. 9, form the groove that exposes said Semiconductor substrate 200 at said first epitaxial loayer 203, said groove is between said buried layer 202 and said active layer 202.
The width range of said groove is 3～30 nanometers.
As an embodiment, the manufacture method of said groove is:
Carry out etching technics along said active layer 201 thickness directions; Said first epitaxial loayer 203 of etching; Until the Semiconductor substrate 200 of exposing the below; Said etching technics is wet-etching technology or dry etch process, and the parameter setting of said wet-etching technology or dry etch process is identical with prior art, does not do at this and gives unnecessary details.
Then, please refer to Figure 10, in said first epitaxial loayer 203 surface and groove, form insulating barrier, the material of said insulating barrier can for silica, carborundum, carborundum or silicon oxynitride in interior insulation material.As an embodiment, the material of said insulating barrier is a silica, and it can utilize oxidation technology or chemical vapor deposition method to make.
Then, please refer to Figure 11, remove the insulating barrier that is positioned at said first epitaxial loayer 203 surfaces, the insulating barrier that is positioned at said groove forms buries side wall 204.The said side wall 204 of burying is used to prevent the source region of follow-up formation and the diffusion of the dopant ion between the drain region, thereby improves transistorized short-channel effect.
As an embodiment, the method for removing the insulating barrier that is positioned at said epitaxial loayer 203 surfaces is the method for existing cmp, and the method for said cmp is not done explanation at length as those skilled in the art's known technology at this.
Then, please refer to Figure 12, carry out etching technics, remove part and bury side wall 204, make the said degree of depth of burying the degree of depth of side wall 204, thereby help the carrying out of follow-up epitaxial deposition technology less than said groove.
Then, please refer to Figure 13, carry out epitaxial deposition process, form second epitaxial loayer 205 on said surface of burying side wall 204, active layer 201 and first epitaxial loayer 203.Wherein, the thickness range that is positioned at second epitaxial loayer 205 on said active layer 201 surfaces is 20～100 nanometers.
Because the said degree of depth of burying the degree of depth of side wall 204 less than said groove; When carrying out epitaxial deposition process; Said top of burying side wall 204 is exposed out; And the both sides at said top have said first epitaxial loayer 203, thereby said top can form second epitaxial loayer 205 above burying side wall 204 in that said epitaxial deposition technology is said from said two side direction of burying side wall 204, and said second epitaxial loayer 205 covers the said surface of burying side wall 204 and covering said first epitaxial loayer 203.
Said second epitaxial loayer 205 is used for making source region and drain region at follow-up processing step with said first epitaxial loayer 203.Being positioned at said thickness range of burying second epitaxial loayer 205 of side wall 204 tops is 10～300 nanometers, and said second epitaxial loayer 205 is as transistorized channel region, as the source region of follow-up formation and the conducting channel between the drain region.
Because utilize epitaxial deposition process to make, therefore material, crystal orientation and the resistivity of material, crystal orientation and the resistivity of said second epitaxial loayer 205 and said first epitaxial loayer 203 are basic identical.
Then, please refer to Figure 14, second epitaxial loayer, 205 surfaces above said active layer 201 form gate dielectric layer 206 and grid 207 successively.
The material of said gate dielectric layer 206 is a silica, and it can utilize oxidation technology to make.The thickness range of said gate dielectric layer 206 is 10～100 dusts.
The material of said grid 207 is a polysilicon, and it can utilize chemical vapor deposition method to make.
Then, please continue with reference to Figure 14, form gap oxide layer 208 at the both sides of said gate dielectric layer 206, the both sides and the top of grid 207, said gap oxide layer 208 is used to protect said gate dielectric layer 206 and grid 207.Said gap oxide layer 208 can utilize oxidation technology or depositing operation to make.The thickness range of said gap oxide layer 208 is 10～50 dusts.
Then; Please continue with reference to Figure 14, be mask with said grid 207 with gap oxide layer 208, carries out ion and inject; In second epitaxial loayer 205 of said grid 207 both sides, form light doping section 209; It is identical with the parameter of the ion injection of existing formation light doping section to form the parameter that the ion of said light doping section 209 injects, and as those skilled in the art's known technology, does not do explanation at length at this.
Then, please refer to Figure 15, form side wall 208 on the surface of second epitaxial loayer 205 of said grid 207 and gap oxide layer 208 both sides, said side wall 208 constitutes grid structures with said gate dielectric layer 206, grid 207, gap oxide layer 208.
The material of said side wall 208 is the insulation material, and the manufacture method of said side wall 208 is identical with prior art, as those skilled in the art's known technology, does not do explanation at length at this.
Then, please continue with reference to Figure 15, in second epitaxial loayer 205 of said grid structure both sides with in first epitaxial loayer 203, form source region 210 and drain region 211, said source region 210 and drain region 211 are positioned at the both sides of said isolation side walls 204.The manufacture method in said source region 210 and drain region 211 is utilized existing source/leakage ion to inject and is formed (SD implant).Because being positioned at said thickness range of burying second epitaxial loayer 205 of side wall 204 tops is 10～300 nanometers, said second epitaxial loayer 205 is as transistorized channel region, as the source region of follow-up formation and the conducting channel between the drain region.Being positioned at said thickness of burying second epitaxial loayer 205 above the side wall 204 is above-mentioned number range; Can guarantee transistorized operate as normal; And said isolation side walls 204 can effectively stop the dopant ion between source region 210 and the drain region 211 to spread through said isolation side walls 204 positions, helps improving short-channel effect.Because said first epitaxial loayer 203 belows are formed with buried layer 202; Said buried layer 202 can be isolated source region 210 and the drain region 211 and the Semiconductor substrate 200 of below, reduces to form junction capacitance between said source region 210 or drain region 211 and the said Semiconductor substrate 200.
Through above-mentioned steps, the transistor of formation please refer to Figure 15, and said transistor comprises:
First epitaxial loayer 203 is positioned at the surface and the said gap of said buried layer 202, and said first epitaxial loayer 203 flushes with said active layer 201;
Groove is positioned at said first epitaxial loayer 203, and said groove is between said buried layer 202 and said active layer 201;
Grid structure; Be positioned at second epitaxial loayer, 205 surfaces of said active layer 201 tops, said grid structure comprises gate dielectric layer 206, the gap oxide layer 208 that is positioned at grid 207, the both sides that are positioned at said gate dielectric layer 206 both sides and grid 207 and the top on said gate dielectric layer 206 surfaces that is positioned at said second epitaxial loayer 205 surfaces, the side wall 208 that is positioned at said grid 207 and gap oxide layer 208 both sides;
As an embodiment, the material of said buried layer 202 is the insulation material, and its thickness range is 5～100 dusts.The material of said buried layer 202 can be preferably silica for silica, silicon nitride, carborundum or silicon oxynitride.
Said material of burying side wall 204 is the insulation material, and its thickness range is 3～30 nanometers, and said material of burying side wall 204 can be silica, silicon nitride, carborundum or silicon oxynitride.The width range of said groove is 3～30 nanometers.
Please refer to Figure 15, as an embodiment, the thickness range of said active layer 201 is 0.05～0.2 micron, and the thickness range that is positioned at second epitaxial loayer 205 on said active layer 201 surfaces is 20～100 nanometers.Material, crystal orientation and the resistivity of said first epitaxial loayer 203 and second epitaxial loayer 205 and material, crystal orientation and the resistivity of said Semiconductor substrate 200 are basic identical.In order to guarantee that transistor can operate as normal; Said thickness of burying second epitaxial loayer 205 of side wall 204 tops should be 10～300 nanometers; In above-mentioned thickness range; Saidly bury the diffusion that side wall 204 can effectively prevent the dopant ion in adjacent source region 210 and drain region 211, thereby can improve transistorized short-channel effect.Because said first epitaxial loayer 203 belows are formed with buried layer 202; Said buried layer 202 can be isolated source region 210 and the drain region 211 and the Semiconductor substrate 200 of below, reduces to form junction capacitance between said source region 210 or drain region 211 and the said Semiconductor substrate 200.
To sum up, transistor provided by the invention and preparation method thereof forms isolation side walls between source region and drain region; Said isolation side walls can prevent the dopant ion diffusion between source region and the drain region; Improved transistorized short-channel effect, because said source region and drain region are positioned at the buried layer top, therefore said buried layer prevents to form junction capacitance between source region and drain region and the Semiconductor substrate; Reduce junction leakage, improved transistorized performance.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (20)
1. a transistorized manufacture method is characterized in that, comprising:
Semiconductor substrate is provided, and said semiconductor substrate surface is formed with active layer, and the material of said active layer is identical with the material of said Semiconductor substrate;
Semiconductor substrate surface in said active layer both sides forms buried layer, has the gap between said buried layer and the said active layer;
In said buried layer surface and gap, form first epitaxial loayer, said first epitaxial loayer flushes with said active layer;
In said first epitaxial loayer, form the groove that exposes said Semiconductor substrate, said groove is between said buried layer and said active layer;
In said groove, form and bury side wall, the said degree of depth of burying the thickness of side wall less than said groove;
Form second epitaxial loayer on said surface of burying side wall, active layer and first epitaxial loayer;
Second epi-layer surface above said active layer forms grid structure;
In second epitaxial loayer of said grid structure both sides with in first epitaxial loayer, form source region and drain region, said source region and drain region are positioned at said isolation side walls both sides.
2. transistorized manufacture method as claimed in claim 1 is characterized in that, being positioned at said thickness range of burying second epitaxial loayer of side wall top is 10～300 nanometers.
3. transistorized manufacture method as claimed in claim 1 is characterized in that, the material of said buried layer is the insulation material.
4. transistorized manufacture method as claimed in claim 3 is characterized in that, the thickness range of said buried layer is 5～100 dusts.
5. transistorized manufacture method as claimed in claim 1 is characterized in that, said material of burying side wall is the insulation material.
6. transistorized manufacture method as claimed in claim 5 is characterized in that, said thickness range of burying side wall is 3～30 nanometers.
7. transistorized manufacture method as claimed in claim 1 is characterized in that, the width range of said groove is 3～30 nanometers.
8. like claim 3 or 5 described transistorized manufacture methods, it is characterized in that said insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
9. transistorized manufacture method as claimed in claim 1 is characterized in that, the thickness range that is positioned at second epitaxial loayer on said active layer surface is 20～100 nanometers.
10. transistorized manufacture method as claimed in claim 1 is characterized in that, the thickness range of said active layer is 0.05～0.2 micron.
11. a transistor is characterized in that, comprising:
Semiconductor substrate, said semiconductor substrate surface is formed with active layer, and the material of said active layer is identical with the material of said Semiconductor substrate;
Buried layer is positioned at the semiconductor substrate surface of said active layer both sides, has the gap between said buried layer and the said active layer;
First epitaxial loayer is positioned at said buried layer surface and gap, and said first epitaxial loayer flushes with said active layer;
Groove is positioned at said first epitaxial loayer, and said groove and exposes said Semiconductor substrate between said buried layer and said active layer;
Bury side wall, be positioned at said groove, the said degree of depth of burying the thickness of side wall less than said groove;
Second epitaxial loayer is positioned at said surface of burying side wall, active layer and first epitaxial loayer;
Grid structure is positioned at second epi-layer surface of said active layer top;
The source region is positioned at said second epitaxial loayer and first epitaxial loayer of burying side wall one side.
The drain region is positioned at said second epitaxial loayer and first epitaxial loayer of burying the side wall opposite side.
12. transistor as claimed in claim 11 is characterized in that, being positioned at said thickness range of burying second epitaxial loayer of side wall top is 10～300 nanometers.
13. transistor as claimed in claim 11 is characterized in that, the material of said buried layer is the insulation material.
14. transistor as claimed in claim 12 is characterized in that, the thickness range of said buried layer is 5～100 dusts.
15. transistor as claimed in claim 11 is characterized in that, said material of burying side wall is the insulation material.
16. transistor as claimed in claim 15 is characterized in that, said thickness range of burying side wall is 3～30 nanometers.
17. transistor as claimed in claim 11 is characterized in that, the width range of said groove is 3～30 nanometers.
18. the transistor like claim 13 or 15 is characterized in that, said insulation material is silica, silicon nitride, carborundum or silicon oxynitride.
19. the transistor as claim 11 is stated is characterized in that, the thickness range that is positioned at second epitaxial loayer on said active layer surface is 20～100 nanometers.
20. the transistor as claim 11 is stated is characterized in that, the thickness range of said active layer is 0.05～0.2 micron.
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| CN201010559189.XA CN102479707B (en) | 2010-11-24 | 2010-11-24 | Transistor and manufacturing method for same |
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| CN201010559189.XA CN102479707B (en) | 2010-11-24 | 2010-11-24 | Transistor and manufacturing method for same |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4523213A (en) * | 1979-05-08 | 1985-06-11 | Vlsi Technology Research Association | MOS Semiconductor device and method of manufacturing the same |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN101789447A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor (MOS) transistor and formation method thereof |
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2010
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4523213A (en) * | 1979-05-08 | 1985-06-11 | Vlsi Technology Research Association | MOS Semiconductor device and method of manufacturing the same |
| CN101740393A (en) * | 2008-11-27 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN101789447A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor (MOS) transistor and formation method thereof |
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