CN102468902B - Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system - Google Patents

Abstract

A method for Turbo encoding rate matching/de-rate matching in an LTE system, the method comprising: determining an interleaving pattern according to the data length K of an encoding block; obtaining a system matrix from a system bit stream, and the first parity bit stream P1 and the second parity bit stream The check bit stream P2 is alternately stored to obtain the check matrix, starting from the first column of the system matrix, every 8 columns is a sub-system matrix, starting from the first column of the check matrix, every 8 columns is a sub-check matrix; determine the system matrix Address and check matrix address; the system bit stream data is packed and placed in the address, and the check bit stream data is packed and placed in the address of the check matrix; output the data in the system matrix address and the check matrix address by column , to obtain the bit stream after rate matching/de-rate matching. After applying the embodiment of the present invention, the speed of rate matching/de-matching can be accelerated.

Description

Method for rate matching/de-rate matching of turbo encoding in LTE system

technical field

The present invention relates to the technical field of communication, and more specifically, to a method for rate matching/de-rate matching of Turbo encoding in an LTE system.

Background technique

Long-term evolution (LTE) is the long-term evolution of 3G communication technology, which provides higher transmission rate for future wireless communication systems, and its high-speed code rate brings a heavy burden to the baseband processing of base stations and terminals. For the baseband processing in the LTE technology, how to speed up bit-level data processing speed, especially the rate matching processing speed of the transmission channel is one of the bottlenecks of the entire baseband processing.

第一校验比特流

第二校验比特流共计三路数据。和

三路比特流的长度相同，比特流的长度等于K+4，K是编码块的数据长度，4是尾比特。尾比特是经过Turbo编码剩余的比特。

和

三路比特流分别输入子块交织器，即比特流送入一个R行，32列的矩阵中，逐行写入，再进行列间置换，然后逐行读出分别得到与

相对应的输出比特流

与

相对应的输出比特流

与

相对应的输出比特流

进入比特收集模块。在比特收集模块中，收集的方式是系统比特流在前，第一校验比特流与第二校验比特流交替存放，构成一个完整的比特流w_k。再根据速率匹配的起始位置和速率匹配输出的长度，裁剪或者重复取数，直到满足输出长度要求输出比特流e_k至终端。The transmission channel rate matching process of the existing Turbo coding is shown in Fig. 1 . The original bit stream at the sender is turbo-encoded to obtain the system bit stream

first parity bit stream

Second parity bit stream A total of three channels of data. and

The lengths of the three bit streams are the same, and the length of the bit stream is equal to K+4, where K is the data length of the coding block, and 4 is the tail bit. The tail bits are the remaining bits after turbo encoding.

and

The three-way bit streams are respectively input into the sub-block interleaver, that is, the bit streams are sent into a matrix of R rows and 32 columns, written row by row, and then permuted between columns, and then read out row by row to obtain and

corresponding output bitstream

and

corresponding output bitstream

and

corresponding output bitstream

Enter the bit collection module. In the bit collection module, the collection method is that the system bit stream comes first, and the first check bit stream and the second check bit stream are alternately stored to form a complete bit stream w _k . Then, according to the starting position of the rate matching and the length of the rate matching output, the number is cut or repeated until the output length requirement is met, and the bit stream e _k is output to the terminal.

第一校验比特流

第二校验比特流

同时到达才开始速率匹配操作，而是将Turbo后编码的各个比特流编码后分别进行速率匹配。由于需要反复读取内存中比特流中的数据，因此上述速率匹配的处理速度较低。According to the above analysis of the overall process, there is no need to wait until the system bit stream

first parity bit stream

Second parity bit stream

The rate matching operation starts only when they arrive at the same time, but each bit stream encoded after Turbo is encoded and rate matched respectively. Since the data in the bit stream in the memory needs to be read repeatedly, the processing speed of the above-mentioned rate matching is low.

Contents of the invention

The embodiment of the present invention proposes a method for rate matching/de-matching of turbo coding in an LTE system, which can speed up the speed of rate matching/de-matching.

A method for Turbo encoding rate matching/de-rate matching in an LTE system, the method comprising:

Determine the interleaving mode according to the data length K of the coding block;

The system matrix is obtained from the system bit stream, and the first parity bit stream P1 and the second parity bit stream P2 are stored alternately to obtain the parity check matrix. Starting from the first column of the system matrix, every 8 columns is a subsystem matrix. Starting from the first column of the matrix, every 8 columns are a sub-check matrix;

Start from N=1 and increase by 1 until N=8, extract the Nth column of each subsystem matrix in turn and calculate the system matrix address corresponding to the column data according to the interleaving mode, start from N=1 and increase by 1 until N=8, after extracting the Nth column of each sub-parity check matrix in turn, calculate the check matrix address corresponding to the column data according to the interleaving mode;

In each extraction, 4 words of the system bit stream are selected to be packed and placed in the address of the system matrix according to predetermined rules, and 4 words of P1 and 4 words of P2 are selected to be packed and placed in the verification according to predetermined rules In the address of the matrix, the selection includes S cycles, S is equal to the row number R of the subsystem matrix minus 1 and divided by 4 and rounded down, and R is equal to K plus 4 and divided by 32 and rounded up;

Output the data in the address of the system matrix and the address of the check matrix in columns to obtain the bit stream after rate matching/de-matching.

The determining the interleaving mode according to the data length K of the coding block includes taking a remainder of K to 32, and determining the interleaving mode according to the remainder.

After extracting the Nth column of each subsystem matrix in turn, calculating the system matrix address corresponding to the column data according to the interleaving mode includes determining the interleaving index according to the interleaving mode, and sequentially offsetting each of the Nth columns of each subsystem matrix by the interleaving index. The address of the data obtains the middle offset address of each data of this column, and then obtains the system matrix address according to the described middle offset address of interleaving pattern and N overall offset;

After extracting the Nth column of each sub-parity check matrix in turn, calculating the check matrix address corresponding to the column data according to the interleaving mode includes determining the interleaving index according to the interleaving mode, and offsetting the Nth column of each sub-parity check matrix in turn by the interleaving index The address of each data in the column obtains the middle offset address of each data in the column, and then the check matrix address is obtained by offsetting the middle offset address according to the interleaving mode and N overall.

N_cb为速率匹配软Buffer大小，RV是冗余版本参数。Before the address of each data in the Nth column of each subsystem matrix is sequentially offset by the interleaving index to obtain the intermediate offset address, it further includes calculating the starting column position of the system matrix, and the starting position of the system matrix is equal to k ₀ ,

N _cb is the rate matching soft buffer size, and RV is the redundancy version parameter.

When k ₀ is greater than 32, the starting column position of the system matrix is equal to k′ ₀ ,

The obtaining the system matrix address by overall offsetting the intermediate offset address according to the interleaving pattern and N includes determining the overall offset according to the interleaving pattern and N, and then offsetting the intermediate offset address as a whole according to the overall offset to obtain the system matrix address. matrix address;

Obtaining the parity check matrix address by offsetting the intermediate offset address according to the interleaving mode and N as a whole includes determining the overall offset according to the interleaving mode and N, and then offsetting the intermediate offset address as a whole according to the overall offset to obtain check matrix address.

The determining the overall offset according to the interleaving mode and N includes determining padding bits according to the interleaving mode, and the overall offset H is equal to the sum of 32 minus the padding bits and the Nth data of P1.

The determining the overall offset according to the interleaving mode and N includes determining redundant bits according to the interleaving mode, and the overall offset H is equal to the difference between the Nth data of P1 and the stuffing bits.

The words of the selected four system bit streams are packaged and placed in the system matrix address according to predetermined rules, including,

Starting from the 0th system word, take out the words of the bit stream every 8 words to obtain the first system word, the second system word, the third system word and the fourth system word; respectively take the highest value of the four system words The data constitutes the output word of the first system, the second highest data constitutes the output word of the second system, the second lowest data constitutes the output word of the third system, and the lowest data constitutes the output word of the fourth system;

The first system output word is placed in the address of the first data to the fourth data in the S row of the system matrix, and the second system output word is placed in the ninth row of the S row of the system matrix Data to the address of the 12th data, the third system output word is placed in the address of the 5th data to the 8th data in the S row of the system matrix, and the fourth system output word is placed in In the addresses of the 13th to 16th data in row S of the system matrix.

The selection of 4 P1 words and 4 P2 words is packed and placed in the address of the check matrix according to predetermined rules, including,

Take out the 0th word and the 8th word from P1 in sequence, record them as the first check word and the second check word in sequence, take out the 1st word and the 9th word from P2 in sequence, and record them as the third check word in turn word and the fourth check word;

Take the highest data from the first check word to the fourth check word to form the first check output word, the second highest data form the second check output word, the second lowest data form the third check output word, and the lowest data form the second check output word. Four verification output words;

The first check output word is placed in the address of the first data to the fourth data in the S row of the check matrix, and the second check output word is placed in the S check matrix In the address of the 9th data to the 12th data in the row, the third verification output word is placed in the address of the 5th data to the 8th data in the S row of the parity check matrix, and the Four check output words are placed in the address of the 13th data to the 16th data in the S row of the check matrix;

Then, take out the 16th word and the 24th word from P1 in sequence, record them as the fifth check word and the sixth check word in sequence, take out the 17th data and the 25th data from P2 in sequence, and record them as the 1st check word in turn Seven check characters and eighth check characters;

Take the highest data from the fifth check word to the eighth check word to form the fifth check output word, the next highest data form the sixth check output word, the second lowest data form the seventh check output word, and the lowest data form the sixth check output word. Eight check output words;

Place the fifth check output word in the address of the first data to the fourth data in row S+1 of the check matrix, and place the sixth check output word in the check matrix In the address of the 9th data to the 12th data in the S+1th row, the seventh check output word is placed in the address of the 5th data to the 8th data in the S+1th row of the parity check matrix , the eighth check output word is placed in the addresses of the 13th to 16th data in row S+1 of the check matrix.

When remaining data exists after S cycles, one remaining data is taken each time and placed in the address of the remaining data.

When N is equal to 8, it further includes filling redundant bits of system data according to the interleaving mode, and filling redundant bits of check data according to the interleaving mode.

As can be seen from the above technical solutions, in the embodiment of the present invention, firstly, the interleaving pattern is determined according to the data length of the coding block, and then the system matrix is divided into subsystem matrices and the check matrix is divided into sub check matrices; according to the interleaving The mode calculates the system matrix address and check matrix address by column, packs the system bit stream of every four words into the system matrix address, packs P1 of every four words and P2 of every four words and places them in the parity check matrix In the address, the system matrix and parity check matrix are output by column. Placing the packed data in the corresponding address is beneficial to the pipeline operation of the processor, thereby speeding up the speed of rate matching. The same technical solution can also be applied to de-rate matching, thereby speeding up the de-rate matching.

Description of drawings

FIG. 1 is a schematic diagram of rate matching of Turbo coding in the prior art;

Fig. 2 is the schematic flow chart of the method for Turbo encoding rate matching in the LTE system of the present invention;

FIG. 3 is a schematic diagram of interleaving mode 1 in an embodiment of the present invention;

FIG. 4 is a schematic diagram of interleaving mode 2 in an embodiment of the present invention;

FIG. 5 is a schematic diagram of interleaving mode 3 in an embodiment of the present invention;

FIG. 6 is a schematic diagram of interleaving mode 4 in an embodiment of the present invention;

Fig. 7 is a schematic diagram of input data storage according to an embodiment of the present invention;

Fig. 8 is a schematic diagram of a data packing operation in an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

In the embodiment of the present invention, the system bit stream, the first parity bit stream (P1) and the second parity bit stream (P2) are processed in parallel at the same time, and the data read and write operations of four consecutive words are constructed to be suitable for mainstream processors. Realize the data access structure of packed data operations, and reduce the number of reads and writes to memory. The processing method is simple, the loop structure is clear, and there is no operation that interrupts the pipeline such as judgment jumps. The processor can fetch data and calculate faster, and directly map the interleaved data of the sub-blocks to the output position, thereby speeding up the rate matching. speed.

In the present invention, Turbo encoding rate matching includes the following steps A to E:

Step A, determine the interleaving mode according to the data length K of the coded block.

Step B. Obtain the system matrix from the system bit stream, and store P1 and P2 alternately to obtain the check matrix. Starting from the first column of the system matrix, every 8 columns is a subsystem matrix, and every 8 columns starting from the first column of the check matrix is a sub-check matrix.

P1 and P2 are stored alternately to obtain a parity check matrix in the same manner as in the prior art, and will not be repeated here. The system matrix has a total of 32 columns and is composed of four subsystem matrices; the check matrix has a total of 32 columns and is also composed of four sub-check matrices.

Step C, sequentially extracting the Nth column of each subsystem matrix and then calculating the system matrix address corresponding to the column data according to the interleaving mode, sequentially extracting the Nth column of each sub-check matrix and calculating the checksum corresponding to the column data according to the interleaving mode matrix address.

The Nth column of the subsystem matrix and the Nth column of the sub-check matrix are extracted each time until 8 cycles are completed to calculate the data address in the system matrix and the data address in the check matrix. When N is less than 8, continue to extract the N+1th column of each sub-matrix, and the initial value of N is 1.

Step D, select the words of 4 system bit streams to pack and place in the address of the system matrix, select the words of 4 P1 and 4 words of P2 to pack and place in the address of the parity check matrix, the selected Including S cycles, S is equal to the number of rows of the sub-matrix R minus 1 divided by 4 and rounded down, and R is equal to K plus 4 divided by 32 and rounded up.

The data packing processing of the system bit stream is placed in the data address of the system matrix; the data packing processing of P1 and P2 is placed in the data address of the parity check matrix. Each word includes 4 data, and in the technical solution of the present invention, selecting 4 words means selecting 16 data.

Step E, outputting the data in the address of the system matrix and the address of the parity check matrix by column to obtain the bit stream after rate matching.

Referring to accompanying drawing 2 is the schematic flow chart of the method for Turbo coding rate matching in the LTE system, specifically comprises the following steps:

Step 201. Determine an interleaving mode.

Since the sub-block interleaving matrix is fixed at 32 columns, the remainder of 32 is taken according to the data length K of the coding block. There are four cases of the remainder, namely 0, 8, 16 and 24, and different bits need to be filled for different remainders. If the remainder is 0, the coding block belongs to interleaving mode 1; if the remainder is 8, the coding block belongs to interleaving mode 2; if the remainder is 16, the coding block belongs to interleaving mode 3; if the remainder is 24, the coding block belongs to interleaving mode 4. 4 types The interleaving mode determines the offset of the matrix data address

LTE specifies 188 fixed code block lengths. The following analyzes the 188 code block lengths:

There are a total of 60 encoding block lengths with a step size of 8:

40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120, 128, 136, 144, 152, 160, 168, 176, 184, 192, 200, 208, 216, 224, 232, 240, 248, 256, 264, 272, 280, 288, 296, 304, 312, 320, 328, 336, 344, 352, 360, 368, 376, 384, 392, 400, 408, 416, 424, 432, 440, 448, 456, 464, 472, 480, 488, 496, 504, 512.

There are a total of 32 coded block lengths with a step size of 16

528, 544, 560, 576, 592, 608, 624, 640, 656, 672, 688, 704, 720, 736, 752, 768, 784, 800, 816, 832, 848, 864, 880, 896, 912, 928, 944, 960, 976, 992, 1008, 1024.

There are a total of 32 coded block lengths with a step size of 32

1056, 1088, 1120, 1152, 1184, 1216, 1248, 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, 2048.

There are a total of 64 coded block lengths with a step size of 64

2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, 4096, 4160, 4224, 4288, 4352, 4416, 4480, 4544, 4608, 4672, 4736, 4800, 4864, 4928, 4992, 5056, 5120, 5184, 5248, 5312, 5376, 5440, 5504, 5568, 5632, 5696, 5760, 5824, 5888, 5952, 6016, 6080, 6144.

Among them, for the coded blocks with a step size of 32 and 64, K takes a remainder of 0 for 32, which all meet the requirements of interleaving mode 1; for a coded block with a step size of 16, 528 satisfies interleaving mode 3, and 544 satisfies interleaving mode 1, followed by Alternate; among the coding blocks with a step size of 8, there are coding blocks satisfying interleaving mode 3 and coding blocks satisfying interleaving mode 1.

The remainder of 32 encoding blocks is obtained to obtain the interleaving mode to which each encoding block belongs.

Coding block length corresponding to interleaving mode 1: 127 types in total

64, 96, 128, 160, 192, 224, 256, 288, 320, 352, 384, 416, 448, 480, 512, 544, 576, 608, 640, 672, 704, 736, 768, 800, 832, 864, 896, 928, 960, 992, 1024, 1056, 1088, 1120, 1152, 1184, 1216, 1248, 1280, 1312, 1344, 1376, 1408, 1440, 1472, 1504, 1536, 1568, 1600, 1632, 1664, 1696, 1728, 1760, 1792, 1824, 1856, 1888, 1920, 1952, 1984, 2016, 2048, 2112, 2176, 2240, 2304, 2368, 2432, 2496, 2560, 2624, 2688, 2752, 2816, 2880, 2944, 3008, 3072, 3136, 3200, 3264, 3328, 3392, 3456, 3520, 3584, 3648, 3712, 3776, 3840, 3904, 3968, 4032, 4096, 4160, 4224, 4288, 4352, 4416, 4480, 4544, 4608, 4672, 4736, 4800, 4864, 4928, 4992, 5056, 5120, 5184, 5248, 5312, 5376, 5440, 5504, 5568, 5632, 5696, 5760, 5824, 5888, 5952, 6016, 6080, 6144.

Coding block length corresponding to interleaving mode 2: 15 types in total

40, 72, 104, 136, 168, 200, 232, 264, 296, 328, 360, 392, 424, 456, 488.

Coding block length corresponding to interleaving mode 3: 31 types in total

48, 80, 112, 144, 176, 208, 240, 272, 304, 336, 368, 400, 432, 464, 496;

528, 560, 592, 624, 656, 688, 720, 752, 784, 816, 848, 880, 912, 944, 976, 1008.

Coding block length corresponding to interleaving mode 4: 15 types in total

56, 88, 120, 152, 184, 216, 248, 280, 312, 344, 376, 408, 440, 472, 504.

Step 202, dividing the system matrix and parity check matrix.

The system bit stream forms four subsystem matrices in turn, and each subsystem matrix has 8 columns in total. The first 7 columns have R data in each column, and the 8th column has R-1 data; the check bit stream forms four sub-check matrices in turn, Each sub-check matrix has 8 columns in total, the first 7 columns each have 2(R-1) data, and the 8th column has 2R data. Since the check matrix is obtained by storing P1 and P2 alternately, the length of each column of data in the check matrix is longer than the length of each column of data in the system matrix.

The following is an example for each interleaving mode:

Interleaving mode 1: corresponding to stuffing bits _ND =28, that is, the case where the coded block length in the length of the bit stream is divisible by 32. Example K=6144, see accompanying drawing 3.

The shorter length of the first 32 columns corresponds to the system matrix, and the longer length of the last 32 columns corresponds to the parity check matrix. The system bit is composed of four subsystem matrices in turn, where the short rectangular bar is a column without redundant bits and has a length of R-1, and the long rectangular bar is a column with redundant bits and has a length of R. The extra bits are extra bits that do not satisfy the column length in the interleaving matrix. The parity bit is composed of four sub-parity check matrices in turn, wherein the short rectangular bar is a column without redundant bits and has a length of 2(R-1), and the long rectangular bar is a column containing redundant bits and has a length of 2R.

Interleaving mode 2: corresponding to N _D =20, that is, the case where the modulo 32 of the coded block length in the length of the bit stream is 8. Example K=488, see accompanying drawing 4.

Interleaving mode 3: corresponding to N _D =12, that is, the case where the modulo 32 of the coding block length in the length of the bit stream is 16. Example K=496, see accompanying drawing 5.

Interleaving mode 4: corresponding to N _D =4, that is, the case where the modulo 32 of the coding block length in the length of the bit stream is 32. Example K=504, see accompanying drawing 6.

Similar to interleaving mode 1, interleaving modes 2, 3, and 4 differ from interleaving mode 1 in that K is different, and the corresponding column lengths of the system matrix and parity check matrix are different.

Step 203, calculating the system matrix address and check matrix address of the Nth column.

After sequentially extracting the Nth column of each subsystem matrix, calculate the system matrix address corresponding to the column data according to the interleaving mode, and sequentially extract the Nth column of each sub-check matrix, and calculate the check matrix address corresponding to the column data according to the interleaving mode.

Each subsystem matrix has a total of 8 columns, and the data address of one column of each subsystem matrix is calculated in one cycle, and all system matrix addresses can be calculated by performing a total of eight cycles; correspondingly, each sub-check matrix is also 8 columns, and one cycle calculates each A column of data addresses of sub-check matrices, a total of eight cycles can be used to calculate all check matrix addresses. So the initial value of N is 1, and the maximum value of N is 8.

Step 2031, calculate the interleaving index.

The interleaving index is a list of offsets for each data address in the matrix determined according to the interleaving mode. For different interleaving modes, calculate the offset of each data address in each interleaving mode, and increase the corresponding offset for each data address in the corresponding system matrix to obtain the intermediate offset address, and then according to the interleaving mode and N overall Offset the middle offset address of each data to obtain the system matrix address; add the corresponding offset to each data address in the parity check matrix to obtain the middle offset address, and then offset the middle offset of each data according to the interleaving mode and N as a whole Shift the address to get the parity check matrix address.

The calculation of the interleaving index is described in detail below:

First, the starting column k ₀ is calculated according to the redundancy version parameter RV and the size of the rate matching soft Buffer N _cb , and the formula described in the LTE protocol:

In the above formula, R is the number of rows of the subsystem matrix, N _cb is the size of the rate matching soft buffer, RV is the parameter of the redundancy version, and the range is 0, 1, 2, 3. Among them, N _cb is a known parameter, and RV is a known parameter.

In addition, due to the particularity of the matrix arrangement, if k ₀ is greater than 32, the starting column position of the system matrix is equal to k′ ₀ :

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="k"\; filenames="HSA00000333503700011.png,HSA00000333503700042.png"\; state="\{\{state\}\}">k</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}^{<span\; class="notranslate">\; \&prime;</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="k"\; filenames="HSA00000333503700011.png,HSA00000333503700042.png"\; state="\{\{state\}\}">k</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 16</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Formula (2) guarantees that the value range of k′ ₀ is 2 to 53. Since the check matrix is a combination of P1 and P2, if the number of data in each column of the check matrix is the same as that of the system matrix, the check matrix should have 64 columns. For the LTE system, P1 and P2 are calculated separately, and the parity check matrix has 96 columns in total. If calculated according to the original formula (1), the value range of k ₀ is 2 to 74. After calculation by the formula (2), it is equivalent to converting the original corresponding number of columns into the number of columns where the parity check matrix is located. For example, the original column is 74, but it is in the 53rd column after calculation by the formula (2).

After the starting column position of the system matrix is determined, the interleaving indexes are respectively calculated according to the four interleaving modes.

To assign a value to the length of each column is to initialize the length of each column. The assignment may be R, R-1 or 2R, 2(R-1) in total.

The output index value at the beginning of column K is 0, the output index value at the beginning of column K+1 is the output index value at the beginning of column K plus the length of column K, and so on. In particular, due to the RV parameter, column 0 will always be placed behind, so the output index value at the beginning of column 0 is the output index value at the beginning of column 63 plus the length of column 63.

In addition, it is also necessary to calculate the output address index of the redundant bit. For the system matrix, since there is only one redundant bit, the output address of the redundant bit is equivalent to the output address index of the next column of the column where the redundant bit is located minus 1; Since there are 2 redundant bits, the output address of the redundant bit is equal to the output address index of the next column of the column where the redundant bit is located minus 2.

Combined with the number of stuffing bits, the characteristics of the following four interleaving modes can be obtained.

Interleaving mode 1, N _D =28, the interleaving mode of systematic bits and P1 is as follows:

<4, 20, 12, 28, 8, 24, 16, 0, 6, 22, 14, 30, 10, 26, 18, 2, 5, 21, 13, 29, 9, 25, 17, 1, 7 , 23, 15, 31, 11, 27, 19, 3>

When the system bit stream and P1 take the 31st element, that is, the 59th column in the matrix in FIG. 3 , P2 takes the 0th element. At this time, there is a jump in data fetching. Therefore, in order to construct a special structure, the starting addresses of the output columns of the 59 to 64 columns in the matrix we defined need to be shifted backward by 1 unit, and the corresponding column The start address of redundant bits is shifted backward by 1 unit.

Interleaving mode 2, N _D =20, the interleaving mode of systematic bits and P1 is as follows:

<12, 28, 20, 4, 16, 0, 24, 8, 14, 30, 22, 6, 18, 2, 26, 10, 13, 29, 21, 5, 17, 1, 25, 9, 15 , 31, 23, 7, 19, 3, 27, 11>

When the system bit stream and P1 take the 31st element, that is, the 57th column in the matrix in FIG. 4 , P2 takes the 0th element. At this time, there is a jump in data fetching. Therefore, in order to construct a special structure, the starting addresses of the output columns of the 57 to 64 columns in the matrix we defined need to be shifted backward by 1 unit, and the corresponding column The start address of redundant bits is shifted backward by 1 unit.

Interleaving mode 3, N _D =12, the interleaving mode of systematic bits and P1 is as follows:

<20, 4, 28, 12, 24, 8, 0, 16, 22, 6, 30, 14, 26, 10, 2, 18, 21, 5, 29, 13, 25, 9, 1, 17, 23 , 7, 31, 15, 27, 11, 3, 19>

When the system bit stream and P1 take the 31st element, that is, the 58th column in the matrix in FIG. 5 , P2 takes the 0th element. At this time, there is a jump in data fetching. Therefore, in order to construct a special structure, the starting addresses of the output columns of the 58 to 64 columns in the matrix we defined need to be shifted backward by 1 unit, and the corresponding column The start address of redundant bits is shifted backward by 1 unit.

For interleaving mode 4, N _D =4, the interleaving mode of systematic bits and P 1 is as follows:

<28, 12, 4, 20, 0, 16, 8, 24, 30, 14, 6, 22, 2, 18, 10, 26, 29, 13, 5, 21, 1, 17, 9, 25, 31 , 15, 7, 23, 3, 19, 11, 27>

When the system bit stream and P1 take the 31st element, that is, the 56th column in the matrix, P2 takes the 0th element. At this time, there is a jump in the data fetching. Therefore, in order to construct a special structure, it is necessary to shift the starting addresses of the output columns of the 56 to 64 columns in the matrix backward by 1 unit, and at the same time set the redundant bits of the corresponding columns to start The address is offset backward by 1 unit.

The size of the interleaving index is 64+56=120 lengths. The first 64 indexes store the starting address index of 32 columns in the system matrix and 32 columns in the parity check matrix, that is, the position of the first bit in the output cache; the last 56 indexes are the extra bits of each special length column in The location in the output cache. Since the two redundant bits in the long column containing redundant bits of the check matrix are closely connected, only one address index needs to be calculated, and the address of the other redundant bit can be added according to the address index.

The system matrix and parity check matrix of interleaving mode 1 have 4 redundant bits in the last row respectively. The reason why it is the last row here is that the padding bit NULL is placed in the last row, so it is called redundant bits, and only 8 redundant bits are needed. . Likewise, interleaving mode 2 requires an index of 24 remaining bits. Interleaving mode 3 requires an index of 40 remaining bits, and interleaving mode 4 requires an index of 56 remaining bits. According to interleaving mode 4, the maximum length is 56, and there are 120 indexes in total. These 120 address indexes determine the offset of the output data storage.

The above index parameters are precomputed before rate matching. Since the LTE system has multiple coding blocks with the same length, it is only necessary to calculate the interleaving index once for the same coding block.

Step 2032: Obtain the system matrix address and check matrix address respectively according to the interleaving mode and the intermediate offset address of the N overall offset.

Since the block interleaving matrix in the sub-block interleaver has 32 columns, the stuffing bits of the coding block are equal to 32 minus K+4 and taking the remainder of 32. The lengths of the systematic bit stream, P1 and P2 are all equal to K+4. That is: the _ND corresponding to the interleaving mode 1 is equal to 28; the _ND corresponding to the interleaving mode 2 _is equal to 20; the ND corresponding to the interleaving mode 3 is equal to 12; the _ND corresponding to the interleaving mode 4 is equal to 4.

According to _ND combined with the first eight data of the interleaving mode of P 1 in Table 1, the overall offset of each column of data in the four interleaving modes can be obtained. When _ND is subtracted from 32, the sum of the Nth data of P1 is less than or equal to 32, and the overall offset H is equal to the sum of the Nth data of P1 after subtracting _ND from 32; when _ND is subtracted from 32, it is equal to The sum of the Nth data of P1 is greater than 32, and the overall offset H is equal to the Nth data of P1 minus N _D .

Table 1 P1 parity check matrix interleaving mode

<0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, 1, 17, 9, 25, 5, 21, 13, 29, 3 , 19, 11, 27, 7, 23, 15, 31>

Interleaving mode 1: N _D = 28 corresponds to H of each column: 4, 20, 12, 28, 8, 24, 16, 0;

Interleaving mode 2: N _D = 20 corresponds to H of each column: 12, 28, 20, 4, 16, 0, 24, 8;

Interleaving mode 3: N _D = 12 corresponds to H of each column: 20, 4, 28, 12, 24, 8, 0, 16;

Interleaving mode 4: N _D =4 corresponds to H of each column: 28, 12, 4, 20, 0, 16, 8, 24.

That is, for the coding block of interleaving mode 1, the overall offset of the first column of the subsystem matrix and the sub-parity check matrix is 4, and the overall offset of the second column is 20, and so on, the third column to the first column can be obtained. The overall offset of the eight columns. The overall offset herein refers to the offset of the address of the column data.

Step 204: Pack the data of the system bit stream in a loop S times, and pack the data of P1 and P2.

In step 203, the addresses corresponding to the data in the system matrix and check matrix have been calculated. In step 204, the data of the system bit stream is packaged and placed in the address of the system matrix; the data of P1 and P2 are packaged and placed in the address of the parity check matrix. The number of cycles S is equal to the number of rows of the subsystem matrix R minus 1 divided by 4 and rounded down, and R is equal to K plus 4 divided by 32 and rounded up.

If there is any remaining data after S cycles, one piece of remaining data is taken each time and placed in the address of the remaining data.

The storage of three code streams for the system bit stream, P1 and P2 input data is shown in FIG. 7 . The first word in the system bit stream consists of data S ₀ , data S ₁ , data S ₂ and data S ₃ , and the first word of P1 consists of data P ₀ , data P ₁ , data P ₂ and data P ₃ constituted, while the first word of P2 consists only of data B ₀ in the fourth position. If the system bit stream and the input data of P1 and P2 do not meet the above conditions, the bit streams that do not meet the conditions need to be adjusted to the above conditions. The adjustment method is a prior art, and will not be repeated here.

The following describes in detail how to pack the words of the system bit stream into addresses in the system matrix.

Starting from the 0th word, the words of the system bit stream are extracted every 8 words to obtain the first system word A0, the second system word A8, the third system word A16 and the fourth system word A24. Referring to Figure 8, take the highest data of the four system words to form the first system output word B0, the second highest data to form the second system output word B8, the second lowest data to form the third system output word B16, and the lowest data to form the fourth system Word B16 is output. The above process is a data packing process. Among them, one word is composed of four data.

Place B0 in the address of the 1st to 4th data in row S of the system matrix, place B8 in the address of the 9th to 12th data in row S of the system matrix, and place B16 in the system matrix In the address of the 5th data to the 8th data in the S row, place B24 in the 13th to 16th data in the fourth column of the S row of the system matrix.

After performing S cycles, the words in the system bit stream are respectively placed in addresses in the system matrix.

Packing the data of P1 and P2 into the addresses in the check matrix is different from the data packing of the system matrix in that the number of data in the check matrix is twice the number of data in the system matrix, so the system matrix Once the data is packaged, the corresponding parity check matrix is used for secondary data packaging.

Take out the 0th word and the 8th word from P1 in sequence, record them as the first check word and the second check word in sequence, take out the 1st word and the 9th word from P2 in sequence, and record them as the third check word in turn word and the fourth check word.

Take the highest data from the first check word to the fourth check word to form the first check output word, the second highest data form the second check output word, the second lowest data form the third check output word, and the lowest data form the second check output word. Four parity output words.

Place the first verification output word in the address of the first data to the fourth data in the S row of the check matrix, and place the second verification output word in the ninth data to the 12th data in the S row of the check matrix In the address of the data, the third check output word is placed in the address of the 5th data to the 8th data in the S row of the check matrix, and the fourth check output word is placed in the S check matrix In the address of the 13th data to the 16th data in the row.

Then, take out the 16th word and the 24th word from P1 in sequence, record them as the fifth check word and the sixth check word in sequence, take out the 17th word and the 25th word from P2 in sequence, and record them as the 1st check word in turn The seventh checksum and the eighth checksum.

Take the highest data from the fifth check word to the eighth check word to form the fifth check output word, the next highest data form the sixth check output word, the second lowest data form the seventh check output word, and the lowest data form the sixth check output word. Eight parity output words.

Place the fifth verification output word in the address of the first data to the fourth data in row S+1 of the parity check matrix, and place the sixth verification output word in the ninth row of S+1 row of the parity check matrix Data to the address of the 12th data, place the seventh verification output word in the address of the 5th data to the 8th data in the S+1 row of the verification matrix, and place the eighth verification output word in the check matrix In the address of the 13th data to the 16th data in row S+1 of the test matrix.

Step 205, judging that N is less than 8.

Determine whether N is less than or equal to 8, if N is less than 8, set N+1 and return to step 103; otherwise, execute step 106.

Since the system matrix is composed of four subsystem matrices, the check matrix is composed of four sub-check matrices. Both the subsystem matrix and the sub-check matrix have 8 columns of data. When N=8, each column of data in the subsystem matrix is placed in the address of the system matrix, and each column of data in the sub-check matrix is placed in the address of the check matrix. address.

So far, the data in the address of the system matrix and the data in the address of the parity check matrix are data after rate matching.

Step 206 , output the data in the address of the system matrix and the data in the address of the parity check matrix column by column.

From column 1 to column 32, the data in the address of the system matrix is sequentially output; then, from column 33 to column 64, the data in the check matrix address is output sequentially to obtain the data after rate matching.

In addition, the technical solution from step 201 to step 206 is also applicable to turbo coding and rate matching in LTE system. The implementation process of the technical solution is the same as that of Turbo coding rate matching, the difference is that in step 2031, the position of the start column is equal to 0.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (9)

1. a method for Turbo encoding rate matching/solution rate matching in an LTE system, it is characterized in that, the method comprises: Determine the interleaving mode according to the data length K of the coding block; The determination of the interleaving mode according to the data length K of the coding block includes: K takes a remainder of 32, and if the remainder is 0, the coding block belongs to the interleaving mode 1; if the remainder is 8, the coding block belongs to the interleaving mode 2; if the remainder is 16, the coding The block belongs to interleaving mode 3; if the remainder is 24, the coded block belongs to interleaving mode 4; The system matrix is obtained from the system bit stream, and the first parity bit stream P1 and the second parity bit stream P2 are stored alternately to obtain the parity check matrix. Starting from the first column of the system matrix, every 8 columns is a subsystem matrix. Starting from the first column of the matrix, every 8 columns are a sub-check matrix; Start from N=1 and increase by 1 until N=8, extract the Nth column of each subsystem matrix in turn, and calculate the system matrix address corresponding to the column data according to the interleaving mode, start from N=1 and increase by 1 until N=8, sequentially extract the Nth column of each sub-check matrix and calculate the address of the check matrix corresponding to the column data according to the interleaving mode; In each extraction, 4 words of the system bit stream are selected to be packed and placed in the address of the system matrix according to predetermined rules, and 4 words of P1 and 4 words of P2 are selected to be packed and placed in the verification according to predetermined rules In the address of the matrix, the selection includes S cycles, S is equal to the row number R of the subsystem matrix minus 1 and divided by 4 and rounded down, and R is equal to K plus 4 and divided by 32 and rounded up; The words of the selected four system bit streams are packaged and placed in the system matrix address according to predetermined rules, including, Starting from the 0th system word, take out the words of the bit stream every 8 words to obtain the first system word, the second system word, the third system word and the fourth system word; respectively take the highest value of the four system words The data constitutes the output word of the first system, the second highest data constitutes the output word of the second system, the second lowest data constitutes the output word of the third system, and the lowest data constitutes the output word of the fourth system; The first system output word is placed in the address of the first data to the fourth data in the S row of the system matrix, and the second system output word is placed in the ninth row of the S row of the system matrix Data to the address of the 12th data, the third system output word is placed in the address of the 5th data to the 8th data in the S row of the system matrix, and the fourth system output word is placed in In the addresses of the 13th to 16th data in row S of the system matrix; The selection of 4 P1 words and 4 P2 words is packed and placed in the address of the check matrix according to predetermined rules, including, Take out the 0th word and the 8th word from P1 in sequence, record them as the first check word and the second check word in sequence, take out the 1st word and the 9th word from P2 in sequence, and record them as the third check word in turn word and the fourth check word; Take the highest data from the first check word to the fourth check word to form the first check output word, the second highest data form the second check output word, the second lowest data form the third check output word, and the lowest data form the second check output word. Four verification output words; The first check output word is placed in the address of the first data to the fourth data in the S row of the check matrix, and the second check output word is placed in the S check matrix In the address of the 9th data to the 12th data in the row, the third verification output word is placed in the address of the 5th data to the 8th data in the S row of the parity check matrix, and the Four check output words are placed in the address of the 13th data to the 16th data in the S row of the check matrix; Then, take out the 16th word and the 24th word from P1 in sequence, record them as the fifth check word and the sixth check word in sequence, take out the 17th data and the 25th data from P2 in sequence, and record them as the 1st check word in turn The seventh check word and the eighth check word; Take the highest data from the fifth check word to the eighth check word to form the fifth check output word, the next highest data form the sixth check output word, the second lowest data form the seventh check output word, and the lowest data form the sixth check output word. Eight check output words; Place the fifth check output word in the address of the first data to the fourth data in row S+1 of the check matrix, and place the sixth check output word in the check matrix In the address of the 9th data to the 12th data in the S+1th row, the seventh check output word is placed in the address of the 5th data to the 8th data in the S+1th row of the parity check matrix In, the eighth check output word is placed in the address of the 13th data to the 16th data in the S+1 row of the check matrix; Output the data in the address of the system matrix and the address of the check matrix in columns to obtain the bit stream after rate matching/de-matching. 2. according to the method for Turbo encoding rate matching/removing rate matching in the described LTE system of claim 1, it is characterized in that, after the Nth column of each subsystem matrix is extracted in turn, calculate the system matrix corresponding to the column data according to the interleaving mode The address includes determining the interleaving index according to the interleaving mode, shifting the address of each data in the Nth column of each subsystem matrix in turn by the interleaving index to obtain the middle offset address of each data in the column, and then according to the interleaving mode and N overall offset Shift the middle offset address to obtain the system matrix address; After extracting the Nth column of each sub-parity check matrix in turn, calculating the check matrix address corresponding to the column data according to the interleaving mode includes determining the interleaving index according to the interleaving mode, and offsetting the Nth column of each sub-parity check matrix in turn by the interleaving index The address of each data in the column obtains the middle offset address of each data in the column, and then the check matrix address is obtained by offsetting the middle offset address according to the interleaving mode and N overall. 3. according to the method for Turbo encoding rate matching/resolving rate matching in the described LTE system of claim 2, it is characterized in that, the address of each data in the N column of each subsystem matrix is shifted successively by the interleaving index to obtain intermediate It is further included before the offset address to calculate the starting column position of the system matrix, and the starting position of the system matrix is equal to k ₀ ,

N _cb is the rate matching soft buffer size, and RV is the redundancy version parameter. 4. according to the method for Turbo coding rate matching/removing rate matching in the described LTE system of claim 3, it is characterized in that, when k ₀ is greater than 32, the starting column position of system matrix equals k ₀ ',

5. according to the method for Turbo coding rate matching/removing rate matching in the described LTE system of claim 2, it is characterized in that, described intermediate offset address obtains system matrix address according to interleaving pattern and N overall offset and comprises, according to interleaving The mode and N determine the overall offset, and then offset the intermediate offset address as a whole according to the overall offset to obtain the system matrix address; Obtaining the parity check matrix address by offsetting the intermediate offset address according to the interleaving mode and N as a whole includes determining the overall offset according to the interleaving mode and N, and then offsetting the intermediate offset address as a whole according to the overall offset to obtain check matrix address. 6. according to the method for Turbo coding rate matching/de-rate matching in the described LTE system of claim 5, it is characterized in that, described according to interleaving mode and N determine overall offset comprises, determine padding bit by interleaving mode, when 32 minus After the padding bits are removed, the sum of the Nth data of P1 is less than or equal to 32, and the overall offset H is equal to the sum of 32 minus the padding bits and the Nth data of P1. 7. according to the method for Turbo encoding rate matching/de-rate matching in the described LTE system of claim 5, it is characterized in that, described according to interleaving mode and N determine overall offset comprises, determine padding bit by interleaving mode, when 32 minus After the padding bits are removed, the sum of the Nth data of P1 and P1 is greater than 32, and the overall offset H is equal to the difference between the Nth data of P1 and the padding bits. 8. according to the method for Turbo coding rate matching/removal rate matching in the described LTE system of claim 1, it is characterized in that, when there is remaining data after S cycle, get one remaining data at every turn and be placed in the address of described remaining data middle. 9. according to the method for Turbo coding rate matching/removing rate matching in the described LTE system of claim 1, it is characterized in that, when N equals 8 further comprise, according to interleaving pattern fill the extra bit of system data, fill check data according to interleaving pattern extra bits.

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