CN102468238A - Semiconductor element with metal grid and manufacturing method thereof - Google Patents

Abstract

The present application discloses a semiconductor element with a metal gate and a method for manufacturing the same. The semiconductor element with a metal gate includes providing a substrate, on which at least one semiconductor element and a contact hole etching stop layer and a dielectric layer covering the semiconductor element are formed, and the semiconductor element includes at least one dummy gate. A dummy gate removal step is performed to form at least one opening in the semiconductor element. The dummy gate removal step simultaneously removes a portion of the contact hole etching stop layer so that the top of the contact hole etching stop layer is lower than the semiconductor element and the dielectric layer to form a plurality of grooves. Thereafter, a groove removal step is performed to form a roughly flat dielectric layer surface on the substrate.

Description

Semiconductor element with metal gate and manufacturing method thereof

technical field

The invention relates to a semiconductor element with a metal gate and a manufacturing method thereof, in particular to a semiconductor element with a metal gate that implements a gate last process and a manufacturing method thereof.

Background technique

As the size of CMOS devices continues to shrink, the traditional method of reducing the thickness of the gate dielectric layer, such as reducing the thickness of the silicon dioxide layer, to achieve the purpose of optimization, is facing problems due to the tunneling effect of electrons. ) and lead to physical limitations of excessive leakage current. In order to effectively extend the generation evolution of logic components, high dielectric constant (high-K) materials can effectively reduce the physical limit thickness, and under the same equivalent oxide thickness (equivalent oxide thickness, hereinafter referred to as EOT), effectively reduce Leakage current and achieve equivalent capacitance to control channel switching and other advantages, it is used to replace the traditional silicon dioxide layer or silicon oxynitride layer as the gate dielectric layer.

However, the traditional polysilicon gate suffers from boron penetration (boron penetration) effect, which leads to problems such as lower device performance; and the polysilicon gate also suffers from the unavoidable depletion effect, making the equivalent gate dielectric layer The increase in thickness and the decrease in gate capacitance value lead to the decline of device driving ability and other difficulties. Therefore, a new gate material has been developed and produced at present, which uses a double work function metal to replace the traditional polysilicon gate, and is used as a control electrode matching a high-K gate dielectric layer.

The combination of dual-function metal gates with NMOS elements and PMOS elements makes the integration technology and process control of related elements more complicated, and the thickness and composition control requirements of each material are also more stringent. The fabrication methods of dual work function metal gates can be broadly divided into two categories: gate first process and gate last process. /Drain ultra-shallow junction activation tempering and the formation of metal silicide and other high thermal budget processes, so the selection and adjustment of materials face more challenges. In order to avoid the above-mentioned high thermal budget environment and obtain a wider selection of materials, the industry proposes a method of replacing the gate-front process with a gate-later process.

In the known gate-last process, a dummy gate or a replacement gate is formed first, and after the fabrication of a general MOS transistor is completed, the dummy/replacement gate is removed to form The gate trench is filled with different metals according to electrical requirements. It can be seen that although the gate-last process can avoid high thermal budget processes such as source/drain ultra-shallow junction activation tempering and the formation of metal silicides, and has a wider choice of materials, it still faces the integration of complex processes, etc. Reliability requirements.

Contents of the invention

Therefore, the object of the present invention is to provide a method for fabricating a semiconductor element with a metal gate implementing a gate-last process.

According to the claims provided by the present invention, a method for manufacturing a semiconductor element with a metal gate is provided. The method firstly provides a substrate on which at least one semiconductor element and a contact hole etch stop layer covering the semiconductor element are formed ( contact etch stop layer, hereinafter referred to as CESL) and a dielectric layer, and the semiconductor element includes at least one dummy gate. A dummy gate removal step is then performed to form at least one opening in the semiconductor device. The dummy gate removal step removes part of the CESL at the same time, so that the top of the CESL is lower than the semiconductor device and the dielectric layer to form a plurality of grooves. After forming the opening and the grooves, a groove removal step is performed to form a substantially flat dielectric layer surface on the substrate.

According to the claims provided by the present invention, there is also provided a method for manufacturing a semiconductor element with a metal gate. The method firstly provides a substrate on which at least a first transistor, a second transistor, and a substrate covering the first transistor are formed. with the CESL and dielectric layer of the second transistor. Next, a first dummy gate removal step is performed to form a first opening in the first transistor. The first dummy gate removing step removes part of the CESL at the same time, so that the top of the CESL is lower than the first transistor and the dielectric layer, thereby forming a plurality of first grooves. After forming the first opening and the first grooves, a first etching process is performed to remove part of the dielectric layer so that the surface of the dielectric layer is coplanar with the bottom of the first grooves, and then the first opening is formed The first metal layer is formed inside. Next, a second dummy gate removal step is performed to form a second opening in the second transistor, and then a second metal layer is formed in the second opening.

According to the claims provided by the present invention, there is also provided a method for manufacturing a semiconductor element with a metal gate. The method firstly provides a substrate on which at least a first transistor, a second transistor, and a substrate covering the first transistor are formed. with the CESL and dielectric layer of the second transistor. Subsequently, a first dummy gate removal step is performed to form a first opening in the first transistor, and a part of the CESL is simultaneously removed during the first dummy gate removal step. After forming the first opening, a first metal layer is formed in the first opening. Next, a second dummy gate removal step is performed to form a second opening in the second transistor, and a part of the CESL is simultaneously removed during the second dummy gate removal step. After forming the second opening, a second metal layer is formed in the second opening, and then a filling metal layer is formed on the base, and the filling metal layer at least fills up the second opening. After the filling metal layer is formed, a metal chemical mechanical polishing step is sequentially performed to remove part of the filling metal layer, and a non-selective metal chemical mechanical polishing step is performed to make the CESL, the dielectric layer and the filling metal layer share flat.

According to the claims provided by the present invention, there is also provided a semiconductor element having a metal gate, the semiconductor element comprising a base, a metal gate formed on the base, a spacer formed on a sidewall of the metal gate, The CESL and the dielectric layer covering the spacer, the top of the CESL is lower than the top of the spacer and the dielectric layer to form at least one groove. The semiconductor device also includes at least one metal layer filling the groove.

According to the method for manufacturing a semiconductor element with a metal gate provided by the present invention, the grooves formed in the CESL can be removed through a groove removal step, such as an etching process before forming a metal layer or after forming a metal layer. The two-stage planarization process and the like are removed, so problems such as the metal layer formed in the groove affecting the electrical performance of the semiconductor device in subsequent processes can be avoided.

Description of drawings

1 to 4 are schematic diagrams of a first preferred embodiment of a method for manufacturing a semiconductor element with a metal gate provided by the present invention;

5 to 7 are schematic diagrams of a second preferred embodiment of the method for manufacturing a semiconductor element with a metal gate provided by the present invention;

8 to 12 are schematic diagrams of a third preferred embodiment of the method for manufacturing a semiconductor element with a metal gate provided by the present invention;

Fig. 13 is a schematic diagram of a variant of the third preferred embodiment;

14 to 17 are schematic diagrams of a fourth preferred embodiment of the method for manufacturing a semiconductor element with a metal gate provided by the present invention; and

Fig. 18 is a schematic diagram of a variation of the fourth preferred embodiment.

Explanation of reference signs

100, 200, 300, 400 Base

102, 202, 302, 402 shallow trench isolation

104, 204, 304, 404 Gate dielectric layer

306, 406 dummy gate

110, 210, 310, 410 The first active area

112, 212, 312, 412 Second active area

120, 220, 320, 420 Transistors of the first conductivity type

122, 222, 322, 422 Second conductivity type transistor

130, 230, 330, 430 The first lightly doped drain

132, 232, 332, 432 Second lightly doped drain

134, 234, 334, 434 Space Wall

136, 336a, 336b Protruding portion of spacer wall

338a, 338b, 438a, 438b Patterned Hardmask

140, 240, 340, 440 First source/drain

142, 242, 342, 442 Second source/drain

144, 244, 344, 444 Metal silicides

150, 250, 350, 450 Contact hole etch stop layer

152, 252, 352, 452 Interlayer dielectric layer

154, 254, 354a, 354b, 454a, 454b groove

156, 356a, 356b, 456a, 456b Dummy gate removal procedure

158, 358a, 358b Diluted hydrogen fluoride etching process

258a, 458a Metal chemical mechanical polishing process

258b, 458b Non-selective chemical mechanical polishing process

160, 260, 360, 460 First opening

162, 262, 362, 462 Second opening

170, 270, 370, 470 The first metal layer

172, 272, 372, 472 Second metal layer

174, 274, 374, 474 Filled metal layer

180, 280, 380, 480 The first metal grid

182, 282, 382, 482 Second metal grid

Detailed ways

Please refer to FIG. 1 to FIG. 4 . FIG. 1 to FIG. 4 are schematic diagrams of a first preferred embodiment of a method for manufacturing a semiconductor device with a metal gate provided by the present invention. As shown in FIG. 1 , firstly, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, etc., and a first active region 110 and a second active region 110 are defined on the surface of the substrate 100. region 112 , and a plurality of shallow trench isolation (STI) 102 for electrically isolating the first active region 110 and the second active region 112 is formed in the substrate 100 . Next, the first conductive type transistor 120 and the second conductive type transistor 122 are respectively formed on the substrate 100 in the first active region 110 and the second active region 112 . In this preferred embodiment, the first conductive type transistor 120 is a P-type transistor; and the second conductive type transistor 122 is an N-type transistor, but those skilled in the art should know that the reverse is also possible. It can be seen that the semiconductor device provided in this preferred embodiment is a complementary metal-oxide semiconductor (CMOS) transistor device.

As shown in FIG. 1 , the first conductive type transistor 120 and the second conductive type transistor 122 each include a gate dielectric layer 104, a dummy gate (not shown) such as a polysilicon layer, and a patterned hard mask (not shown in the figure). Show). In this preferred embodiment, the gate dielectric layer 104 may be a conventional silicon dioxide layer, or may be a high-k (high-K) gate dielectric layer, and the high-K gate dielectric layer Selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON) and metal oxides, wherein the metal oxides include hafnium oxide (HfO), hafnium silicon oxide (hafnium silicon oxide, HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (aluminum oxide, AlO), lanthanum oxide (lanthanum oxide, LaO), lanthanum aluminate (lanthanum aluminum oxide, LaAlO), tantalum oxide (tantalum oxide, TaO), zirconium oxide (zirconium oxide, ZrO), zirconium silicon oxide (ZrSiO), or hafnium zirconium oxide (HfZrO), etc.

Please continue with Figure 1. The first conductive type transistor 120 and the second conductive type transistor 122 respectively include a first lightly doped drain (light doped drain, hereinafter referred to as LDD) 130 and a second LDD 132, a spacer 134, and a first source/drain 140 and a second source/drain 142 . The spacer 134 can be a single-layer structure including silicon oxide (SiO) or high temperature oxide (high temperature oxide, HTO) and other dielectric materials or silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide, ONO) Composite film structure. In addition, in this preferred embodiment, the first source/drain 140 and the second source/drain 142 may also be fabricated by a selective epitaxial growth (hereinafter referred to as SEG) method. For example, when the first conductivity type transistor 120 is a P-type transistor and the second conductivity type transistor 122 is an N-type transistor, an epitaxial layer containing silicon germanium (SiGe) and an epitaxial layer containing silicon carbide (SiC) can be used. The first source/drain 140 and the second source/drain 142 are respectively formed in each layer, so as to further improve the electrical performance by using the stress effect between the epitaxial layer and the channel silicon. In addition, the surfaces of the first source/drain 140 and the second source/drain 142 respectively include metal silicide 144 . After the first conductive type transistor 120 and the second conductive type transistor 122 are formed, a contact etch stop layer (CESL) 150 and a contact hole etch stop layer (CESL) 150 covering the first conductive type transistor 120 and the second conductive type transistor 122 are sequentially formed on the substrate 100 An inter-layer dielectric (inter-layer dielectric, hereinafter referred to as ILD) layer 152 .

Please continue with Figure 1. Next, a known planarization process, such as a CMP process, can be used to planarize the ILD layer 152 and the CESL 150 until the dummy gates are exposed. After the planarization process, the dummy gates of the first conductivity type transistor 120 and the second conductivity type transistor 122 are simultaneously removed by using the dummy gate removal step 156, and the dummy gates of the first conductivity type transistor 120 and the second conductivity type transistor 120 are removed simultaneously. A first opening 160 and a second opening 162 are respectively formed in the type transistor 122 , and the gate dielectric layer 104 is exposed at the bottom of the first opening 160 and the second opening 162 . It is also worth noting that in the dummy gate removal step 156, part of the CESL 150 is removed at the same time when the dummy gate is removed, so that the top of the CESL 150 is lower than the first conductivity type transistor 120 and the second conductivity type transistor 122. The spacers 134 and the ILD layer 152 are used to form a plurality of recesses 154 . The recesses 154 have a depth ranging from 50˜150 angstrom.

See Figure 2. Next, a groove removal step is performed, preferably a dilute hydrogen fluoride (dilute HF, DHF) etching process 158, such as a wet etching or dry etching process including DHF. The groove removal step 158 is used to remove a portion of the ILD layer 152 so that the ILD layer 152 is coplanar with the CESL 150 and the bottom of the groove 154 . Thus, after the groove removal step 158 , the grooves 154 are removed as shown in FIG. 2 , and a substantially planar surface of the ILD layer 152 is formed, and the spacer protrusions 136 protrude from the surface of the ILD layer 152 .

See Figure 3. After the groove removal step 158, a barrier layer (barrier layer) (not shown) is formed in the first opening 160 and the second opening 162 to prevent the high-K gate dielectric layer 104 from The metal layer formed produces a reaction or diffusion effect. After forming the barrier layer, a first metal layer 170 and a second metal layer 172 are respectively formed in the first opening 160 and the second opening 162 . The first metal layer 170 can be a metal that meets the work function requirements of a P-type transistor, such as titanium nitride (titanium nitride, TiN) or tantalum carbide (tantalum carbide, TaC); The metal required for the work function required by the N-type transistor is, for example, selected from titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl) or hafnium aluminide (HfAl) group. After forming the first metal layer 170 and the second metal layer 172, a filling metal layer 174 filling the first opening 160 and the second opening 162 is formed on the substrate 100. The filling metal layer 174 has excellent hole filling ability. Metals, such as aluminum, tungsten, copper and other metals, and preferably aluminum, but not limited thereto.

It is worth noting that the first metal layer 170 and the second metal layer 172 can be a single-layer structure or a composite layer structure, and there are various ways of forming them; there are also various combinations of their forming sequences. For example, after the first metal layer 170 is formed in the first opening 160 and the second opening 162 , the first metal layer 170 in the second active region 112 can be removed first, and then the second metal layer 170 can be formed on the substrate 100 . The metal layer 172 , and then the second metal layer 172 in the first active region 110 is removed. Alternatively, after the first metal layer 170 is formed in the first opening 160 and the second opening 162, the second metal layer 172 is formed in the second opening 162, and then the second metal in the first active region 110 is removed. Layer 172. In addition, after removing the second metal layer 172 in the first active region 110, anneal can be used to adjust (tuning) the metal combination in the second opening 162, so that the final metal composite layer in the second opening 162 The work function requirement required by the N-type transistor is further satisfied. Alternatively, the second metal layer 172 can be formed on the substrate 100, and then ion doping is used to convert the second metal layer 172 in the first active region 110 to meet the required power of the P-type transistor. The first metal layer 170 required by the function. The above-mentioned methods for forming the first metal layer 170 and the second metal layer 172 are only examples, and those skilled in the art should know that these methods can be implemented according to product and process requirements, and are not limited thereto, so details are not repeated here. In addition, this preferred embodiment can also integrate the high-K last process, that is, after the groove removal step 158 is performed, a high-K gate dielectric layer (not shown) is formed immediately, and then filled in each the desired gate metal layer.

See Figure 4. Next, a planarization process, such as a chemical-mechanical polishing (CMP) process, is performed to remove the redundant filling metal layer 174 , the first metal layer 170 and the second metal layer 172 . It should be noted that since the CMP process is more sensitive to protrusions on the plane, when the above metal layer is removed by the CMP process, the spacer protruding portion 136 protruding from the surface of the ILD layer 152 will also be removed. remove. Therefore, after the CMP process, the first metal gate 180 of the first conductivity type transistor 120 and the second metal gate 182 of the second conductivity type transistor 122 can be obtained. As shown in FIG. 4 , tops of the first metal gate 180 and the second metal gate 182 are coplanar with the ILD layer 152 and the CESL 150 .

According to the first preferred embodiment of the present invention, after removing the dummy gates of the transistors of the first conductivity type 120 and the transistors of the second conductivity type 122 at the same time and forming the groove 154, a portion is also removed by a DHF etching process 158 ILD layer 152 , making ILD layer 152 coplanar with the bottom of recess 154 . In other words, the present preferred embodiment utilizes the DHF etching process 158 to eliminate the existence of the groove 154 and form the spacer protrusion 136 on the ILD layer 152 . Therefore, when the fabrication of the metal layers 170/172/174 is completed and the surface of the substrate 100 is planarized by the CMP process, the gap can be successfully removed at one time by utilizing the fact that the CMP process is sensitive to the protruding parts on the substrate 100 The wall protruding portion 136 makes no residual metal exist on the substrate 100 except for the first metal gate 180 and the second metal gate 182 .

Next, please refer to FIGS. 5 to 7 , which are schematic diagrams of a second preferred embodiment of a method for fabricating a semiconductor device with a metal gate provided by the present invention. First of all, it should be noted that the material selection of each element in this second preferred embodiment is the same as that of the first preferred embodiment, so those skilled in the art can learn from the first preferred embodiment, so these materials are no longer It will be described in detail in the second preferred embodiment. As shown in Figure 5, this preferred embodiment firstly provides a substrate 200, the surface of the substrate 200 defines a first active region 210 and a second active region 212, and a plurality of active regions 210 and 212 are formed in the substrate 200 to electrically isolate the first active The STI 202 of the source region 210 and the second active region 212. Next, the first conductive type transistor 220 and the second conductive type transistor 222 are respectively formed on the substrate 200 in the first active region 210 and the second active region 212 . In this preferred embodiment, the first conductive type transistor 220 is a P-type transistor; and the second conductive type transistor 222 is an N-type transistor, but those skilled in the art should know that the reverse is also possible. It can be seen that the semiconductor device provided by this preferred embodiment is also a CMOS device.

As shown in FIG. 5 , the first conductive type transistor 220 and the second conductive type transistor 222 each include a gate dielectric layer 204, a dummy gate (not shown) such as a polysilicon layer, and a patterned hard mask (not shown in the figure). Show). In addition, the first conductive type transistor 220 and the second conductive type transistor 222 respectively include a first LDD 230 and a second LDD 232, a spacer 234, and a first source/drain 240 and a second source/drain 242. As mentioned above, in this preferred embodiment, the first source/drain 240 and the second source/drain 242 can also be fabricated by using the SEG method. In addition, the surfaces of the first source/drain 240 and the second source/drain 242 respectively include metal silicide 244 . After forming the first conductive type transistor 220 and the second conductive type transistor 222, the CESL 250 and the ILD layer 252 covering the first conductive type transistor 220 and the second conductive type transistor 222 are sequentially formed on the substrate 200.

Please continue with Figure 5. Next, a known planarization process, such as a CMP process, can be used to planarize the ILD layer 252 and the CESL 250 until the dummy gates are exposed. After the planarization process, the dummy gates of the first conductivity type transistor 220 and the second conductivity type transistor 222 are simultaneously removed by using the dummy gate removal step, and the dummy gates of the first conductivity type transistor 220 and the second conductivity type transistor 220 are removed simultaneously. A first opening 260 and a second opening 262 are respectively formed in the transistor 222 , and the gate dielectric layer 204 is exposed at the bottom of the first opening 260 and the second opening 262 . It is also worth noting that in the step of removing the dummy gate, part of the CESL 250 is removed at the same time, so that the top of the CESL 250 is lower than that of the first conductivity type transistor 220 and the second conductivity type transistor 222. The spacers 234 and the ILD layer 252 form a plurality of grooves 254 , and the grooves 254 have a depth ranging from 50˜150 angstroms.

Please still refer to Figure 5. Next, a barrier layer (not shown) is formed in the first opening 260 and the second opening 262 respectively, and a first metal layer 270 is formed in the first opening 260 and the second opening 262 respectively after forming the barrier layer. and the second metal layer 272 . The first metal layer 270 can be a metal meeting the work function requirements of the P-type transistor; and the second metal layer 272 can be a metal meeting the work function requirements of the N-type transistor. After forming the first metal layer 270 and the second metal layer 272 , a filling metal layer 274 filling the first opening 260 and the second opening 262 is formed on the substrate 200 . It should be noted that the first metal layer 270 , the second metal layer 272 and the filling metal layer 274 are filled into the groove 254 as shown in FIG. 5 . As mentioned above, the first metal layer 270 and the second metal layer 272 can be a single-layer structure or a composite layer structure, and there are many ways to form them; The manufacturing method of the second metal layer 272 and the process of optionally integrating the high-Klast can also refer to the description of the first preferred embodiment, so details are not repeated here.

See Figure 6. After the first metal layer 270 , the second metal layer 272 and the filling metal layer 274 are completed, the groove removal step is performed. In this preferred embodiment, the step of removing the groove may include two parts. First, a metal-chemical mechanical polish (metal-CMP) step 258a is performed to remove the redundant filling metal layer 274, the second A metal layer 270 and a second metal layer 272 . It should be noted that the metal CMP step 258a stops on the surface of the ILD layer 252 to obtain the first metal gate 280 of the first conductivity type transistor 220 and the second metal gate 282 of the second conductivity type transistor 222, and the first The metal gate 280 and the second metal gate 282 are coplanar with the ILD layer 252 .

So far, this preferred embodiment also provides a semiconductor device with a metal gate, which includes a substrate 200, a metal gate 280/282 formed on the substrate 200, and a gap formed on the sidewall of the metal gate 280/282. Wall 234, and CESL 250 and ILD layer 252 covering spacer 234. It should be noted that the top of the CESL 250 is lower than the spacer 234 and the ILD layer 252 to form a groove 254, and the groove 254 is filled with the metal layer 270, 272, or 274. As mentioned above, the metal gate 280/282 includes the gate dielectric layer 204 disposed on the substrate 200, the work function (work function) metal layer 270 or 272 disposed on the gate dielectric layer 204, and disposed on the Fill metal layer 274 on work function gold layer 270 or 272 . As mentioned above, the first metal layer 272 of the first metal gate 280 includes the metal required for the work function of the P-type transistor, so it serves as the work function metal layer of the first metal gate 280; and the second metal gate 282 The second metal layer 272 includes the metal required for the work function of the N-type transistor, so it serves as the work function metal layer of the second metal gate 282 . The groove 254 has a depth ranging from 50-150 angstroms.

See Figure 7. Next, the second part of the groove removal step is performed, ie, a non-selectivity chemical mechanical polishing step 258b is performed. Unlike the metal CMP step 258a, the non-selective CMP step 258b is a non-selective planarization method, so the non-selective CMP step 258b is used to simultaneously remove the ILD layer 252 and the metal layers 270, 272 in the recess 254 , 274, so the groove 254 and the metal therein can be completely removed. As shown in FIG. 7, after the non-selective CMP step 258b, the ILD layer 252, the CESL 250, the spacer 234, the first metal layer 270, the second metal layer 272, and the fill metal layer 274 are all coplanar and aligned with the original concave The bottoms of the grooves 254 are coplanar.

According to the second preferred embodiment of the present invention, after forming the first metal layer 270 , the second metal layer 272 and the filling metal layer 274 , the groove 254 and the metal layer therein are removed by a groove removal step. First, the metal CMP step 258a is used to remove the redundant filling metal layer 274, the first metal layer 270 and the second metal layer 272; then the non-selective CMP step 258b is used to remove the ILD layer 252 and the metal layer 270 in the groove 254 , 272, 274. Through the two-step CMP process, the groove 254 and the metal layer inside can be successfully removed, so that there is no residual metal on the substrate 200 except for the first metal gate 280 and the second metal gate 282 .

Please refer to FIG. 8 to FIG. 12 . FIG. 8 to FIG. 12 are schematic diagrams of a third preferred embodiment of a method for manufacturing a semiconductor device with a metal gate provided by the present invention. First of all, it is worth noting that the material selection of each element in this third preferred embodiment is the same as that of the aforementioned preferred embodiments, so those skilled in the art can learn from the aforementioned preferred embodiments, so these materials are no longer listed in the first preferred embodiment. The three preferred embodiments will be described in detail. As shown in FIG. 8 , this preferred embodiment firstly provides a substrate 300 whose surface defines a first active region 310 and a second active region 312 , and a plurality of active regions 310 and 312 are formed in the substrate 300 to electrically isolate the first active regions. STI 302 of region 310 and second active region 312. Next, a first conductive type transistor 320 and a second conductive type transistor 322 are respectively formed on the substrate 300 in the first active region 310 and the second active region 312 . In this preferred embodiment, the first conductive type transistor 320 is a P-type transistor; and the second conductive type transistor 322 is an N-type transistor, but those skilled in the art should know that the reverse is also possible.

As shown in FIG. 8 , the first conductivity type transistor 320 and the second conductivity type transistor 322 each include a gate dielectric layer 304 , a dummy gate 306 such as a polysilicon layer, and a patterned hard mask (not shown). In addition, the first conductive type transistor 320 and the second conductive type transistor 322 respectively include a first LDD 330 and a second LDD 332, a spacer 334, and a first source/drain 340 and a second source/drain 342. As mentioned above, in this preferred embodiment, the first source/drain 340 and the second source/drain 342 can also be fabricated by using the SEG method. In addition, the surfaces of the first source/drain 340 and the second source/drain 342 respectively include metal silicide 344 . After the first conductive type transistor 320 and the second conductive type transistor 322 are formed, the CESL 350 and the ILD layer 352 covering the first conductive type transistor 320 and the second conductive type transistor 322 are sequentially formed on the substrate 300 .

Please continue with Figure 8. Next, a known planarization process, such as a CMP process, can be used to planarize the ILD layer 352 and the CESL 350 until the dummy gates 306 of the first conductive type transistor 320 and the second conductive type transistor 322 are exposed. A patterned hard mask 338 a is then formed in the second active region 312 to protect the dummy gate 306 in the second active region 312 . After the patterned hard mask 338a is formed, a first dummy gate removal step 356a is performed to remove the dummy gate 306 of the transistor of the first conductivity type 320 , and a first opening 360 is formed in the transistor of the first conductivity type 320 , and the gate dielectric layer 304 is exposed at the bottom of the first opening 360 . It is also worth noting that in the first dummy gate removal step 356a, when removing the dummy gate 306, part of the CESL 350 is removed at the same time, so that the top of the CESL 350 is lower than the spacer 334 of the transistor 320 of the first conductivity type. A plurality of grooves 354 a are formed with the ILD layer 352 , and the grooves 354 a have a depth ranging from 50˜150 angstroms.

See Figure 9. Next, a first etching process is performed, preferably a DHF etching process 358a, such as a wet etching process or a dry etching process including DHF. The first etching process is used to remove part of the ILD layer 352, so that the ILD layer 352 is coplanar with the bottom of the groove 354a. Therefore, after the first etching process, the groove 354a is removed, and a roughly flat surface of the ILD layer 352 is formed as shown in FIG.

See Figure 10. After removing the first groove 354 and forming the spacer protrusion 336a, the patterned hard mask 338a is removed, and then a barrier layer (not shown) and a first metal layer are sequentially formed in the first opening 360 370 and a fill metal layer 374 filling the first opening 360 . As mentioned above, the first metal layer 370 can be a metal that satisfies the work function requirement of the P-type transistor; the filling metal layer 374 is a metal material with excellent hole-filling ability. Similarly, a high-K gate dielectric layer (not shown) may optionally be formed first after the first etching process. Then, a first planarization process, such as a CMP process, is performed to remove part of the filling metal layer 374 and the first metal layer 370 to complete the fabrication of the first metal gate 380 of the first conductivity type transistor 320 .

Please continue with Figure 10. After the fabrication of the first metal gate 380 is completed, a patterned hard mask 338 b is formed in the first active region 310 to protect the first metal gate 380 in the first active region 312 . Subsequently, the dummy gate 306 of the transistor of the second conductivity type 322 is removed by the second dummy gate removal step 356b, and a second opening 362 is formed in the transistor of the second conductivity type 322, and the gate dielectric layer 304 It is also exposed at the bottom of the second opening 362 . Similarly, when removing the dummy gate 306 in the second dummy gate removal step 356b, part of the CESL 350 is removed at the same time, so that the top of the CESL 350 is lower than the spacer 334 and the ILD layer of the second conductivity type transistor 322 352, and form a plurality of grooves 354b, and the depth of the grooves 354b is the same as that of the grooves 354a.

See Figure 11. Next, a second etching process, preferably a DHF etching process 358b, such as wet etching or dry etching including DHF, is performed to remove a portion of the ILD layer 352 so that the ILD layer 352 is coplanar with the bottom of the groove 354b. Therefore, after the second etching process, the groove 354b is removed, and a roughly flat surface of the ILD layer 352 is formed as shown in FIG.

See Figure 12. After removing the groove 354b and forming the spacer protrusion 336b, the patterned hard mask 338b is removed, and then a barrier layer (not shown), a second metal layer 372 and a second metal layer 372 are sequentially formed in the second opening 362. The filling metal layer 374 that fills the second opening 362 , wherein the second metal layer 372 can be a metal satisfying the work function requirement of the N-type transistor. In addition, a high-K gate dielectric layer (not shown) may optionally be formed first after the second etching process. After forming the second metal layer 372 and the filling metal layer 374, a second planarization process, such as a CMP process, is performed to remove part of the filling metal layer 374 and the second metal layer 372 to complete the second conductivity type transistor 322. Fabrication of the second metal gate 382 . It should be noted that since the CMP process is more sensitive to protrusions on the substrate, when the above metal layer is removed by the CMP process, the spacer protrusions 336a/336b protruding from the surface of the ILD layer 352 will be combined with The remaining metal layer on the ILD layer 352 is removed together, so that the first metal gate 380, the second metal gate 382, the ILD layer 352 and the CESL 350 are coplanar as shown in FIG. 12 .

In addition, in order to remove the metal and spacer protrusions 336a/336b more effectively, in the modification of this preferred embodiment, the CMP process is divided into two steps, and the metal chemical mechanical polishing step (not shown in the figure) is performed first. ) to remove the redundant filling metal layer 374 , the first metal layer 370 and the second metal layer 372 . Afterwards, a non-selective CMP step (not shown) is used to remove the ILD layer 352 and the metal layers 370 , 372 , 374 in the grooves 354 a / 354 b . Through this two-step CMP process, the grooves 354a/354b and the metal layer therein can be successfully removed.

Also see Figure 13. Fig. 13 is a schematic diagram of a variation of the third preferred embodiment. The main difference between this variation and the third preferred embodiment is that the filling metal layer 374 filling the first opening 360 and the second opening 362 is formed simultaneously. For example, in this variation, after the first metal layer 370 is formed, a patterned hard mask (not shown) is formed in the first active region 310 to protect the first metal layer in the first active region 310 370. Then remove the dummy gate 306 of the transistor 322 of the second conductivity type. After the dummy gate 306 is removed, the patterned hard mask in the first active region 310 is removed, and then the second metal layer 372 is sequentially formed on the substrate 300 to fill the first opening 360 and the first opening 360 . Two openings 362 are filled with a metal layer 374 . After the fabrication of all the metal layers is completed, the redundant filling metal layer 374, the second metal layer 372 and the first metal layer 370 are removed through the CMP process at one time or through the aforementioned two-stage CMP process to form the 12 shows a roughly flat surface. In addition, as mentioned above, the CMP process is relatively sensitive to the protrusions on the substrate, so when the CMP process is performed to remove the above metal layer, the spacer protrusions 336a/336b protruding from the surface of the ILD layer 352 will be removed. and remove.

According to the third preferred embodiment provided by the present invention, after removing the dummy gates 306 of the transistors of the first conductivity type 320 and the transistors of the second conductivity type 322 and forming the grooves 354a/354b in the CESL 350, using The DHF etch process 358a/358b removes a corresponding portion of the ILD layer 352, making the ILD layer 352 coplanar with the bottom of the recess 354a/354b. In other words, the presence of the grooves 354a/354b are eliminated by two DHF etching processes 358a/358b, respectively, and the spacer protrusions 336a/336b are formed on the substrate 300, respectively. Therefore, when the fabrication of each metal layer is completed and the surface of the substrate 300 is planarized using the CMP process, the feature that the CMP process is sensitive to the protruding portion on the substrate 300 can be used to successfully remove the protruding portion 336a/336b of the spacer , so that there is no residual metal on the substrate 300 except for the first metal gate 380 and the second metal gate 382 .

Please refer to FIG. 14 to FIG. 17 . FIG. 14 to FIG. 17 are schematic diagrams of a fourth preferred embodiment of a method for manufacturing a semiconductor device with a metal gate provided by the present invention. As mentioned above, the material selection of each element in this fourth preferred embodiment is the same as that of the aforementioned preferred embodiment, so those skilled in the art can learn from the aforementioned preferred embodiment, so these materials are no longer included in the fourth preferred embodiment. The four preferred embodiments will be described in detail. As shown in Figure 14, this preferred embodiment firstly provides a substrate 400, the surface of which defines a first active region 410 and a second active region 412, and a plurality of active regions are formed in the substrate 400 to electrically isolate the first active regions. STI 402 of region 410 and second active region 412. Next, a first conductive type transistor 420 and a second conductive type transistor 422 are respectively formed on the substrate 400 in the first active region 410 and the second active region 412 . In this preferred embodiment, the first conductive type transistor 420 is a P-type transistor; and the second conductive type transistor 422 is an N-type transistor, but those skilled in the art should know that the reverse is also possible.

As shown in FIG. 14 , the first conductivity type transistor 420 and the second conductivity type transistor 422 each include a gate dielectric layer 404 , a dummy gate 406 such as a polysilicon layer, and a patterned hard mask (not shown). In addition, the first conductive type transistor 420 and the second conductive type transistor 422 respectively include a first LDD 430 and a second LDD 432, a spacer 434, and a first source/drain 440 and a second source/drain 442. As mentioned above, in this preferred embodiment, the first source/drain 440 and the second source/drain 442 can also be fabricated by using the SEG method. In addition, the surfaces of the first source/drain 440 and the second source/drain 442 respectively include metal silicide 444 . After forming the first conductive type transistor 420 and the second conductive type transistor 422, the CESL 450 and the ILD layer 452 covering the first conductive type transistor 420 and the second conductive type transistor 422 are sequentially formed on the substrate 400.

Please continue with Figure 14. Next, a known planarization process, such as a CMP process, can be used to planarize the ILD layer 452 and the CESL 450. A patterned hard mask 438 a is then formed in the second active region 412 to protect the dummy gate 406 in the second active region 412 . After the patterned hard mask 438a is formed, a first dummy gate removal step 456a is performed to remove the dummy gate 406 of the transistor of the first conductivity type 420 , and a first opening 460 is formed in the transistor of the first conductivity type 420 , and the gate dielectric layer 404 is exposed at the bottom of the first opening 460 . It is also worth noting that the first dummy gate removal step 456a removes part of the CESL 450 while removing the dummy gate 406, so that the top of the CESL 450 is lower than the spacer 434 of the first conductivity type transistor 420 A plurality of grooves 454 a are formed with the ILD layer 452 , and the grooves 454 a have a depth ranging from 50˜150 angstroms.

See Figure 15. After the patterned hard mask 438a is removed, a barrier layer (not shown), a first metal layer 470 and a filling metal layer 474 filling the first opening 460 are sequentially formed in the first opening 460 . As mentioned above, the first metal layer 470 can be a metal that satisfies the work function requirement of the P-type transistor; the filling metal layer 474 is a metal material with excellent hole-filling ability. In addition, a high-K gate dielectric layer (not shown) may optionally be formed first after removing the dummy gate 406 . Then, a first planarization process, preferably a metal CMP process, is performed to remove part of the filling metal layer 474 and the first metal layer 470 to complete the fabrication of the first metal gate 480 of the first conductivity type transistor 420 . It should be noted that the metal CMP step stops on the surface of the ILD layer 452 , so as shown in FIG. 15 , after the metal CMP process, part of the first metal layer 470 or the filling metal layer 474 still remains in the groove 454 a.

Please continue with Figure 15. After the fabrication of the first metal gate 480 is completed, a patterned hard mask 438 b is formed in the first active region 410 to protect the first metal gate 480 in the first active region 412 . Subsequently, the dummy gate 406 of the transistor 422 of the second conductivity type is removed by using the second dummy gate removal step 456b, and a second opening 462 is formed in the transistor 422 of the second conductivity type, and the gate dielectric layer 404 It is also exposed at the bottom of the second opening 462 . Similarly, when removing the dummy gate 406 in the second dummy gate removal step 456b, part of the CESL 450 is removed at the same time, so that the top of the CESL 450 is lower than the spacer 434 and the ILD layer of the second conductivity type transistor 422 452 to form a plurality of grooves 454b, and the depth of the grooves 454b is the same as that of the grooves 454a.

See Figure 16. Next, the patterned hard mask 438b is removed, and then a high-K gate dielectric layer (not shown) can be selectively formed in the second opening 462 first, and a barrier layer (not shown), a barrier layer (not shown), and a barrier layer (not shown) can be formed sequentially. The second metal layer 472 and the filling metal layer 474, the second metal layer 472 can be a metal that meets the work function requirement of the N-type transistor. After forming the second metal layer 472 and the filling metal layer 474 , a metal CMP process 458 a is performed to remove the redundant filling metal layer 474 and the second metal layer 472 . It should be noted that the metal CMP process 458 a stops on the surface of the ILD layer 452 to obtain the second metal gate 482 of the second conductivity type transistor 422 .

See Figure 17. A non-selective CMP process 458b is also performed next. Unlike the metal CMP process 458a, the non-selective CMP process 458b is a non-selective planarization method, so the non-selective CMP process 458b is used to remove the ILD layer 452 and the metal layer 470/ in the grooves 454a/454b. 472/474, so the groove 454a/454b and the metal in it can be completely removed. In other words, after the non-selective CMP process 458b, the surface of the substrate 400, especially the ILD layer 452, the CESL 450, the spacer 434, the first metal layer 470, the second metal layer 472, and the filling metal layer 474 are all coplanar, and Coplanar with the bottom of the recess 454a/454b.

Also see Figure 18. Fig. 18 is a schematic diagram of a variation of the fourth preferred embodiment. Similarly, the main difference between this variation and the fourth preferred embodiment is that the metal layer 474 filling the first opening 460 and the second opening 462 is formed simultaneously. For example, in this variation, after the first metal layer 470 is formed, a patterned hard mask (not shown) is formed in the first active region 410 to protect the first metal layer 470 in the first active region 410 , and then remove the dummy gate 406 of the transistor 422 of the second conductivity type. After the dummy gate 406 is removed, the patterned hard mask in the first active region 410 is removed, and then the second metal layer 472 is sequentially formed on the substrate 400 to fill the first opening 460 and the first opening 460 . Two openings 462 are filled with a metal layer 474 . After the fabrication of all the metal layers is completed, the metal CMP process 458a is first performed to remove the redundant third metal layer 474, the second metal layer 472 and the first metal layer 470 to form a roughly flat surface as shown in FIG. 16 . As mentioned above, after the metal CMP process 458a, the first metal layer 470 and the third metal layer 474 still remain in the groove 454a; while the second metal layer 472 and the third metal layer 474 remain in the groove 454b . Next, a non-selective CMP step 458b is performed to remove the ILD layer 452 and the metal layers 470/472/474 in the recesses 454a/454b, so that the recesses 454a/454b and the metals in the recesses 454a/454b can be completely removed. After non-selective CMP step 458b, ILD layer 452, CESL 450, spacer 434, first metal layer 470, second metal layer 472, and fill metal layer 474 are all coplanar and coplanar with the bottom of recess 454a/454b flat.

In addition, it should be noted that the fourth preferred embodiment and its variants are not limited to performing a DHF etching process after forming the first opening 460 and the groove 454a to remove part of the ILD layer 452, so that the ILD layer is consistent with the original The bottoms of the grooves 454a are coplanar. Similarly, it is not limited to performing the DHF etching process after forming the second opening 462 and the groove 454b to remove part of the ILD layer 452 so that the ILD layer is coplanar with the bottom of the original groove 454b. After the first metal layer 470 , the second metal layer 472 and the third metal layer 474 are fabricated, the above-mentioned metal CMP step 458 a and non-selective CMP step 458 b are performed in sequence.

According to the fourth preferred embodiment of the present invention, after forming the first opening 460 and the second opening 462 respectively, and forming the first metal layer 470, the second metal layer 472 and the filling metal layer 474 respectively, first use metal CMP Step 458a removes redundant filling metal layer 474, first metal layer 470 and second metal layer 472; then non-selective CMP step 458b removes ILD layer 452 and metal layers 470, 472, 474. Through the two-step CMP process, the groove 454 a / 454 b and the metal layer inside can be successfully removed, so that there is no residual metal on the substrate 400 except for the first metal gate 480 and the second metal gate 482 .

In summary, according to the method for manufacturing a semiconductor element with a metal gate provided by the present invention, the grooves formed in the CESL can be removed through a groove removal step, such as an etching process before forming a metal layer or in The two-stage planarization process after the formation of the metal layer is removed, so problems such as the metal layer formed in the groove affecting the electrical performance of the semiconductor device in subsequent processes can be avoided.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (30)

1. manufacture method with semiconductor element of metal gates includes:

Substrate is provided, be formed with in this substrate at least one semiconductor element with cover this semiconductor element contact hole etching stopping layer and dielectric layer, and this semiconductor element comprises a nominal grid at least;

Carry out nominal grid and remove step,, remove this contact hole etching stopping layer of part simultaneously, make the top of this contact hole etching stopping layer be lower than this semiconductor element and this dielectric layer and form a plurality of grooves in this semiconductor element, to form at least one opening; And

Carry out groove and remove step, in this substrate, to form smooth dielectric layer surface.

2. manufacture method as claimed in claim 1, wherein this groove removes step and comprises dilution hydrogen fluoride etch technology, in order to this dielectric layer of etching.

3. manufacture method as claimed in claim 2, wherein this groove removes the bottom copline on this dielectric layer surface and this groove after the step.

4. manufacture method as claimed in claim 2 also is contained in this substrate surface and forms at least one metal level and the step of carrying out flatening process, is carried out at this groove in regular turn and removes after the step.

5. manufacture method as claimed in claim 1 also is contained in the step that this substrate surface forms at least one metal level, is carried out at this groove and removes before the step.

6. manufacture method as claimed in claim 5, wherein this groove removes step and also comprises:

Carry out the chemical mechanical polishing of metals step; And

Carry out non-selective chemical-mechanical polishing step.

7. manufacture method as claimed in claim 6, wherein this groove removes this metal level after the step, this dielectric layer contacts hole etching stopping layer copline with this.

8. manufacture method as claimed in claim 1; Wherein this semiconductor element comprises the CMOS transistor unit; This CMOS transistor unit also comprises first conductive-type transistor and second conductive-type transistor, and this first conductive-type transistor and this second conductive-type transistor also comprise this nominal grid respectively.

9. manufacture method as claimed in claim 8, wherein this nominal grid removes this nominal grid that step removes this first conductive-type transistor and this second conductive-type transistor simultaneously.

10. manufacture method with semiconductor element of metal gates includes:

Substrate is provided, be formed with at least one the first transistor, transistor seconds in this substrate, cover this first transistor and this transistor seconds contact hole etching stopping layer and dielectric layer;

Carry out first nominal grid and remove step,, remove this contact hole etching stopping layer of part simultaneously, make the top of this contact hole etching stopping layer be lower than this first transistor and this dielectric layer and form a plurality of first grooves in this first transistor, to form first opening;

Carry out first etch process, remove this dielectric layer of part, make this dielectric layer surface and these first bottom portion of groove coplines;

In this first opening, form the first metal layer;

Carry out second nominal grid and remove step, in this transistor seconds, to form second opening; And

In this second opening, form second metal level.

11. manufacture method as claimed in claim 10, wherein this second nominal grid removes step and removes this contact hole etching stopping layer of part simultaneously, makes the top of this contact hole etching stopping layer be lower than this transistor seconds and this dielectric layer and forms a plurality of second grooves.

12. manufacture method as claimed in claim 11 also comprises second etch process, is carried out to form after this second opening, in order to remove this dielectric layer of part, makes this dielectric layer surface and these second bottom portion of groove coplines.

13. manufacture method as claimed in claim 10 also is contained in the step that forms the 3rd metal level in this substrate.

14. manufacture method as claimed in claim 13, wherein the 3rd metal level is formed at before this second nominal grid that removes this transistor seconds, and the 3rd metal level fills up this first opening.

15. manufacture method as claimed in claim 14 also comprises the step of carrying out flatening process, in order to remove the 3rd metal level and this first metal layer of part.

16. manufacture method as claimed in claim 13, wherein the 3rd metal level is formed at and forms after this second metal level, and the 3rd metal level fills up this first opening and this second opening.

17. manufacture method as claimed in claim 16; Also comprise the step of carrying out flatening process; Remove the 3rd metal level, this first metal layer and this second metal level of part, make this first metal layer, this second metal level, the 3rd metal level, this dielectric layer contact hole etching stopping layer copline with this.

18. manufacture method as claimed in claim 17, wherein this flatening process also comprises:

Carry out the chemical mechanical polishing of metals step; And

Carry out non-selective chemical-mechanical polishing step.

19. the manufacture method with semiconductor element of metal gates includes:

Substrate is provided, be formed with at least one the first transistor, transistor seconds in this substrate, cover this first transistor and this transistor seconds contact hole etching stopping layer and dielectric layer;

Carry out first nominal grid and remove step,, remove this contact hole etching stopping layer of part simultaneously in this first transistor, to form first opening;

In this first opening, form the first metal layer;

Carry out second nominal grid and remove step,, remove this contact hole etching stopping layer of part simultaneously in this transistor seconds, to form second opening;

In this second opening, form second metal level;

In this substrate, form and fill metal level, and this filling metal level fills up this second opening at least;

Carry out chemical mechanical polishing of metals technology, to remove this filling metal level of part; And

Carry out non-selective chemical mechanical polishing of metals technology, so that should contact hole etching stopping layer, this dielectric layer and this filling metal level copline.

20. manufacture method as claimed in claim 19, wherein this first nominal grid removes the top that step makes this contact hole etching stopping layer and is lower than this first transistor and this dielectric layer, and forms a plurality of first grooves.

21. manufacture method as claimed in claim 20 also comprises first etch process, be carried out at form this first opening and these first grooves after, in order to remove this dielectric layer of part, make this dielectric layer surface and these first bottom portion of groove coplines.

22. manufacture method as claimed in claim 19 also comprises the step that forms the 3rd metal level, be carried out to form after this first metal layer, and the 3rd metal level fills up this first opening.

23. manufacture method as claimed in claim 22 also comprises the step of carrying out flatening process, is carried out to form after the 3rd metal level, in order to remove part the 3rd metal level.

24. manufacture method as claimed in claim 19, wherein this second nominal grid removes top that step makes this contact hole etching stopping layer and is lower than this transistor seconds and this dielectric layer and forms a plurality of second grooves.

25. manufacture method as claimed in claim 24 also comprises second etch process, be carried out at form this second opening and these second grooves after, in order to remove this dielectric layer of part, make this dielectric layer surface and these second bottom portion of groove coplines.

26. manufacture method as claimed in claim 19, wherein this non-selective chemical mechanical polishing of metals technology is in order to remove this first groove and this second groove.

27. the semiconductor element with metal gates includes:

Substrate;

Metal gates is formed in this substrate;

Clearance wall is formed at the sidewall of this metal gates;

Contact hole etching stopping layer and dielectric layer cover this clearance wall, and the top of this contact hole etching stopping layer is lower than this clearance wall top and dielectric layer and is formed with at least one groove; And

At least one metal level fills up this groove.

28. semiconductor element as claimed in claim 27, wherein this metal gate structure also includes:

Gate dielectric is arranged in this substrate;

Workfunction layers is arranged on this gate dielectric; And

Fill metal level, be arranged on this work function golden number layer.

29. semiconductor element as claimed in claim 28, wherein this metal level one of comprises in this workfunction layers and this filling metal level at least.

30. semiconductor element as claimed in claim 27, wherein this groove has a degree of depth, and the scope of this degree of depth is between 50～150 dusts.

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