CN102467972A - Dynamic shift register unit and dynamic shift register - Google Patents

Abstract

The dynamic shift register unit and the dynamic shift register provided by the present invention can complete the shift of the input signal by using five MOS transistors and one capacitor, that is, the output signal at the output terminal lags behind the input signal by 1/4 cycle in phase. The shift register unit uses the storage function of the capacitor to output the effective level range of the pulse signal to the output terminal in the third 1/4 period of the pulse signal. Therefore, the shift register belongs to the self-feedback using capacitor Dynamic shift register. The dynamic shift register provided by the present invention can realize self-feedback by using a capacitor, thereby simplifying the circuit structure and saving layout area.

Description

A kind of dynamic shift register unit and dynamic shift register

technical field

The invention relates to the technical field of registers, in particular to a dynamic shift register unit and a dynamic shift register.

Background technique

When the display panel is working, the driving circuit of the display panel must have a scanning action to turn on each scanning line of the thin film transistor array one by one, so that the data signal of this line is transmitted to each display unit in the thin film transistor array. Such scanning action is accomplished by the shift register.

The shift register in the prior art will be introduced below with reference to the accompanying drawings. Referring to FIG. 1 , this figure is a circuit diagram of a shift register produced by Sony Corporation. The patent application number corresponding to the shift register is US7283117.

The shift register includes a shifter 11 and a keeper 12 .

Wherein, the shifter 11 includes a NAND circuit, and the NAND circuit receives the input pulse st. The input pulse st is used as the enable signal of the whole shift register, and the shift register starts to work when the input pulse st is low level in this circuit.

The keeper 12 includes a PMOS transistor Qp21 and an NMOS transistor Qn21, the PMOS transistor Qp21 and the NMOS transistor Qn21 are connected in series between the power supply VDD and the clock pulse ck, and the gates and drains of the PMOS transistor Qp21 and the NMOS transistor Qn21 are respectively connected to together.

The input terminal A of the keeper 12 is connected to the output terminal of the NAND circuit, and the output terminal out of the keeper 12 is used as the input terminal of the next register.

The working principle of FIG. 1 is described below in conjunction with FIG. 2 . Referring to FIG. 2 , the figure is a waveform diagram of each signal in FIG. 1 .

During the t11-t12 time period, the input pulse st is at a low potential, the PMOS transistor Qp11 is turned on, the NMOS transistor Qn11 is turned off, and the potential at point A of the input terminal of the keeper 12 is high; then the PMOS transistor Qp21 is turned off, the NMOS transistor Qn21 is turned on, and the clock The pulse ck is output to the output terminal out of the keeper 12 as an output signal. At this moment, the clock pulse ck is at a high potential, and the output terminal out of the keeper 12 is also at a high potential.

During the t12-t13 time period, the switching states of the PMOS transistor Qp11, NMOS transistor Qn11, PMOS transistor Qp21 and NMOS transistor Qn21 remain unchanged from the t11-t12 time period, but because the clock pulse ck changes from high potential to low potential, Therefore, the input terminal out of the keeper 12 is at low potential, and at the same time, the PMOS transistor Qp12 is turned on, and the input terminal A of the keeper 12 is at a high potential.

During the t13-t14 time period, the input pulse st potential changes from low to high. The PMOS transistor Qp11 is turned off, and the NMOS transistor Qn11 is turned on, because at the moment of transition, the PMOS transistor Qp12 is kept open due to the OUT signal of the input terminal 12 of the keeper, and then the input terminal A point of the keeper 12 is kept at a high potential, continuously The low signal of ck is output to out.

During the time period t14-t15, ck becomes a high potential, and the output terminal out of the keeper 12 also instantly becomes a high potential, and acts on the NMOS transistor Qn12 at the same time. Because the input pulse st is also at a high potential at this moment, it acts on the NMOS transistor Qn11, the input terminal A point of the keeper 12 becomes a low potential, the PMOS transistor Qp21 is turned on, VDD is output to the input terminal out of the keeper 12, and A self-feedback cycle is formed, and the output terminal out of the keeper 12 is output at a high potential, thereby completing a complete shifting process.

It can be seen from FIG. 2 that within one clock pulse cycle, the signal at the output terminal out of the keeper 12 is shifted backward by 1/4 cycle than the signal of the input pulse st, and the shift within one cycle is completed.

Sony's shift register is a static shift register. Its working principle is to use the self-feedback of the circuit itself to maintain the potential of the nodes in the circuit. However, the structure of this static shift register is relatively complicated, and the corresponding layout area Also larger.

Contents of the invention

The technical problem to be solved by the present invention is to provide a dynamic shift register unit and a dynamic shift register, the circuit structure is relatively simple, and the corresponding layout area is relatively small.

The present invention provides a dynamic shift register unit, comprising: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a first capacitor;

Both the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to the input signal;

Both the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to the first node;

The first capacitor is connected between the first node and ground;

Both the source of the first PMOS transistor and the source of the second PMOS transistor are connected to a power supply;

The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is grounded, and the gate of the second NMOS transistor is connected to the output terminal;

Both the gate of the second PMOS transistor and the gate of the third NMOS transistor are connected to the first node;

Both the drain of the second PMOS transistor and the drain of the third NMOS transistor are connected to the output terminal;

The source of the third NMOS transistor is connected to the pulse signal.

Preferably, the input signal is active low.

The embodiment of the present invention also provides a dynamic shift register, including a pulse signal generator, and also includes N said dynamic shift register units, where N is a positive integer; the input end of the first dynamic shift register unit is connected to the input signal , the output signal of the previous dynamic shift register unit is used as the input signal of the latter dynamic shift register unit; Pulse signal for bit register unit.

Preferably, four dynamic shift register units are included, which are respectively a first dynamic shift register unit, a second dynamic shift register unit, a third dynamic shift register unit and a fourth dynamic shift register unit;

The pulse signal generator is used to generate four pulse signals with a phase difference of 1/4 cycle, which are respectively the first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal; the first pulse signal, The second pulse signal, the third pulse signal and the fourth pulse signal are respectively used as the first dynamic shift register unit, the pulse signal of the second dynamic shift register unit, the third dynamic shift register unit and the fourth dynamic shift register unit ;

The input end of the first dynamic shift register unit is connected to the input signal, and the output end is connected to the input end of the second dynamic shift register unit;

The output end of the second dynamic shift register unit is connected to the input end of the third dynamic shift register unit;

The output end of the third dynamic shift register unit is connected to the input end of the fourth dynamic shift register unit;

The output terminal of the fourth dynamic shift register unit serves as the input signal of the next dynamic shift register.

The present invention also provides a dynamic shift register unit, including: a fifth PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a second capacitor;

Both the gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor are connected to the input signal;

The drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are both connected to the second node;

The source of the fifth PMOS transistor is connected to the power supply, the drain is connected to the source of the fourth PMOS transistor, and the gate is connected to the output terminal;

The source of the fourth NMOS transistor is grounded;

The second capacitor is connected between the power supply and the second node;

Both the gate of the fifth PMOS transistor and the gate of the fifth NMOS transistor are connected to the second node;

Both the drain of the fifth PMOS transistor and the drain of the fifth NMOS transistor are connected to the output terminal;

The source of the fifth NMOS transistor is grounded; the source of the fifth PMOS transistor is connected to the pulse signal.

Preferably, the input signal is active high.

The present invention also provides a dynamic shift register, including a pulse signal generator, and also includes N said dynamic shift register units, where N is a positive integer; the input end of the first dynamic shift register unit is connected to the input signal, and the preceding The output signal of a dynamic shift register unit is used as the input signal of the latter dynamic shift register unit; the pulse signal generator is used to generate pulse signals with a phase difference of 1/4 cycle successively, as each dynamic shift register in turn Unit's pulse signal.

The embodiment of the present invention also provides a dynamic shift register, including a pulse signal generator, including four dynamic shift register units, respectively the first dynamic shift register unit, the second dynamic shift register unit, the third dynamic shift register unit, and the second dynamic shift register unit. a dynamic shift register unit and a fourth dynamic shift register unit;

The pulse signal generator is used to generate four pulse signals with a phase difference of 1/4 cycle, which are respectively the first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal; the first pulse signal, The second pulse signal, the third pulse signal and the fourth pulse signal are respectively used as the first dynamic shift register unit, the pulse signal of the second dynamic shift register unit, the third dynamic shift register unit and the fourth dynamic shift register unit ;

The input end of the first dynamic shift register unit is connected to the input signal, and the output end is connected to the input end of the second dynamic shift register unit;

The output end of the second dynamic shift register unit is connected to the input end of the third dynamic shift register unit;

The output end of the third dynamic shift register unit is connected to the input end of the fourth dynamic shift register unit;

The output terminal of the fourth dynamic shift register unit serves as the input signal of the next dynamic shift register.

Compared with the prior art, the present invention has the following advantages:

The dynamic shift register unit and the dynamic shift register provided by the present invention can complete the shift of the input signal by using five MOS transistors and one capacitor, that is, the output signal at the output terminal lags behind the input signal by 1/4 cycle in phase. The shift register unit uses the storage function of the capacitor to output the effective level interval of the pulse signal to the output terminal in the third 1/4 period of the pulse signal, so the shift register is realized by using the storage function of the capacitor Self-feedback dynamic shift register. Different from the static shift register of Sony Corporation in the prior art, the transistor Qp12 is mainly used to realize self-feedback. Since the transistors used in Sony's static shift register realize self-feedback, there are many transistors, which makes the circuit structure complex. However, the dynamic shift register provided by the present invention can realize self-feedback by using a capacitor, thereby simplifying the circuit structure and saving layout area.

Description of drawings

Fig. 1 is a circuit diagram of a shift register in the prior art;

Fig. 2 is a waveform diagram corresponding to each signal in Fig. 1;

Fig. 3 is a circuit diagram of Embodiment 1 of a dynamic shift register unit provided by the present invention;

Fig. 4 is a waveform diagram corresponding to each signal in Fig. 3;

5 is a schematic diagram of a dynamic shift register provided by an embodiment of the present invention;

Fig. 6 is the waveform diagram corresponding to each signal in the implementation shown in Fig. 5 of the present invention;

Fig. 7 is a circuit diagram of another embodiment of the dynamic shift register unit provided by the present invention;

FIG. 8 is a waveform diagram corresponding to each signal in the embodiment shown in FIG. 7 of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

Refer to FIG. 3 , which is a circuit diagram of Embodiment 1 of the dynamic shift register unit provided by the present invention.

The dynamic shift register unit provided in this embodiment includes: a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a first capacitor C1;

Both the gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are connected to the input signal IN;

Both the drain of the first PMOS transistor MP1 and the drain of the first NMOS transistor MN1 are connected to the first node N1;

The first capacitor C1 is connected between the first node N1 and a ground signal VEE;

Both the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the power signal VDD;

The source of the first NMOS transistor MN1 is connected to the drain of the second NMOS transistor MN2, the source of the second NMOS transistor MN2 is connected to the ground signal VEE, and the gate of the second NMOS transistor MN2 is connected to the output terminal OUT;

Both the gate of the second PMOS transistor MP2 and the gate of the third NMOS transistor MN3 are connected to the first node N1;

Both the drain of the second PMOS transistor MP2 and the drain of the third NMOS transistor MN3 are connected to the output terminal OUT;

The source of the third NMOS transistor MN3 is connected to the pulse signal CK.

The working principle of the dynamic shift register unit provided by this embodiment will be described in detail below with reference to FIG. 3 and FIG. 4 . Refer to FIG. 4 , which is a waveform diagram corresponding to each signal in FIG. 3 .

Wherein, the pulse signal CK is a pulse signal input to the shift register unit. In the time period T1, the pulse signal CK is at a high level, and the input signal IN is at a low level. Therefore, the first PMOS transistor MP1 is turned on. A source of the PMOS transistor MP1, the power signal VDD is transmitted to the drain of the first PMOS transistor MP1, causing the node N1 to be at a high level, and the high level of the node N1 is stored in the first capacitor C1. And at the same time, the third NMOS transistor MN3 is turned on, and the pulse signal CK is transmitted to the drain through the source of the third NMOS transistor MN3, that is, the output terminal OUT is at a high level, thereby causing the second NMOS transistor MN2 to be turned on, and the second NMOS transistor MN2 to be turned on. The ground signal VEE of the source of the NMOS transistor MN2 is transmitted to its drain, and the drain of the second NMOS transistor MN2 is at a low level. All other transistors are off.

In the time period T2, the pulse signal CK changes from high level to low level, the input signal IN is still low level, the node N1 is still high level, and the third NMOS transistor MN3 is still open and will become The low level pulse signal CK is transmitted to the output terminal OUT, and the output terminal OUT becomes low level. At the same time, the second NMOS transistor MN2 is in the off state, and the drain potential of the second NMOS transistor MN2 is in an indeterminate state, but because the first NMOS transistor MN1 and the second NMOS transistor MN2 are both in the off state, it does not affect The output OUT signal has an effect.

In the time period T3, the pulse signal CK is still at low level, the input signal IN becomes high level, the first PMOS transistor MP1 is turned off, and the first NMOS transistor MN1 is turned on, because the high level of the node N1 is stored in In the first capacitor C1, MN3 is still turned on, and the input terminal OUT outputs a low-level signal of the pulse signal CK, thereby causing the second NMOS transistor MN2 to be disconnected.

In the time period T4, the pulse signal CK becomes high level, the input signal IN is still high level, the high level stored in the first capacitor C1 still acts on the third NMOS transistor MN3, and the third NMOS transistor MN3 is turned on , the output terminal OUT outputs the high level of the pulse signal CK, thereby causing the second NMOS transistor MN2 to be turned on. The high level of the input signal IN makes the first NMOS transistor MN1 continuously open, and the ground signal is transmitted to the node N1 through the source and drain of the second NMOS transistor MN2 and the source and drain of the first NMOS transistor MN1, and the node N1 is Pull it to a low potential, thereby turning on the second PMOS transistor MP2, the power signal VDD connected to the source of the second PMOS transistor MP2 is transmitted to the output terminal OUT, and the output terminal OUT is at a high level, thereby completing a self-feedback cycle process , the output terminal OUT remains at a high level.

During the time period T5, the pulse signal CK is still at a high level, and the input signal IN is at a high level, but because the self-feedback condition between them is still satisfied, the output terminal OUT keeps outputting a high level. To sum up, the shift register unit completes the shift within one cycle, and the output signal at the output terminal OUT is shifted backward by 1/4 cycle than the input signal IN. From Figure 4, we can clearly see the phase relationship between the various signals, and we can see that the signal at the output terminal OUT lags behind the signal at the input signal IN by 1/4 cycle.

The dynamic shift register unit provided by the present invention can complete the shift of the input signal IN by using five MOS transistors and one capacitor C1, that is, the output signal of the output terminal OUT lags behind the input signal IN by 1/4 period in phase, and the The cycle refers to the cycle of the pulse signal CK. The shift register unit utilizes the storage function of the capacitor C1 to output the effective level interval of the pulse signal CK to the output terminal OUT in the third 1/4 period of the pulse signal CK. The dynamic shift register provided by the present invention utilizes The storage function of the capacitor C1 can realize self-feedback, thereby simplifying the circuit structure and saving the layout area.

The embodiment of the present invention also provides a dynamic shift register. The above embodiments only provide a dynamic shift register unit. If a complete cycle of shifting needs to be completed, four dynamic shift registers described in the above embodiments are required. register unit. A complete dynamic shift register is introduced below in conjunction with the accompanying drawings.

Referring to FIG. 5 , this figure is a schematic diagram of a dynamic shift register provided by an embodiment of the present invention.

The dynamic shift register provided by this embodiment includes a pulse signal generator G, and also includes four dynamic shift register units shown in Figure 3, which are respectively the first dynamic shift register unit A and the second dynamic shift register unit B, the third dynamic shift register unit C and the fourth dynamic shift register unit D;

The pulse signal generator G is used to generate four pulse signals with a phase difference of 1/4 cycle in sequence, namely the first pulse signal CK1, the second pulse signal CK2, the third pulse signal CK3 and the fourth pulse signal CK4;

The first pulse signal CK1, the second pulse signal CK2, the third pulse signal CK3 and the fourth pulse signal CK4 respectively serve as the first dynamic shift register unit A, the second dynamic shift register unit B, and the third dynamic shift register unit C and the pulse signal of the fourth dynamic shift register unit D;

The input terminal of the first dynamic shift register unit A is connected to the input signal IN, and the output terminal OUT1 is connected to the input terminal of the second dynamic shift register unit;

The output terminal OUT2 of the second dynamic shift register unit B is connected to the input terminal of the third dynamic shift register unit C;

The output terminal OUT3 of the third dynamic shift register unit C is connected to the input terminal of the fourth dynamic shift register unit D;

The output terminal OUT4 of the fourth dynamic shift register unit D serves as the input signal of the next dynamic shift register.

Refer to FIG. 6 , which is a waveform diagram of each signal in FIG. 5 .

It can be seen from Figure 6 that OUT1 is shifted by 1/4 cycle than IN, OUT2 is shifted by 2/4 cycle than IN, OUT3 is shifted by 3/4 cycle than IN, and OUT4 is shifted by one cycle than IN.

It can be understood that a dynamic shift register can be formed by N dynamic shift register units shown in FIG. 3 , and N is a positive integer. For example, this dynamic shift register includes a pulse signal generator, and also includes N dynamic shift register units shown in Figure 3; the input end of the first dynamic shift register unit is connected to the input signal, and the first dynamic shift register unit The output signal of the unit is used as the input signal of the next dynamic shift register unit; the pulse signal generator is used to generate pulse signals with a phase difference of 1/4 cycle sequentially as the pulse signal of each dynamic shift register unit. It should be noted that what is shown in FIG. 5 is only a complete dynamic shift register, which can complete a shift within a complete cycle. If the number of lines to be scanned in the display panel is exactly a positive integer multiple of 4, an integer number of such dynamic shift registers is required. For example, if the number of lines to be scanned is exactly 200 lines, 50 such dynamic shift registers are required. bit register. If the number of lines to be scanned in the display panel is not a positive integer multiple of 4, for example, the number of lines to be scanned is 202 lines, then 50 such dynamic shift registers are needed, and 2 additional shift registers are required separately as shown in Figure 3 Dynamic shift register unit.

It should be noted that the dynamic shift register unit in the above embodiments uses a low level as an effective signal. The low level active here means that when the input signal IN is at a low level, the dynamic shift register shown in FIG. 3 is triggered. The bit register unit starts to work, so that within a period T of a pulse signal CK, the input signal IN is shifted backward by 1/4 period, and the output terminal OUT outputs the shifted signal. The following introduces another dynamic shift register unit provided by the embodiment of the present invention, which uses a high level as an effective signal. The high level active here means that when the input signal IN is at a high level, the trigger shown in Figure 7 The dynamic shift register unit starts to work, so that within one period T of the pulse signal CK, the input signal IN is shifted backward by 1/4 period, and the output terminal OUT outputs the shifted signal.

Referring to FIG. 7 , this figure is a circuit diagram of another embodiment of the dynamic shift register unit provided by the present invention.

The dynamic shift register unit provided in this embodiment includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, and a second capacitor C2;

Both the gate of the fourth PMOS transistor MP4 and the gate of the fourth NMOS transistor MN4 are connected to the input signal IN;

Both the drain of the fourth PMOS transistor MP4 and the drain of the fourth NMOS transistor MN4 are connected to the second node N2;

The source of the third PMOS transistor MP3 is connected to the power supply VDD, the drain is connected to the source of the fourth PMOS transistor MP4, and the gate is connected to the output terminal OUT;

The source of the fourth NMOS transistor MN4 is grounded VEE;

The second capacitor C2 is connected between the power supply VDD and the second node N2;

Both the gate of the fifth PMOS transistor MP5 and the gate of the fifth NMOS transistor MN5 are connected to the second node N2;

Both the drain of the fifth PMOS transistor MP5 and the drain of the fifth NMOS transistor MN5 are connected to the output terminal OUT;

The source of the fifth NMOS transistor MN5 is grounded VEE; the source of the fifth PMOS transistor MP5 is connected to the pulse signal CK.

It can be understood that the working principle of the dynamic shift register provided in this embodiment is similar to that in FIG. 3 , and will not be repeated here. From the waveform diagram shown in FIG. IN is shifted by 1/4 cycle.

It should be noted that the dynamic shift register unit shown in FIG. 7 can also be connected as a dynamic shift register in the form of FIG. 5 , and its working principle is similar, which will not be repeated here.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent of equivalent change Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (8)

1. a dynamic shift register cell is characterized in that, comprising: PMOS pipe, the 2nd PMOS pipe, NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and first electric capacity;

The grid of the grid of said PMOS pipe and NMOS pipe all connects input signal;

The drain electrode of said PMOS pipe all is connected first node with the drain electrode of NMOS pipe;

Said first electric capacity is connected between said first node and the ground;

The source electrode of the source electrode of said PMOS pipe and the 2nd PMOS pipe all connects power supply;

The source electrode of said NMOS pipe connects the drain electrode of the 2nd NMOS pipe, the source ground of the 2nd NMOS pipe, and the grid of the 2nd NMOS pipe connects output terminal;

The grid of said the 2nd PMOS pipe all is connected said first node with the grid of the 3rd NMOS pipe;

The drain electrode of said the 2nd PMOS pipe all is connected output terminal with the drain electrode of the 3rd NMOS pipe;

The source electrode of said the 3rd NMOS pipe connects pulse signal.

2. dynamic shift register cell according to claim 1 is characterized in that, said input signal is that low level is effective.

3. a dynamic shift register comprises pulse signal generator, it is characterized in that, also comprises N claim 1 or 2 described dynamic shift register cells, and N is a positive integer; The input end of first dynamic shift register cell connects input signal, and the output signal of previous dynamic shift register cell is as the input signal of a back dynamic shift register cell; Said pulse signal generator is used to produce the pulse signal that differs 1/4 periodic phase successively, successively as the pulse signal of each dynamic shift register cell.

4. dynamic shift register according to claim 3; It is characterized in that; Comprise four said dynamic shift register cells, be respectively first dynamic shift register cell, second dynamic shift register cell, the 3rd dynamic shift register cell and the 4th dynamic shift register cell;

Said pulse signal producer is used to produce four pulse signals that differ 1/4 periodic phase successively, is respectively first pulse signal, second pulse signal, the 3rd pulse signal and the 4th pulse signal; First pulse signal, second pulse signal, the 3rd pulse signal and the 4th pulse signal be respectively as first dynamic shift register cell, the pulse signal of second dynamic shift register cell, the 3rd dynamic shift register cell and the 4th dynamic shift register cell;

The input end of first dynamic shift register cell connects input signal, and output terminal connects the input end of second dynamic shift register cell;

The output terminal of second dynamic shift register cell connects the input end of the 3rd dynamic shift register cell;

The output terminal of the 3rd dynamic shift register cell connects the input end of the 4th dynamic shift register cell;

The output terminal of the 4th dynamic shift register cell is as the input signal of next dynamic shift register.

5. a dynamic shift register cell is characterized in that, comprising: the 5th PMOS pipe, the 4th PMOS pipe, the 5th PMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe and second electric capacity;

The grid of said the 4th PMOS pipe all is connected input signal with the grid of the 4th NMOS pipe;

The drain electrode of said the 4th PMOS pipe all is connected Section Point with the drain electrode of the 4th NMOS pipe;

The source electrode of said the 5th PMOS pipe connects power supply, and drain electrode connects the source electrode of the 4th PMOS pipe, and grid connects output terminal;

The source ground of said the 4th NMOS pipe;

Said second electric capacity is connected between power supply and the Section Point;

The grid of said the 5th PMOS pipe all is connected Section Point with the grid of the 5th NMOS pipe;

The drain electrode of said the 5th PMOS pipe all is connected output terminal with the drain electrode of the 5th NMOS pipe;

The source ground of said the 5th NMOS pipe; The source electrode of said the 5th PMOS pipe connects pulse signal.

6. dynamic shift register cell according to claim 5 is characterized in that, said input signal is that high level is effective.

7. a dynamic shift register comprises pulse signal generator, it is characterized in that, also comprises N claim 5 or 6 described dynamic shift register cells, and N is a positive integer; The input end of first dynamic shift register cell connects input signal, and the output signal of previous dynamic shift register cell is as the input signal of a back dynamic shift register cell; Said pulse signal generator is used to produce the pulse signal that differs 1/4 periodic phase successively, successively as the pulse signal of each dynamic shift register cell.

8. dynamic shift register; It is characterized in that; Comprise four said dynamic shift register cells, be respectively first dynamic shift register cell, second dynamic shift register cell, the 3rd dynamic shift register cell and the 4th dynamic shift register cell;

Said pulse signal producer is used to produce four pulse signals that differ 1/4 periodic phase successively, is respectively first pulse signal, second pulse signal, the 3rd pulse signal and the 4th pulse signal; First pulse signal, second pulse signal, the 3rd pulse signal and the 4th pulse signal be respectively as first dynamic shift register cell, the pulse signal of second dynamic shift register cell, the 3rd dynamic shift register cell and the 4th dynamic shift register cell;

The input end of first dynamic shift register cell connects input signal, and output terminal connects the input end of second dynamic shift register cell;

The output terminal of second dynamic shift register cell connects the input end of the 3rd dynamic shift register cell;

The output terminal of the 3rd dynamic shift register cell connects the input end of the 4th dynamic shift register cell;

The output terminal of the 4th dynamic shift register cell is as the input signal of next dynamic shift register.

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