CN102457188B - Digital flash lamp charging circuit - Google Patents
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- CN102457188B CN102457188B CN201010514534.8A CN201010514534A CN102457188B CN 102457188 B CN102457188 B CN 102457188B CN 201010514534 A CN201010514534 A CN 201010514534A CN 102457188 B CN102457188 B CN 102457188B
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- 230000006698 induction Effects 0.000 claims abstract description 22
- 238000004146 energy storage Methods 0.000 claims abstract description 9
- 238000005070 sampling Methods 0.000 claims description 34
- 239000000872 buffer Substances 0.000 description 21
- 238000010586 diagram Methods 0.000 description 9
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000452 restraining effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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Abstract
The invention provides a digital flash lamp charging circuit which comprises a transformer, a power supply element and a special application integrated circuit. A secondary side of the transformer is electrically connected to an energy storage element, and the power supply element can supply power to a primary side of the transformer. The special application integrated circuit outputs a pulse modulation signal to control whether the power is selectively inputted into the primary side or not, converts an induction signal generated at the secondary side of the transformer into a digital signal, and tracks an induction negative edge of the induction signal to adjust a cut-out time of the pulse modulation signal, thus a next pulse positive edge of the pulse modulation signal is close to a corresponding induction negative edge.
Description
Technical field
The present invention relates to a kind of charging circuit for flashlamp, relate in particular to a kind of break time of Application Specific Integrated Circuit with modulation PM signal of having, make the positive edge of its pulse can be close to the digital flash lamp charging circuit of the negative edge of induction.
Background technology
Current common charging circuit, in order to meet the demand of safety, power supply unit must provide stable output voltage and output current.Under this condition, the power supply unit of charging circuit is most likely in conjunction with transformer, and at the primary side of transformer, adjusting device is set, to reach the purpose of the charging/discharging function of adjusting output current and completing circuit simultaneously.In the design field of current related transformer, the primary side that the designer is chosen in transformer mostly arranges charging chip (Integrated Chip, IC), to realize charging circuit.
General common can be in order to the circuit that photoflash lamp is charged, be the charging circuit that utilizes charging chip (IC) to form, and use analog element to do the observation of voltage and electric current, so, this kind of mode also easily is subject to the impact of noise, makes the data distortion recorded.Secondly, the passive devices such as the resistance of charging chip (IC) and the required configuration of observation station, electric capacity have also accounted for sizable area and parts number on circuit board.Sum up above, utilize the circuit of charging chip (IC) so that photoflash lamp is discharged and recharged, in operation, certain complexity is not only arranged, on cost of manufacture and service behaviour, its considerable place is also arranged.
Summary of the invention
In view of above problem, the object of the invention is to propose a kind of digital flash lamp charging circuit, not only can be in order to solve the existing observation of using analog element to make voltage and electric current, can make the data that record easily be subject to noise effect and the problem of distortion, more can utilize logical circuit to replace existing charging chip (IC), to reduce component number and the area consumption used on circuit board.
To achieve these goals, the present invention proposes a kind of digital flash lamp charging circuit, is suitable for an energy-storage travelling wave tube charging.Digital flash lamp charging circuit comprises: a transformer, a source element and an Application Specific Integrated Circuit.Transformer has a primary side and a secondary side, and wherein secondary side is electrically connected at energy-storage travelling wave tube.Source element is to export an electric power.Application Specific Integrated Circuit is to export a PM signal, to control electric power, optionally whether inputs primary side.The PM signal has the positive edge of a pulse and a break time.Secondary side produces an induced signal in response to primary side, and induced signal has the negative edge of an induction.Application Specific Integrated Circuit is after induced signal is converted to a digital signal, follows the trail of the negative edge of induction according to digital signal, so as to adjusting break time, and makes the positive edge of next pulse close to the negative edge of corresponding induction.
So, the digital flash lamp charging circuit that the present invention proposes, can utilize the break time of Application Specific Integrated Circuit modulation PM signal, and make according to this positive edge of next pulse of PM signal to bear edge close to corresponding induction, to reach the higher operating efficiency that discharges and recharges.
Below in conjunction with the drawings and specific embodiments, describe the present invention, but not as a limitation of the invention.
The accompanying drawing explanation
Fig. 1 is digital flash lamp charging circuit according to an embodiment of the invention;
Fig. 2 A is the waveform schematic diagram according to one embodiment of the invention;
Fig. 2 B is the waveform schematic diagram according to one embodiment of the invention;
Fig. 2 C is the waveform schematic diagram according to one embodiment of the invention;
Fig. 3 A is the Application Specific Integrated Circuit according to the first embodiment of the present invention;
Fig. 3 B is Application Specific Integrated Circuit according to a second embodiment of the present invention;
The Application Specific Integrated Circuit that Fig. 3 C is a third embodiment in accordance with the invention;
The Application Specific Integrated Circuit that Fig. 3 D is a fourth embodiment in accordance with the invention;
Fig. 3 E is Application Specific Integrated Circuit according to a fifth embodiment of the invention;
Fig. 4 A is the sampling schematic diagram according to the first embodiment of the present invention;
Fig. 4 B follows the trail of to the schematic diagram of the negative edge of induction according to the positive edge of Fig. 4 A pulse;
The sampling schematic diagram that Fig. 4 C is a third embodiment in accordance with the invention;
Fig. 4 D follows the trail of to the schematic diagram of the negative edge of induction according to the positive edge of Fig. 4 C pulse;
The comparing reference diagram that Fig. 5 A is first and second embodiment sampling method according to the present invention; And
The comparing reference diagram that Fig. 5 B is the 3rd and the 4th embodiment sampling method according to the present invention;
Wherein, Reference numeral
Transformer 10 primary sides 11
Impulse controller 34,34a, 34b, 34c, 34d
Digital flash lamp charging circuit 100
The first buffer 310 second buffers 320
The second comparator 342 indicating controllers 350
Multiplexer 360,400
Flip-flop 370 filters 380
Secondary side switch current I
ssecondary side switch current maximum I
spk
Edge P-is born in the positive edge P+ of pulse pulse
Negative edge T-sample time of positive edge T+ sample time, T '-, T "-
Operating time T
onbreak time T
off, T '
off, T "
off
Induced signal V
fBthe negative edge V-of induction
Input voltage V
inoutput voltage V
o
Maximum allowance signal V
dUPminimal tolerance signal V
dWN
Maximum minimum detectable signal V
tHHminimum critical signal V
tHL
Sampling time point T for the first time
1sampling time point T for the second time
2
Sampling time point T for the third time
3the 4th sub-sampling time point T
4
PM signal V
pWMbasal signal V
cMP
Differential signal V
dIFFindex signal V
iND
Modulation time interval T
Δwork period T
d
Shifted signal V
oFF, V '
oFF, V "
oFF
Embodiment
Below in conjunction with accompanying drawing, structural principle of the present invention and operation principle are described in detail:
Fig. 1 is digital flash lamp charging circuit according to an embodiment of the invention.Digital flash lamp charging circuit 100 comprises a transformer 10, an Application Specific Integrated Circuit (Application-specific IntegratedCircuit, ASIC) 20 and one source element 30.Transformer 10 has primary side 11 and secondary side 12, and source element 30 is connected in the primary side 11 of transformer 10, and source element 30 is in order to provide an input voltage V
in(or claim electric power), and by the switching of transformer 10 and in its secondary side 12 output one output voltage V
o.The secondary side 12 of transformer 10 is connected in energy-storage travelling wave tube, and the input voltage V that can provide by source element 30
inenergy-storage travelling wave tube is charged.For example, energy-storage travelling wave tube can be as the electric capacity 50 in Fig. 1.
Application Specific Integrated Circuit 20 is disposed between the primary side 11 and secondary side 12 of transformer 10, and can be in order to produce a PM signal V
pWM, with control inputs voltage V
inoptionally input or do not input primary side 11.According to one embodiment of the invention, electric capacity 50 also can be connected in photoflash lamp, by digital flash lamp charging circuit 100, to complete the charging to photoflash lamp.
Please coordinate and consult Fig. 2 A to Fig. 2 C, as PM signal V
pWMwhile just being switched to electronegative potential, secondary side switch current I
scan there is secondary side switch current maximum I
spk, in this, the secondary side 12 of transformer 10 can form in response to secondary side switch current I simultaneously
sinduced signal V
fB.When the value of secondary side switch current Is along with the charging interval to electric capacity 50 (is PM signal V
pWMfor the time of electronegative potential) reduce gradually, and secondary side switch current I
swhile finally being returned to zero, induced signal V
fBalso can fade away, in this, be defined as induced signal V
fBthe negative edge V-of induction.
In this, PM signal V
pWMthe time point that is switched to high potential by electronegative potential is the positive edge P+ of pulse, PM signal V
pWMthe time point that is switched to electronegative potential by high potential is the negative edge P-of pulse, and PM signal V
pWMthere is an operating time T
onwith one break time T
off.Operating time T
onfor PM signal V
pWMfor the time interval of high potential (or claiming time span), and break time T
offfor PM signal V
pWMtime interval for electronegative potential.
Then refer to Fig. 3 A, Application Specific Integrated Circuit 20 comprises an analog-digital converter 32, an impulse controller (PWM controller) 34 and one pulse signal generator 36.Analog-digital converter 32 can be in order to transformation induction signal V
fBfor digital signal.That is to say, analog-digital converter 32 can be in order to induced signal V
fBsampled, and, along with different sampling time points, exported respectively some more digital signals.
According to the first embodiment of the present invention, as shown in Figure 3A, impulse controller 34 comprises one first buffer 310, one second buffer 320, a difference engine 330, one first comparator 340, an indicating controller 350 and is connected in a multiplexer 360 and the flip-flop 370 between the first buffer 310, the second buffer 320 and analog-digital converter 32.
For example, as shown in Figure 4 A, the user can pass through positive edge T+ sample time of software set one and negative edge T-sample time in advance, so that indicating controller 350 is in PM signal V
pWMthe negative edge P-of pulse after positive edge T+ sample time after, carry out sample trigger for the first time, namely the T of sampling time point for the first time of analog-digital converter 32 in Fig. 4 A
1.Then, at PM signal V
pWMfinish as time switching cycle T
d, and again arrive the positive edge P+ of its pulse, operating time T
onafter the negative edge P-of pulse, indicating controller 350 under negative edge T-sample time after the negative edge P-of pulse, carries out sample trigger for the second time, namely the T of sampling time point for the second time of analog-digital converter 32 in Fig. 4 A again
2.
Analog-digital converter 32 is in sampling time point T for the first time
1the digital signal obtained is basal signal V
cMP, in sampling time point T for the second time
2the digital signal obtained is shifted signal V
oFF.Difference engine 330 is connected in the first buffer 310 and the second buffer 320, and can be in order to obtain basal signal V
cMPwith shifted signal V
oFFdifference, export according to this differential signal V
dIFF.The first comparator 340 is connected in difference engine 330, and can be in order to poor sub-signal V
dIFFin a maximum allowance signal V
dUPwith a minimal tolerance signal V
dWN.
As shown in Figure 5A, as differential signal V
dIFFbe greater than maximum allowance signal V
dUPthe time (graphic middle Case-A), the index signal V of the first comparator 340 output one high potentials (Hit)
iND, that is to say that analog-digital converter 32 is in sampling time point T for the second time
2the shifted signal V that sampling obtains
oFFfor induced signal V
fBthe electronegative potential value.Therefore, indicating controller 350 can be according to index signal V
iNDhigh potential (Hit) signal, upgrade negative edge T-sample time and break time T
off.In this, according to the first embodiment of the present invention, as shown in Figure 4 A, negative edge T ' sample time next time-meeting is shortened a modulation time interval T again than previous negative edge T-sample time
Δ.And PM signal V
pWMt ' break time
offcan equal previous negative edge T-sample time.
Similarly, the negative edge sample time T ' of analog-digital converter 32 after the negative edge P-of its pulse-carry out sampling time point T for the third time
3sampling action.If now, as shown in Figure 5A, the first comparator 340 differential signal V that relatively difference engine 330 is exported
dIFFbe less than minimal tolerance signal V
dWNthe time (graphic middle Case-C), the index signal V of the first comparator 340 output
iNDfor electronegative potential (Not-hit), meaning be analog-digital converter 32 in sampling time point T3 for the third time sample shifted signal V '
oFFfor induced signal V
fBthe high potential value.Therefore, indicating controller 350 can be according to index signal V
iNDelectronegative potential (Not-hit) signal, again upgrade negative edge T-sample time and break time T
off.In this, as shown in Figure 4 A, negative edge T sample time next time "-can be again than 1/2nd modulation time interval T of previous negative edge T ' sample time-increase
Δ.And PM signal V
pWMt break time "
offcan be than previous break time of T '
off/ 2nd modulation time interval T again
Δ.
Then, analog-digital converter 32 is in this 4th sub-sampling time point T
4obtained shifted signal V "
oFFcan obtain shifted signal V via the second buffer 320 with difference engine 330 again "
oFFwith basal signal V
cMPdifference, and then by the first comparator 340 than maximum allowance signal V
dUPwith minimal tolerance signal V
dWN.The index signal V that indicating controller 350 can be exported according to the first comparator 340
iNDhigh or low current potential, and successively modulation with upgrade PM signal V
pWMt break time
offwith negative edge T-sample time.Due to modulation time interval T
Δcan preset by software, and modulation time interval T
Δcan successively reduce by half, and along with the time successively decreases.For this reason, the user can determine modulation time interval T in advance by software
Δbe decremented to a lower limit in certain hour.At modulation time interval T each time
Δin the situation of successively successively decreasing and restraining, as shown in Figure 4 B, final PM signal V
pWMthe positive edge P+ of pulse will close to its front one time break time T
offafter the induced signal V that thereupon produces
fBthe negative edge V-of induction, and PM signal V
pWMwork period T
dalso can be fixed up, until induced signal V
fBthe negative edge V-of induction position while changing, will continue tracking induced signal V according to the Application Specific Integrated Circuit 20 of the embodiment of the present invention
fBthe negative edge V-of induction.
In addition, for increasing the accuracy of data, impulse controller 34 can comprise more than one multiplexer 360, flip-flop 370 and a filter 380 again.Fig. 3 B is the Application Specific Integrated Circuit according to second embodiment of the invention, and wherein impulse controller 34a comprises one first buffer 310, one second buffer 320, a difference engine 330, one first comparator 340, an indicating controller 350 and is connected in filter 380, the multiplexer 360 and flip-flop 370 between the first buffer 310, the second buffer 320 and analog-digital converter 32.
In addition, Application Specific Integrated Circuit according to third embodiment of the invention, can also be as shown in Figure 3 C, wherein impulse controller 34b comprises one second buffer 320, one second comparator 342, an indicating controller 350 and is connected in a multiplexer 360 and the flip-flop 370 between the second buffer 320 and analog-digital converter 32.
Refer to Fig. 4 C, the user can pass through the negative edge of software set one T-sample time in advance, to guarantee that analog-digital converter 32 is in sampling time point T for the first time
1the time, can be sampled to induced signal V
fBthe electronegative potential value.
Analog-digital converter 32 is in sampling time point T for the first time
1the digital signal obtained is shifted signal V
oFF, shifted signal V
oFFcan be temporary among the second buffer 320 via the triggering of changing settling signal (end of convert) in Fig. 3 C.The second comparator 342 is connected in the second buffer 320, and can be in order to compare shifted signal V
oFFin a maximum minimum detectable signal V
tHHwith a minimum critical signal V
tHL.
As shown in Figure 5 B, as shifted signal V
oFFbe less than minimum critical signal V
tHLthe time (graphic middle Case-A), the index signal V of the second comparator 342 output high potentials
iND.Therefore, indicating controller 350 can be according to index signal V
iNDhigh potential (Hit) signal, upgrade negative edge T-sample time and break time T
off.In this, a third embodiment in accordance with the invention, as shown in Figure 4 C, negative edge T ' sample time next time-meeting is shortened a modulation time interval T again than previous negative edge T-sample time
Δ.And PM signal V
pWMt ' break time
offcan equal previous negative edge T-sample time.
Similarly, the negative edge sample time T ' of analog-digital converter 32 after the negative edge P-of its pulse-carry out sampling time point T for the second time
2sampling action.In this, analog-digital converter 32 is in sampling time point T for the second time
2lower be sampled to shifted signal V '
oFFalso can be under the triggering that converts signal (end of convert), and deposited to the second buffer 320.Then, please coordinate and consult Fig. 5 B, if the second comparator 342 relatively analog-digital converters 32 in sampling time point T for the second time
2the shifted signal V ' be sampled to
oFFbe greater than maximum minimum detectable signal V
tHHthe time (graphic middle Case-C), the index signal V of the second comparator 342 output electronegative potentials
iND.Therefore, indicating controller 350 can be according to index signal V
iNDelectronegative potential (Not-hit) signal, again upgrade negative edge T-sample time and break time T
off.In this, negative edge T sample time next time "-can be again than 1/2nd modulation time interval T of previous negative edge T ' sample time-increase
Δ.And PM signal V
pWMt break time "
offcan be than previous break time of T '
off/ 2nd modulation time interval T again
Δ.
Then, analog-digital converter 32 is in sampling time point T for the third time
3obtained shifted signal V "
oFFcan be temporary in again in the second buffer 320, and then pass through the second comparator 342 than maximum minimum detectable signal V
tHHwith minimum critical signal V
tHL.The index signal V exported according to the second comparator 342
iNDhigh or low current potential, and successively modulation with upgrade PM signal V
pWMt break time
offwith negative edge T-sample time.
At modulation time interval T each time
Δin the situation of successively successively decreasing and restraining, as shown in Figure 4 D, final PM signal V
pWMthe positive edge P+ of pulse will close to its front one time break time T
offafter the induced signal V that thereupon produces
fBthe negative edge V-of induction, and PM signal V
pWMwork period T
dalso can be fixed up thereupon.
Another for increasing the accuracy of data, impulse controller 34b can comprise more than one multiplexer 360, flip-flop 370 and a filter 380 again.Fig. 3 D is the Application Specific Integrated Circuit according to fourth embodiment of the invention, and wherein impulse controller 34c comprises one second buffer 320, one second comparator 342, an indicating controller 350 and is connected in filter 380, the multiplexer 360 and flip-flop 370 between the second buffer 320 and analog-digital converter 32.
In addition, according to a fifth embodiment of the invention, can also be in conjunction with the second embodiment (as Fig. 3 B) and the 4th embodiment (as Fig. 3 D), to become a preferred embodiment.Refer to Fig. 3 E, for better the 5th embodiment of the present invention, the combination that wherein sampling theorem of impulse controller 34d is the second embodiment of the present invention (as Fig. 3 B) and the 4th embodiment (as Fig. 3 D), only the impulse controller 34d of this preferred embodiment has also comprised a multiplexer 400.
So, digital flash lamp charging circuit according to the embodiment of the present invention, can utilize analog-digital converter to be sampled induced signal, and according to two kinds of algorithms (as first and second embodiment and third and fourth embodiment), make the positive edge of pulse of PM signal to bear edge close to the induction of induced signal, so that transformer can be got back in the primary side charging, so as to reaching the operating efficiency that digital flash lamp charging circuit is higher.
Certainly; the present invention also can have other various embodiments; in the situation that do not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (6)
1. a digital flash lamp charging circuit, be suitable for an energy-storage travelling wave tube charging, and described energy-storage travelling wave tube is connected in described photoflash lamp, it is characterized in that, this digital flash lamp charging circuit comprises:
One transformer, have a primary side and a secondary side, and this secondary side is electrically connected at this energy-storage travelling wave tube;
One source element, export an electric power; And
One pulsewidth modulated intergrated circuit, export a PM signal and optionally whether input this primary side to control this electric power, this PM signal has the positive edge of a pulse and a break time, this secondary side responds this primary side and produces an induced signal, this induced signal has the negative edge of an induction, after this pulsewidth modulated intergrated circuit is converted to a digital signal by this induced signal, follow the trail of the negative edge of this induction according to this digital signal to adjust this break time, make the positive edge of next this pulse approach the negative edge of this corresponding induction
Wherein, this pulsewidth modulated intergrated circuit comprises:
One analog-digital converter, in order to change this induced signal for this digital signal;
One pulse signal generator, according to producing an operating time, this break time this PM signal, this PM signal sequentially comprises the positive edge of this pulse, this operating time, the negative edge of a pulse and this break time; And
One impulse controller, originate from this analog-digital converter and obtain a sampling value according to positive edge sample time, a negative edge sample time and this pulse are negative, this impulse controller is according to critical value on this sampling value,, and critical value and upgrade this break time and should bear edge sample time once.
2. digital flash lamp charging circuit according to claim 1, it is characterized in that, this impulse controller originates from this analog-digital converter and obtains a high potential value according to this positive edge sample time and this pulse are negative, this impulse controller is according to should negative edge sample time and this pulse is negative originates from this analog-digital converter and obtain an electronegative potential value, and it is this sampling value that this impulse controller be take the difference of this high potential value and this electronegative potential value.
3. digital flash lamp charging circuit according to claim 1, it is characterized in that, this impulse controller originates from this analog-digital converter and obtains a plurality of high potential values according to this positive edge sample time and this pulse are negative, this impulse controller is according to should negative edge sample time and this pulse is negative originates from this analog-digital converter and obtain a plurality of electronegative potential values, it is this sampling value that this impulse controller be take the difference of a high potential meta numerical value and an electronegative potential meta numerical value, wherein this high potential meta numerical value and this electronegative potential meta numerical value are respectively the median of those high potential values and the median of those electronegative potential values.
4. digital flash lamp charging circuit according to claim 1, is characterized in that, this impulse controller is according to should negative edge sample time and this pulse is negative originates from this analog-digital converter and obtain an electronegative potential value, and take this electronegative potential value as this sampling value.
5. digital flash lamp charging circuit according to claim 1, it is characterized in that, this impulse controller is according to should negative edge sample time and this pulse is negative originates from this analog-digital converter and obtain a plurality of electronegative potential values, and to take an electronegative potential meta numerical value be this sampling value, the median that wherein this electronegative potential meta numerical value is those electronegative potential values.
6. digital flash lamp charging circuit according to claim 1, it is characterized in that, this impulse controller originates from this analog-digital converter and obtains a plurality of high potential values according to this positive edge sample time and this pulse are negative, this impulse controller is according to should negative edge sample time and this pulse is negative originates from this analog-digital converter and obtain a plurality of electronegative potential values, this impulse controller also comprises a multiplexer, and optionally to take a difference meta numerical value and an electronegative potential meta numerical value according to this multiplexer be this sampling value, wherein those high potential values have a high potential meta numerical value, the median that described high potential meta numerical value is those high potential values, and the median that this electronegative potential meta numerical value is those electronegative potential values, the difference that this difference meta numerical value is this high potential meta numerical value and this electronegative potential meta numerical value.
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|---|---|---|---|
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|---|---|---|---|
| CN201010514534.8A CN102457188B (en) | 2010-10-15 | 2010-10-15 | Digital flash lamp charging circuit |
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| CN102457188B true CN102457188B (en) | 2014-01-01 |
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|---|---|---|---|---|
| CN101420179A (en) * | 2007-10-22 | 2009-04-29 | 罗姆股份有限公司 | Capacitor charging circuit and control circuit, control method and electronic equipment |
| CN101447737A (en) * | 2008-12-25 | 2009-06-03 | 杭州电子科技大学 | Constant power output direct current transforming circuit |
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| US7961485B2 (en) * | 2007-12-12 | 2011-06-14 | Semiconductor Components Industries, Llc | Method of forming a PWM controller and structure therefor |
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| CN101420179A (en) * | 2007-10-22 | 2009-04-29 | 罗姆股份有限公司 | Capacitor charging circuit and control circuit, control method and electronic equipment |
| CN101447737A (en) * | 2008-12-25 | 2009-06-03 | 杭州电子科技大学 | Constant power output direct current transforming circuit |
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