CN102456637A - Heat sink with bump/pedestal and semiconductor chip assembly body with cavity in bump - Google Patents

Abstract

A semiconductor chip assembly having a bump/pad heat spreader and a cavity in the bump. A semiconductor chip assembly at least comprises a semiconductor device, a heat sink, a lead and an adhesive layer. The heat spreader includes a bump, a base and a flange. The conductive wire includes a pad and a terminal. The semiconductor element extends into a cavity of the bump and is electrically connected to the conductive line while being thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends from the bump in a direction opposite the cavity, and the flange extends from the bump side at the cavity entrance. The wire is located outside the cavity and provides signal routing between the pad and the terminal.

Description

Heat sink with bump/pedestal and semiconductor chip assembly body with cavity in bump

technical field

The invention relates to a semiconductor chip assembly body, more specifically, a semiconductor chip assembly body with semiconductor elements, wires, adhesive layers and heat sinks and a manufacturing method thereof.

Background technique

Existing semiconductor components such as packaged and unpackaged semiconductor chips can provide high-voltage, high-frequency and high-performance applications; these applications require high power consumption to perform specific functions, but the higher the power, the semiconductor Components generate more heat. In addition, after the packaging density is increased and the size is reduced, the surface area available for heat dissipation is reduced, which leads to serious accumulation of heat energy.

Semiconductor components are prone to problems such as performance degradation and shortened service life under high temperature operation, and may even fail immediately. High heat not only affects chip performance, but may also cause thermal stress on the chip and its surrounding components due to thermal expansion mismatch. Therefore, it is necessary to quickly and effectively dissipate heat from the chip to ensure its operating efficiency and reliability. A high thermal conductivity path typically conducts and dissipates thermal energy to an area with a larger surface area than the chip or die pad on which the chip resides.

Light-emitting diodes (LEDs) have recently become popular as an alternative to incandescent, fluorescent, and halogen light sources. LEDs can provide high energy efficiency and low-cost long-time lighting for applications such as medical, military, signage, signaling, aviation, marine, vehicles, portable devices, commercial and household lighting. For example, LEDs can provide light sources for equipment such as lamps, flashlights, headlights, searchlights, traffic lights and displays.

The high-power chips in LEDs generate a lot of heat while providing high light output. However, under high-temperature operation, LEDs suffer from problems such as color shift, reduced brightness, shortened lifespan, and immediate failure. In addition, LEDs have limitations in terms of heat dissipation, which in turn affects their light output and reliability. Therefore, LEDs particularly highlight the market's demand for high-power chips with good heat dissipation.

The LED package usually includes an LED chip, a base, an electrical contact and a thermal contact. The base is thermally connected to the LED chip and serves to support the LED chip. The electrical contacts are electrically connected to the positive pole and the negative pole of the LED chip. The thermal junction is thermally connected to the LED chip through the base, and the carrier below it can sufficiently dissipate heat to prevent the LED chip from overheating.

People in the field are actively investing in the research and development of high-power chip packages and heat-conducting plates with various design and manufacturing technologies in order to meet performance requirements in this extremely cost-competitive environment.

The plastic ball grid array (PBGA) package is to wrap a chip and a laminated substrate in a plastic case, and then stick it on a printed circuit board (PCB) with solder balls. The laminate substrate includes a dielectric layer, usually containing glass fibers. The heat energy generated by the chip can be transferred to the solder ball through the plastic and dielectric layer, and then to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, PBGAs do not dissipate heat well.

Quad Flat No-Lead (QFN) packages place the chip on a copper die pad soldered to a printed circuit board. The heat energy generated by the chip can be transferred to the printed circuit board through the die pad. However, due to the limited routing capability of its lead frame interposer, the QFN package is not suitable for high input/output (I/O) chips or passive components.

The heat conduction plate provides functions such as electrical routing, thermal management and mechanical support for semiconductor components. A thermal pad usually consists of a substrate for signal routing, a heat sink or heat sink for heat removal, a solder pad for power connection to semiconductor components, and a power connection to the next layer of semiconductor chip assembly terminal. The substrate can be a laminated structure with single or multi-layer routing circuitry and one or more dielectric layers. The heat sink can be a metal base, a metal block or a buried metal layer.

The thermally conductive plate is bonded to the semiconductor chipset body of the next layer. For example, the next semiconductor chip assembly body can be a lamp holder with a printed circuit board and a heat dissipation device. In this example, an LED package is mounted on a heat conduction plate, the heat conduction plate is disposed on a heat sink, and the heat conduction plate/heat sink subassembly and the printed circuit board are disposed in the lamp holder. In addition, the heat conducting plate is electrically connected to the printed circuit board via wires. The base plate guides electric signals from the printed circuit board to the LED packaging body, and the heat sink dissipates and transmits the heat energy of the LED packaging body to the heat dissipation device. Therefore, the heat conducting plate can provide an important heat path for the LED chips.

US Patent No. 6,507,102 to Juskey et al. discloses a semiconductor chip assembly in which a composite substrate composed of glass fibers and cured thermosetting resin includes a central opening. A heat slug having a square or rectangular shape similar to the aforementioned central opening is adhered to the sidewall of the central opening so as to be combined with the substrate. The upper and lower conductive layers are adhered to the top and the bottom of the substrate respectively, and are electrically connected to each other through the electroplating via holes penetrating the substrate. A chip is arranged on the heat dissipation block and bonded to the upper conductive layer by wire bonding, a packaging material is molded on the chip, and the lower conductive layer is provided with solder balls.

During manufacture, the substrate is originally a B-stage resin film placed on the lower conductive layer. The heat dissipation block is inserted in the central opening, thus located on the lower conductive layer, and separated from the substrate by a gap. The upper conductive layer is arranged on the substrate. After the upper and lower conductive layers are heated and pressed together, the resin is melted and flows into the aforementioned gap to solidify. The upper and lower conductive layers are patterned, thereby forming circuit wiring on the substrate, and exposing the resin flash on the heat dissipation block. The resin flash is then removed to expose the heat slug. Finally, the chip is placed on the heat dissipation block and then wire bonded and packaged.

Therefore, the heat energy generated by the chip can be transferred to the printed circuit board through the heat slug. However, in mass production, manually placing the heat sink in the central opening is extremely labor-intensive and expensive. Furthermore, due to the small lateral installation tolerance, it is not easy to accurately locate the heat dissipation block in the central opening, resulting in gaps and uneven wiring between the substrate and the heat dissipation block. As a result, the substrate is only partially adhered to the heat dissipation block, cannot obtain sufficient supporting force from the heat dissipation block, and is easy to delaminate. In addition, the chemical etchant used to remove part of the conductive layer to expose the resin flash will also remove part of the heat sink that is not covered by the resin flash, making the heat sink uneven and difficult to bond, resulting in a low yield of the semiconductor chip assembly , Insufficient reliability and high cost.

US Patent No. 6,528,882 to Ding et al. discloses a high heat dissipation ball grid array package, the substrate of which includes a metal core layer, and the chip is placed on the die pad area on the top surface of the metal core layer. An insulating layer is formed on the bottom surface of the metal core layer. The blind hole penetrates the insulating layer and directly leads to the metal core layer, and the hole is filled with heat-dissipating solder balls, and solder balls corresponding to the heat-dissipating solder balls are arranged on the substrate. The heat energy generated by the chip can flow to the heat dissipation solder ball through the metal core layer, and then flow to the printed circuit board. However, the insulating layer interposed between the metal core layer and the printed circuit board restricts the heat flow to the printed circuit board.

US Patent No. 6,670,219 to Lee et al. discloses a recessed down ball grid array (CDBGA) package in which a ground plate with a central opening is disposed on a heat sink to form a heat sink substrate. A substrate with a central opening is disposed on the ground plate through an adhesive layer with a central opening. A chip is installed in a groove formed by the central opening of the ground plate on the heat sink, and solder balls are arranged on the substrate. However, since the solder balls are located on the substrate, the heat sink cannot contact the printed circuit board, so the heat dissipation effect of the heat sink is limited to heat convection rather than heat conduction, thus greatly limiting its heat dissipation effect.

US Patent No. 7,038,311 to Woodall et al. provides a high heat dissipation BGA package with an inverted T-shaped heat sink comprising a post and a wide base. A substrate with a window-shaped opening is placed on the wide base, and an adhesive layer adheres the post and the wide base to the substrate. A chip is placed on the post and bonded to the substrate by wire bonding, a packaging material is molded on the chip, and solder balls are arranged on the substrate. The post extends through the window opening and supports the substrate by the wide base, and the solder balls are located between the wide base and the periphery of the substrate. The heat energy generated by the chip can be transmitted to the wide base through the pillars, and then to the printed circuit board. However, the wide base only protrudes below the substrate at a position corresponding to the position between the central window and the innermost solder ball, since there must be room on the wide base to accommodate the solder balls. As a result, the substrate is unbalanced during the manufacturing process, and is easy to shake and bend, which leads to difficulties in chip mounting, wire bonding, and packaging material molding. In addition, the wide base may bend due to the molding of the packaging material, and once the solder balls collapse, it may prevent the package from being soldered to the next semiconductor chip assembly body. Therefore, the yield rate of the package is low, the reliability is insufficient and the cost is too high.

U.S. Patent Application Publication No. 2007/0267642 of Erchak et al. proposes a light-emitting device semiconductor chip assembly, wherein an inverted T-shaped base includes a substrate, a protrusion and an insulating layer with a through hole. The insulating layer and has electrical contacts. A packaging body with a through hole and a transparent upper cover is arranged on the electrical contact. An LED chip is arranged on the protruding part and connected to the substrate by wire bonding. The protruding portion is adjacent to the substrate and extends through the insulating layer and the through hole on the package body to enter the package body. The insulating layer is arranged on the substrate, and the insulating layer is provided with electric contacts. The package body is arranged on the electrical contacts and keeps a distance from the insulating layer. The heat energy generated by the chip can be transferred to the substrate through the protruding part, and then reaches a heat dissipation device. However, these electrical contacts are not easy to be disposed on the insulating layer, and it is difficult to electrically connect with the semiconductor chip assembly of the next layer, and it is impossible to provide multi-layer routing.

Existing packages and thermal pads have significant disadvantages. For example, electrical insulating materials with low thermal conductivity, such as epoxy resin, limit the heat dissipation effect, while electrical insulating materials with higher thermal conductivity, such as epoxy resin filled with ceramic or silicon carbide, have low adhesion and The disadvantage of high mass production cost. The electrically insulating material may delaminate due to heat during fabrication or early in operation. If the substrate is a single-layer circuit system, the routing capability is limited, but if the substrate is a multi-layer circuit system, the over-thick dielectric layer will reduce the heat dissipation effect. In addition, the previous technology has problems such as insufficient performance of the heat sink, too large volume, or difficult thermal connection to the next layer of semiconductor chipset. The manufacturing process of the prior art is also not suitable for low-cost mass production.

In view of the various development situations and related limitations of existing high-power semiconductor component packages and heat-conducting plates, there is a real need for a cost-effective, reliable performance, suitable for mass production, multi-functional, flexible signal routing and excellent heat dissipation. semiconductor chipsets.

Contents of the invention

Cross-references to related applications:

This application is a continuation-in-part of U.S. Patent Application Serial No. 12/616,773, filed November 11, 2009, and a continuation-in-part of U.S. Patent Application Serial No. 12/616,775, filed November 11, 2009 The contents of the above two cases are incorporated herein by reference. This application also claims priority to U.S. Provisional Patent Application No. 61/330,318, filed May 1, 2010, and U.S. Provisional Patent Application No. 61/350,036, filed June 1, 2010, both of which The content of the case is also incorporated herein by reference.

Prior U.S. Patent Application No. 12/616,773, filed November 11, 2009, and U.S. Patent Application No. 12/616,775, previously filed November 11, 2009, both filed September 11, 2009 12/557,540 US patent application filed on September 11, 2009, which is also a continuation-in-part of US patent application number 12/557,541 filed on September 11, 2009.

Prior U.S. Patent Application No. 12/557,540, filed September 11, 2009, and U.S. Patent Application No. 12/557,541, previously filed September 11, 2009, both filed March 18, 2009 A continuation-in-part of US Patent Application No. 12/406,510 filed on . This U.S. Patent Application No. 12/406,510 asserts U.S. Provisional Patent Application No. 61/071,589, filed May 7, 2008, U.S. Provisional Patent Application No. 61/071,588, filed May 7, 2008 , U.S. Provisional Patent Application No. 61/071,072, filed April 11, 2008, and U.S. Provisional Patent Application No. 61/064,748, filed March 25, 2008, the contents of which are Incorporated herein by reference. U.S. Patent Application No. 12/557,540, previously filed September 11, 2009, and U.S. Patent Application No. 12/557,541, previously filed September 11, 2009, also claim February 9, 2009 Priority to U.S. Provisional Patent Application No. 61/150,980, filed on , the contents of which are incorporated herein by reference.

The object of the present invention is to overcome the aforementioned defects and provide a novel semiconductor chip assembly.

The invention provides a semiconductor chip assembly body, which includes a semiconductor element, a heat sink, a wire and an adhesive layer. The heat sink includes a bump, a base and a flange layer. The wire includes a welding pad and a terminal. The semiconductor element extends into a cavity of the bump, is electrically connected to the wire, and is thermally connected to the bump. The bump extends into an opening of the adhesive layer from the base, the base extends perpendicularly from the bump in a direction opposite to the recess, the flange layer is from the side of the bump at the entrance of the recess to extend. The wire is located outside the cavity and can provide signal routing between the pad and the terminal.

According to a form of the present invention, a semiconductor chip assembly includes a semiconductor element, an adhesive layer, a heat sink and a wire. The adhesive layer has an opening. The heat sink includes a bump, a base, and a flange layer, wherein (i) the bump is adjacent to the base and the flange layer, and is integrated with the flange layer, and the bump is formed from the base extending along a first vertical direction and extending from the flange layer along a second vertical direction opposite to the first vertical direction; (ii) the base extends from the bump along the second vertical direction and from The bump protrudes laterally along a side direction perpendicular to the vertical directions; (iii) the flange layer extends laterally from the bump and keeps a distance from the base; (iv) the bump has a side surface the cavity facing the first vertical direction, the cavity is covered by the bump in the second vertical direction, and the bump also separates the cavity from the base; in addition, the cavity has a Entrance at the edge. The wire includes a welding pad and a terminal.

The semiconductor element extends into the cavity, and is electrically connected to the pad, thereby electrically connected to the terminal; the semiconductor element is also thermally connected to the bump, thereby thermally connected to the base. The adhesive layer contacts the bump, the base and the flange layer, is located between the base and the flange layer, and extends laterally from the bump to the terminal or beyond the terminal. The wire is located outside the cavity. The bump extends into the opening and covers the semiconductor element in the second vertical direction. The pocket extends into the opening.

According to another aspect of the present invention, a semiconductor chip assembly includes a semiconductor element, an adhesive layer, a heat sink, a substrate and a wire. The adhesive layer has an opening. The heat sink includes a bump, a base, and a flange layer, wherein (i) the bump is adjacent to the base and the flange layer, and is integrated with the flange layer, and the bump is formed from the base extending along a first vertical direction, and extending from the flange layer along a second vertical direction opposite to the first vertical direction; (ii) the base extends from the bump along the second vertical direction, and at The second vertical direction covers the bump and protrudes laterally from the bump in a side direction perpendicular to the vertical directions; (iii) the flange layer extends laterally from the bump and is connected to the base keep a distance; (iv) the bump has a cavity facing the first vertical direction, the cavity is covered by the bump in the second vertical direction, and the bump also separates the cavity from the base seat, in addition, the recess has an entrance located at the flange layer. The substrate includes a dielectric layer, and a via extends through the substrate. The wire includes a welding pad and a terminal.

The semiconductor element extends into the cavity, and is electrically connected to the pad, thereby electrically connected to the terminal; the semiconductor element is also thermally connected to the bump, thereby thermally connected to the base. The adhesive layer contacts the bump, the base, the flange layer and the dielectric layer, and is located between the bump and the dielectric layer, between the flange layer and the dielectric layer, and between the base and the dielectric layer. Between the flange layer, the adhesive layer also extends laterally from the bump to the peripheral edge of the semiconductor chip assembly body. The wire is located outside the cavity. The bump extends into the opening and the through hole, and covers the semiconductor device in the second vertical direction. The cavity extends into the opening and the through hole.

The heat sink can be composed of the bump, the base and the flange layer. The heat sink can also consist essentially of copper, aluminum or copper/nickel/aluminum alloy. The heat sink may also consist of an inner copper, aluminum or copper/nickel/aluminum alloy core and coated contacts consisting of gold, silver and/or nickel. No matter which composition method is used, the heat sink can provide heat dissipation, and the heat energy of the semiconductor element can be diffused to the next layer of semiconductor chip assembly.

The semiconductor element can be disposed on the bump, overlap the bump but not overlap the substrate or the wire, and at the same time be electrically connected to the pad through a bonding wire extending outside the cavity, and through a The die-bonding material in the cavity is thermally connected to the bump. For example, the semiconductor element can extend inside and outside the cavity, while the bonding wire can be located outside the cavity. Alternatively, the semiconductor element can be located in the cavity, and the bonding wire can extend inside and outside the cavity. No matter which method is adopted, the semiconductor element extends into and is located in the periphery of the cavity, and the bonding wire extends inside and outside the periphery of the cavity.

The semiconductor device can be a packaged or unpackaged semiconductor chip. For example, the semiconductor element can be an LED package including LED chips. Alternatively, the semiconductor element may be a semiconductor chip such as an LED chip.

The adhesive layer can contact the bump and the dielectric layer in a gap between the bump and the substrate in the through hole, extend across the dielectric layer in the gap, and contact outside the gap The base, the dielectric layer and the terminal. The adhesive layer can also cover the portion of the base outside the bump in the first vertical direction, cover the substrate in the first vertical direction, and cover and surround the bump in the side directions. The adhesive layer can also conformally coat the sidewall of the bump, a surface portion of the pedestal, and a surface of the dielectric layer, wherein the surface portion of the pedestal adjoins the bump and is formed from the bump. The blocks project laterally while facing the first vertical direction, and the surface of the dielectric layer also faces the first vertical direction. The adhesive layer can also fill the space between the bump and the dielectric layer, the space between the base and the flange layer, and the space between the base and the substrate.

The adhesive layer can extend laterally from the bump to the terminal or beyond the terminal. For example, the adhesive layer and the terminal can extend to the peripheral edge of the semiconductor chip package body; in this case, the adhesive layer extends laterally from the bump to the terminal. Alternatively, the adhesive layer may extend to the peripheral edge of the semiconductor chip assembly body, while the terminals are kept at a distance from the peripheral edges of the semiconductor chip assembly body; in this case, the adhesive layer is from the side of the bump extends beyond the terminal.

The bump may be integral with the flange layer. For example, the bump and the flange layer can be a single metal body, or include a single metal body at their interface, wherein the single metal body can be copper. The thickness of the bump can also be greater than the thickness of the base. In addition, the bump and the adhesive layer can be coplanar at the base. The bump may also contact the adhesive layer but be spaced from the dielectric layer while extending into the opening and the via.

The protrusion may include a first bent corner adjacent to the base and a second bent corner adjacent to the flange layer. The bumps may also have a characteristic non-uniform thickness that is stamped. In addition, the diameter of the protrusion at the flange layer may be larger than the diameter of the protrusion at the base. For example, the bump can be in the shape of a flat-topped cone or a pyramid, and its diameter increases from the base along the first vertical direction toward the flange layer. For another example, the protrusion may include a third bent corner, wherein the diameter of the protrusion increases from the base along the first vertical direction to the third bent corner, and as for the protrusion from the first The diameter of the portion of the flange layer extending from the three bent corners along the first vertical direction remains unchanged. In addition, the vertical position of the third bent corner can be between opposite main surfaces of the semiconductor device. The bump can also be a cylindrical shape with a fixed diameter. The bump can also provide a concave die seat and a reflector for the semiconductor device.

The diameter at the entrance of the cavity may be larger than the diameter at the bottom of the cavity. For example, the cavity may be in the shape of a flat-topped cone or a pyramid, and its diameter increases from its bottom plate toward its entrance along the first vertical direction. Alternatively, the diameter of the recess may increase from its base plate along the first vertical direction to the third bent corner, and the recess extends from the third bent corner to the recess along the first vertical direction. The diameter of the hole entrance remains unchanged. The pocket may also be cylindrical with a fixed diameter. The entrance and floor of the pocket can also have a round, square or rectangular perimeter. The recess may also have a shape conforming to the bump, extending into the opening and the through hole, and encompassing a majority of the bump in the vertical and lateral directions.

The base can have a uniform thickness and keep a distance from the conductive layer and the dielectric layer. For example, the pedestal may occupy the same spatial extent as the bump, or extend laterally from the bump to the adhesive layer without extending to the conductive layer or the dielectric layer.

The pedestal may have a first thickness adjacent to the bump and a second thickness greater than the first thickness adjacent to the dielectric layer. In addition, the pedestal may also have a side facing the second A flat surface in a vertical direction. A portion of the base adjacent to the adhesive layer and distanced from the dielectric layer may also have the first thickness, and a corner of the base adjacent to the adhesive layer and the dielectric layer may also have the first thickness. Two thickness. The base can also contact the adhesive layer and the dielectric layer, cover the flange layer in the second vertical direction, extend laterally beyond the flange layer, support the substrate and the adhesive layer, and connect with the semiconductor chip set Keep a distance around the perimeter of the body. The surface area of the base on a lateral plane may be larger than the joint surface area of the protrusion and the flange layer on a lateral plane, and more than twice the surface area of the protrusion on a lateral plane.

The thickness of the flange layer may be greater than the thickness of the base. The flange layer can also contact the adhesive layer, keep a distance from the dielectric layer, and extend outside the adhesive layer and the dielectric layer along the first vertical direction. The flange layer can also have a round, square or rectangular perimeter.

The flange layer and the solder pad may have the same thickness and be coplanar on a surface facing the first vertical direction. The base and the terminal adjacent to each other may have the same thickness, and the thickness of the base adjacent to the protrusion may be different from the thickness of the terminal. The base and the terminal are located on a side facing the second vertical direction. The surfaces are coplanar.

The substrate can contact the base and keep a distance from the bump, the flange layer and the welding pad. The substrate can also be a laminated structure.

The conducting wire may include a routing line, which is located on a conductive path between the pad and the terminal, and extends outside the adhesive layer and the dielectric layer toward the first vertical direction. Likewise, the conductive line may include a coated via on a conductive path between the pad and the terminal and extending through the adhesive layer and the dielectric layer. For example, the solder pad may extend outside the adhesive layer and the dielectric layer toward the first vertical direction, the terminal may extend outside the adhesive layer and the dielectric layer toward the second vertical direction, and the coated through hole It can penetrate through the adhesive layer and the dielectric layer, and electrically connect the pad and the terminal. Likewise, the pad and the routing line may extend outside the adhesive layer and the dielectric layer toward the first vertical direction, and the terminal may extend outside the adhesive layer and the dielectric layer toward the second vertical direction. On the outside, the covering through hole can pass through the adhesive layer and the dielectric layer, and electrically connect the routing line and the terminal.

The wire can contact the adhesive layer and the dielectric layer, and keep a distance from the heat sink. For example, the solder pad may contact the adhesive layer but be spaced from the dielectric layer, the terminal may contact the dielectric layer but be spaced from the adhesive layer, the coated via may contact and extend through the adhesive layer and the dielectric layer. electrical layer, thereby providing vertical signal routing between the pad and the terminal. Likewise, the solder pad and the routing line can contact the adhesive layer but keep a distance from the dielectric layer, the terminal can contact the dielectric layer but keep a distance from the adhesive layer, and the coated through-hole can contact and extend through the The adhesive layer and the dielectric layer thus provide horizontal signal routing between the pad and the coated via, and vertical signal routing between the routing line and the terminal. Furthermore, the covered through hole can extend to a peripheral edge of the semiconductor chip assembly body, or keep a distance from the peripheral edge of the semiconductor chip assembly body.

The wire may consist of the pad, the terminal and the covered through hole. The wire may also consist essentially of copper. The wire may also consist of an inner copper core and covered contacts of gold, silver and/or nickel. No matter which composition method is used, the wire can provide signal routing between the pad and the terminal.

The pad can be used as an electrical contact point of the semiconductor element, and the terminal can be used as an electrical contact point of the semiconductor chip assembly body of the next layer, and the pad and the terminal can be connected between the semiconductor element and the semiconductor chip assembly body of the next layer. Provide signal routing between.

The bump, the base, the flange layer, the solder pad, the terminal and the covered through-hole can use the same metal. For example, the bump, the pedestal, the flange layer, the pad, the terminal and the coated via may comprise a gold, silver or nickel surface layer and an inner copper core, mainly copper. In this example, a covered contact may comprise a gold or silver surface layer and an inner nickel layer in contact with and between the surface layer and the inner copper core; alternatively, the covered contact may comprise a contact The nickel surface layer of the inner copper core. In addition, the heat sink may include a copper core shared by the bump, the base and the flange layer, and the wire may include a copper core shared by the solder pad, the terminal, and the coated through hole. For example, the heat sink and the leads may comprise a gold, silver or nickel surface layer and an inner copper core, mainly copper. In this case, the heat sink may include a covered contact disposed on the bump and the flange layer at a distance from the base; the heat sink may include another covered contact disposed on the on the base and keep a distance from the bump and the flange layer; as for the wire, it may include a covered contact located on the pad, the terminal and the covered through hole.

The semiconductor chip assembly may include an encapsulation material extending into the cavity and covering the semiconductor element in the first vertical direction. The encapsulation material can also be located in the cavity, or extend inside or outside the cavity. The lateral extent of the encapsulation material may be limited by the cavity, or the encapsulation material may extend laterally from the cavity. The encapsulation material can contact the semiconductor element in the cavity, and at the same time fill up the remaining space in the cavity. The encapsulation material within the cavity may also extend into the opening and the via, and cover a majority of the bump along the side and vertical directions. For example, the encapsulation material can be an encapsulation material for changing colors, which contacts an LED chip, a bonding wire, a crystal-bonding material, and the bump in the cavity, and is connected with the wire, the base, and the adhesive layer. Keeping a distance from the dielectric layer, the packaging material can convert the blue light emitted by the LED chip into white light. In this example, the semiconductor chip assembly may include a transparent encapsulation material, which is in contact with the color-changing encapsulation material, the flange layer, the welding pad, and the bonding wire outside the cavity, and is connected to the LED chip. , the crystal-bonding material, the base, and the terminal keep a distance, and cover the color-changing packaging material, the flange layer, and the bonding wire in the first vertical direction. In addition, the encapsulation material for color conversion may include silicone resin and phosphor, and the transparent encapsulation material may include silicone resin but no phosphor.

The semiconductor chip assembly may be a first-level or second-level monocrystalline or polycrystalline device. For example, the semiconductor chip assembly can be a first-level package including a single chip or multiple chips. Alternatively, the semiconductor chip assembly can be a second-level module comprising a single LED package or a plurality of LED packages, wherein each of the LED packages can comprise a single LED chip or a plurality of LED chips.

The present invention provides a method for manufacturing a semiconductor chip assembly, which includes: providing a bump and an overhanging platform; setting an adhesive layer on the overhanging platform, and this step includes inserting the bump into the adhesive layer an opening; disposing a conductive layer on the adhesive layer, this step includes aligning the bump to a through hole of the conductive layer; making the adhesive layer flow between the bump and the conductive layer; curing the adhesive layer; providing a wire including a solder pad, a terminal and a selected portion of the outrigger; providing a heat sink including the bump, a base and a selected portion of the outrigger; disposing a semiconductor element on the bump, wherein the semiconductor element extends into a cavity of the bump; electrically connecting the semiconductor element to the wire; and thermally connecting the semiconductor element to the heat sink.

According to an aspect of the present invention, a method of fabricating a semiconductor chip assembly includes: (1) providing a bump, an overhanging platform, an adhesive layer, and a conductive layer, wherein (a) the bump has a concave The recess is facing a first vertical direction and has an entrance located at the overhanging platform, the protrusion adjoins the overhanging platform and is integrally formed therewith, and the protrusion is along a line with the first A second vertical direction opposite to the vertical direction protrudes vertically from the overhanging platform, simultaneously extends into an opening of the adhesive layer, and aligns with a through hole in the conductive layer, (b) the overhanging platform is perpendicular to the The lateral direction in the vertical direction protrudes from the side of the bump, (c) the adhesive layer is arranged on the overhanging platform, between the overhanging platform and the conductive layer, and is not cured. In addition, (d ) the conductive layer is disposed on the adhesive layer; (2) making the adhesive layer flow into the through hole along the second vertical direction into a gap between the bump and the conductive layer; (3) curing the adhesive layer ; (4) provide a wire, the wire includes a pad, a terminal and a selected portion of the outrigger platform, the selected portion is to keep a distance from the bump; (5) provide a heat sink, the heat dissipation The seat includes the protrusion, a base and a flange layer, wherein (a) the protrusion is adjacent to the base and extends perpendicularly from the base along the first vertical direction, (b) the base is along the The second vertical direction extends from the bump, and (c) the flange layer includes a selected portion of the overhanging platform that adjoins and is integral with the bump, and from the side of the bump (6) setting a semiconductor element on the bump, wherein the semiconductor element extends into the cavity; (7) electrically connecting the semiconductor element to the pad, thereby electrically connecting the semiconductor element to the the terminal; and (8) thermally connecting the semiconductor element to the bump, thereby thermally connecting the semiconductor element to the base.

According to another aspect of the present invention, a method of manufacturing a semiconductor chip assembly includes: (1) providing a bump and an overhanging platform, wherein the bump has a cavity facing a first a vertical direction, and has an entrance located at the overhanging platform, the protrusion is adjacent to and integral with the overhanging platform, and in addition, the protrusion is along a second vertical direction opposite to the first vertical direction. The overhanging platform protrudes vertically, and the overhanging platform protrudes from the side of the protrusion along a side direction perpendicular to the vertical directions; (2) providing an adhesive layer, wherein an opening extends through the adhesive layer; (3) providing a conductive layer, wherein a through hole extends through the conductive layer; (4) disposing the adhesive layer on the overhanging platform, wherein the bump extends into the opening; (5) disposing the conductive layer on the adhesive layer, this step includes aligning the bump to the through hole, wherein the adhesive layer is between the overhanging platform and the conductive layer and is uncured; (6) heating and melting the adhesive layer; (7) making the The overhanging platform and the conductive layer are in contact with each other, whereby the bump moves in the through hole along the second vertical direction, and at the same time, pressure is applied to the melted adhesive layer between the overhanging platform and the conductive layer. forcing the melted adhesive layer to flow into a gap between the bump and the conductive layer in the through hole along the second vertical direction; (8) heating and solidifying the melted adhesive layer, whereby the bump and the overhanging platform mechanically adhered to the conductive layer; (9) providing a wire comprising a pad, a terminal, and selected portions of both the overhanging platform and the conductive layer, the selected portions being in contact with the bump Keep a distance; (10) provide a heat sink, the heat sink includes the bump, a base and a flange layer, wherein (a) the bump is adjacent to the base, and along the first vertical direction from the base the base extends vertically, (b) the base extends perpendicularly from the bump along the second vertical direction and projects laterally from the bump, and (c) the flange layer includes an optional portion of the overhanging platform A fixed portion, the selected portion is adjacent to the bump and integrally formed with it, while protruding from the side of the bump; (11) setting a semiconductor element on the bump, wherein the semiconductor element extends into the cavity; ( 12) electrically connecting the semiconductor element to the pad, thereby electrically connecting the semiconductor element to the terminal; and (13) thermally connecting the semiconductor element to the bump, thereby thermally connecting the semiconductor element to the base .

Disposing the conductive layer may include: separately disposing the conductive layer on the adhesive layer. Alternatively, disposing the conductive layer may include: disposing the conductive layer together with a carrier on the adhesive layer so that the conductive layer is in contact with and interposed between the adhesive layer and the carrier, and then after the adhesive layer is cured, first The carrier is removed, and the wire is provided. Alternatively, arranging the conductive layer may include: arranging the conductive layer and a dielectric layer together on the adhesive layer, so that the conductive layer is kept at a distance from the adhesive layer, and the dielectric layer is in contact with and interposed between the adhesive layer. between the conductive layer and the adhesive layer.

According to another aspect of the present invention, a method of manufacturing a semiconductor chip assembly includes: (1) providing a bump, an overhang platform, an adhesive layer, and a substrate, wherein (a) the bump has a concave The recess is facing a first vertical direction and has an entrance located at the overhanging platform, the protrusion adjoins the overhanging platform and is integrally formed therewith, and the protrusion is along a line with the first A second vertical direction opposite to the vertical direction protrudes vertically from the outrigger platform, and simultaneously extends into an opening of the adhesive layer, and is aligned with a through hole in the substrate, (b) the outrigger platform is perpendicular to the The lateral direction in the vertical direction protrudes from the side of the bump, (c) the adhesive layer is disposed on the overhanging platform, between the overhanging platform and the substrate, and is uncured, and (d) the The substrate is disposed on the adhesive layer, wherein the substrate includes a conductive layer and a dielectric layer, and the dielectric layer is located between the conductive layer and the adhesive layer; (2) making the adhesive layer along the second vertical direction (3) solidify the adhesive layer; (4) provide a wire, which includes a pad, a terminal, a covered through hole, the overhang a selected portion of the platform and a selected portion of the conductive layer, wherein the selected portions are adjacent to the covered through-hole and kept at a distance from the bump, and the covered through-hole is a conductive connection between the pad and the terminal Path; (5) providing a heat sink, the heat sink includes the bump, a base and a flange layer, wherein (a) the bump is adjacent to the base, and along the first vertical direction from the base extending vertically, (b) the base covers the bump in the second vertical direction and protrudes laterally from the bump while including a selected portion of the conductive layer, the selected portion is held with the conductive line distance, and (c) the flange layer includes a selected portion of the overhanging platform, the selected portion is adjacent to the bump and integrally formed with it, and protrudes from the side of the bump; (6) providing a a semiconductor element on the bump, wherein the semiconductor element extends into the cavity; (7) electrically connecting the semiconductor element to the pad, thereby electrically connecting the semiconductor element to the terminal; and (6) thermally connecting The semiconductor element is connected to the bump, thereby thermally connecting the semiconductor element to the base.

According to still another aspect of the present invention, a method of manufacturing a semiconductor chip assembly includes: (1) providing a bump and an overhanging platform, wherein the bump has a cavity facing a first a vertical direction, and has an entrance located at the overhanging platform, the protrusion is adjacent to and integral with the overhanging platform, and in addition, the protrusion is along a second vertical direction opposite to the first vertical direction. The overhanging platform protrudes vertically, and the overhanging platform protrudes from the side of the protrusion along a side direction perpendicular to the vertical directions; (2) providing an adhesive layer, wherein an opening extends through the adhesive layer; ( 3) providing a substrate comprising a conductive layer and a dielectric layer, wherein a through hole extends through the substrate; (4) disposing the adhesive layer on the overhanging platform, this step includes inserting the bump into the opening, wherein The bump extends through the opening; (5) disposing the substrate on the adhesive layer, this step includes inserting the bump into the through hole, wherein the bump extends into the through hole, the adhesive layer is located on the overhanging The platform and the dielectric layer are not solidified, and the dielectric layer is located between the conductive layer and the adhesive layer; (6) heating and melting the adhesive layer; (7) making the overhanging platform and the substrate close to each other, Thereby causing the bump to move in the through hole along the second vertical direction, while applying pressure to the melted adhesive layer between the overhanging platform and the substrate, and the pressure forces the melted adhesive layer to flow in the second vertical direction A gap between the bump and the substrate in the through hole; (8) heating and solidifying the melted adhesive layer, thereby mechanically adhering the bump and the overhanging platform to the substrate; (9) providing a covering perforation, the covered perforation extends through the outrigger platform, the adhesive layer, the dielectric layer and the conductive layer; (10) providing a pad, a terminal, a base and a flange layer; (11) providing a a wire comprising the pad, the terminal, the covered through-hole, a selected portion of the overhanging platform, and a selected portion of the conductive layer, wherein the selected portions are adjacent to the covered through-hole and connected to the bump block, and the coated through hole is a conductive path between the pad and the terminal; (12) providing a heat sink, the heat sink includes the bump, the base and the flange layer, wherein (a) The protrusion adjoins the base and extends perpendicularly from the base along the first vertical direction, (b) the base covers the protrusion in the second vertical direction and extends from the side of the protrusion along the side directions and (c) the flange layer includes a selected portion of the overhanging platform, the selected portion adjacent to The bump is integrally formed with it, while protruding from the side of the bump; (13) setting a semiconductor element on the bump, wherein the semiconductor element extends into the cavity; (14) electrically connecting the semiconductor element to the pad, thereby electrically connecting the semiconductor element to the terminal; and (15) thermally connecting the semiconductor element to the bump, thereby thermally connecting the semiconductor element to the base.

Providing the bump may include mechanically stamping a metal plate, thereby forming the bump and the cavity in the bump on the metal plate. In this example, the bump is a stamped portion of the metal plate and the overhanging platform is an unstamped portion of the metal plate.

Providing the adhesive layer may include: providing a film of uncured epoxy resin. Flowing the adhesive layer may include: melting the uncured epoxy resin; and squeezing the uncured epoxy resin between the outrigger platform and the substrate. Curing the adhesive layer may include: curing the melted uncured epoxy resin.

Providing the solder pad may include removing selected portions of the overhanging platform after curing the adhesive layer. The removing may include wet chemical etching the overhanging mesa using a patterned etch stop that defines the bonding pad such that the bonding pad includes a selected portion of the outrigging mesa.

Providing the flange layer may include removing selected portions of the overhanging platform after curing the adhesive layer. The removing can include wet chemical etching the overhanging platform using a patterned etch stop layer that defines the ledge layer such that the ledge layer includes a selected portion of the overhanging platform.

Providing the terminal may include removing selected portions of the conductive layer after curing the adhesive layer. The removing can include wet chemical etching the conductive layer with a patterned etch stop defining the terminal such that the terminal includes a selected portion of the conductive layer.

Providing the base may include removing selected portions of the conductive layer after curing the adhesive layer. The removing can include wet chemical etching the conductive layer with a patterned etch stop defining the pedestal such that the pedestal includes a selected portion of the conductive layer.

Providing the pad and the flange layer can include removing selected portions of the overhanging mesa using a patterned etch stop layer that defines the pad and the flange layer. In this way, the bonding pad and the flange layer can be formed simultaneously in the same wet chemical etching step using the same patterned etch stop layer. Likewise, providing the terminal and the pedestal may include removing selected portions of the conductive layer using a patterned etch stop that defines the terminal and the pedestal. In this way, the terminal and the pedestal can be formed simultaneously in the same wet chemical etching step using the same patterned etch stop layer.

The pads may be formed before, after, or during the formation of the terminals. Therefore, the pad and the terminal can be formed simultaneously by using different patterned etch stop layers in the same wet chemical etching step, or successively formed by using different patterned etch stop layers. Likewise, the flange layer may be formed before, after, or during formation of the base. Therefore, the flange layer and the base can be formed simultaneously by using different patterned etch stop layers in the same wet chemical etching step, or formed successively by using different patterned etch stop layers. Likewise, the solder pad, the terminal, the flange layer and the base can be formed simultaneously or successively.

Providing the terminal may include: after curing the adhesive layer, grinding the bump, the adhesive layer, and the conductive layer so that the bump, the adhesive layer, and the conductive layer are positioned on a side facing the second vertical direction. surfaces laterally flush with each other; and then removing selected portions of the conductive layer using a patterned etch stop defining the terminal such that the terminal includes a selected portion of the conductive layer. The grinding may include: grinding the adhesive layer without grinding the bump; and then grinding the bump, the adhesive layer and the conductive layer. The removing may include wet chemical etching the conductive layer with a patterned etch stop defining the terminal.

Providing the pad may include: after grinding, depositing conductive metal on the bump and the overhanging platform to form a coating; then removing selected portions of both the overhanging platform and the coating to enable The pad includes selected portions of both the overhanging platform and the cladding layer. Depositing a conductive metal to form the coating layer may include: electrolessly coating a thin coating layer on the bump and the overhanging platform; and then electroplating a thick coating layer on the thin coating layer . The removing may include wet chemical etching the overhanging mesa and the cladding layer using a patterned etch stop layer defining the bonding pad.

Providing the terminal may include: after grinding, depositing conductive metal on the bump, the adhesive layer and the conductive layer to form a covering layer; then removing selected portions of both the conductive layer and the covering layer to The terminal is made to include selected portions of both the conductive layer and the coating layer. Depositing conductive metal to form the coating layer may include: electrolessly coating a thin coating layer on the bump, the adhesive layer, and the conductive layer; and then electroplating a thick coating layer on the thin coating layer. on the coating. The removing may include wet chemical etching the conductive layer and the coating layer using a patterned etch stop layer that defines the terminal.

Providing the wire may include: providing the pad, the terminal, and a covered through-hole, wherein the covered through-hole is located on a conductive path between the pad and the terminal. The solder pad and the terminal can be formed first, and then the covered through hole is formed, and the covered through hole extends through the overhanging platform, the adhesive layer, the dielectric layer and the conductive layer.

Providing the pad, the flange layer, and the coated via may include: drilling through the overhanging platform, the dielectric layer, the adhesive layer, and the conductive layer to form a hole after curing the adhesive layer; A conductive metal is deposited on the bump, the protruding platform, the dielectric layer, the adhesive layer and the conductive layer and in the hole to form a covering layer, wherein the covering layer forms a first covering layer, and the first covering layer covering the bump and the overhanging platform in the first vertical direction, while covering the coated through-hole in the hole; then forming a patterned etch on the first coating layer to define the pad and the flange layer resisting layer; using the patterned etching resisting layer to etch the overhanging platform and the first coating layer to form a pattern defined by the patterned etching resisting layer; and removing the patterned etching resisting layer.

Providing the base, the terminal, and the coated through hole may include: after curing the adhesive layer, drilling through the outrigger platform, the dielectric layer, the adhesive layer, and the conductive layer to form a hole; Deposit conductive metal on the platform, the dielectric layer, the adhesive layer and the conductive layer and in the hole to form a coating layer, wherein the coating layer forms a second coating layer, and the second coating layer is in the second vertical direction covering the bump, the adhesive layer and the conductive layer, and simultaneously covering the covered through hole in the hole; then forming a patterned etch stop layer on the second covering layer that can define the base and the terminal; using the The patterned etch stop layer etches the conductive layer and the second coating layer to form a pattern defined by the patterned etch stop layer; and removes the patterned etch stop layer.

Providing the pedestal, the flange layer, the solder pad, the terminal, and the coated via may include: after curing the adhesive layer, drilling through the overhanging platform, the dielectric layer, the adhesive layer, and the conductive layer to forming a hole; then depositing conductive metal on the bump, the outrigger platform, the dielectric layer, the adhesive layer, the conductive layer and in the hole to form a covering layer, wherein the covering layer forms a first covering layer layer and a second coating layer, the first coating layer covers the bump and the outrigger platform in the first vertical direction, and the second coating layer covers the bump, the adhesive layer and the outrigger platform in the second vertical direction Conductive layer, while covering the coated through hole in the hole; then forming a patterned etch stop layer on the first cover layer that can define the pad and the flange layer, using the patterned etch stop layer to etch the outer surface Extending the platform and the first cladding layer to form a pattern defined by the patterned etch resist layer; forming a patterned etch resist layer on the second cladding layer that can define the base and the terminal, using the pattern Etching the conductive layer and the second covering layer to form a pattern defined by the patterned etch resist layer; and removing the patterned etch resist layers. In addition, etching the overhanging platform and the first cladding layer may include: exposing the adhesive layer in the first vertical direction, but not exposing the dielectric layer in the first vertical direction. Etching the conductive layer and the second cladding layer may include: exposing the dielectric layer in the second vertical direction, but not exposing the adhesive layer in the second vertical direction.

Making the adhesive layer flow may include: filling the gap with the adhesive layer. Making the adhesive layer flow may also include: pressing the adhesive layer, making it pass through the gap, and extending beyond the bump and the conductive layer along the second vertical direction, and finally reaching both the bump and the conductive layer. wherein the surface portions are adjacent to the notch and face the second vertical direction, therefore, the adhesive layer extends to the outside of the bump and the conductive layer along the second vertical direction.

Curing the adhesive layer may include: mechanically combining the bump and the outrigger platform with the substrate.

Disposing the semiconductor device may include: providing a die-bonding material between a semiconductor chip (such as an LED chip) and the bump. Electrically connecting the semiconductor device may include: providing a bonding wire between the chip and the bonding pad. Thermally connecting the semiconductor device may include: providing the die-bonding material between the chip and the bump.

The semiconductor element can be encapsulated in the following manner: deposit a liquid encapsulation material in the cavity, make it fill up the remaining space in the cavity, and cover the semiconductor element in the first vertical direction, and then harden the encapsulation material. Additionally, the cavity may provide a dam to limit the lateral extent of the encapsulating material as the encapsulating material extends out of the cavity in the first vertical direction.

The adhesive layer can contact the bump, the pedestal, the flange layer, the pad, the covered through hole and the dielectric layer, and cover the substrate and the terminal in the first vertical direction, and in the second Covering the solder pad and the flange layer in the vertical direction, covering and surrounding the bump in the side direction, and extending to the semiconductor chip assembly formed by separating it from other semiconductor chip assemblies produced in the same batch after the semiconductor chip assembly is manufactured. peripheral edge.

The base may cover the semiconductor device, the bump and the flange layer in the second vertical direction but not cover the adhesive layer, the dielectric layer, the terminal or the coated through hole. The base can support the base plate and the adhesive layer, and keep a distance from the peripheral edge of the semiconductor chip set body after the semiconductor chip set body is manufactured and separated from other semiconductor chip set bodies produced in the same batch.

As used herein, the term "adjacent" means that the elements are integrated (form a single entity) or contact each other (without spacing or separation from each other). For example, the bumps adjoin the pedestal and flange layers, but not the dielectric layer.

The term "overlapping" means lying above and extending within the perimeter of an underlying element. "Overlapping" includes extending inside, outside, or within the perimeter. For example, in the state where the cavity faces upwards, the semiconductor element in this case overlaps the bump, because an imaginary vertical line can run through the semiconductor element and the bump at the same time, regardless of whether there is a gap between the semiconductor element and the bump. There is another element (such as a die-bonding material) that is also penetrated by the imaginary vertical line, and regardless of whether there is another imaginary vertical line that only penetrates the bump and does not penetrate the semiconductor element (that is, it is located outside the periphery of the semiconductor element) ). Likewise, the bump is overlapped by the base, the pad is overlapped by the adhesive layer, and the base is overlapped by the bump. Also, "overlapping" is synonymous with "on top", and "overlapped" is synonymous with "below".

The term "contact" means direct contact. For example, the dielectric layer contacts the terminals but not the bumps.

The term "covering" means complete covering in a vertical and/or lateral direction. For example, if the pedestal extends laterally beyond the via and contacts the dielectric layer with the cavity facing up, the pedestal covers the bump from below, but the bump does not cover the pedestal from above .

The word "layer" includes a layer with a pattern or without a pattern. For example, when the substrate is placed on the adhesive layer, the conductive layer can be a blank plate with no pattern on the dielectric layer; circuit pattern. Additionally, "layer" may include multiple laminated layers.

The term "pad" when used in conjunction with a wire means a connection area used to connect and/or bond to an external connection medium (such as solder or wire bonding) that electrically connects the wire to the semiconductor element.

The term "terminal" when used in conjunction with a wire refers to a connection area that contacts and/or engages an external connection medium (such as solder or wire bonding) that electrically connects the wire to the next An external device (such as a printed circuit board or a wire connected thereto) associated with a semiconductor chip assembly.

The term "coated via" when used in conjunction with a wire refers to an electrical interconnect structure formed in a hole by coating. For example, a covered through-hole can remain intact in its corresponding hole and keep a distance from the peripheral edge of the semiconductor chip assembly, or it can be cleaved or trimmed into a trench in a subsequent process, so that the remaining part of the covered through-hole The part is located in the trench at the peripheral edge of the body of the semiconductor chipset; the presence of the covered through-hole is independent of which of the above-mentioned configurations is adopted.

The terms "opening", "through hole" and "hole" mean a through hole. For example, after the protrusion is inserted into the opening of the adhesive layer with the recess facing downward, it is exposed from the adhesive layer facing upward. Similarly, after the bump is inserted into the through hole of the substrate, it is exposed from the substrate facing upward.

The term "interposition" refers to relative movement between elements. For example, "inserting the bump into the through hole" includes: the bump is fixed and moves from the substrate toward the outrigger platform; the substrate is fixed and the bump moves toward the substrate; and the bump and the substrate are in contact with each other. For another example, “inserting (or extending) the bump into the through hole” includes: the bump penetrates (into and out of) the through hole; and the bump is inserted into but not penetrated (into but not out of) the through hole.

The phrase "close to each other" also refers to relative movement between elements. For example, "the overhanging platform and the substrate are close to each other" includes: the outrigger platform is fixed and moves from the substrate to the outrigger platform; the substrate is fixed and the outrigger platform moves toward the substrate; and the outrigger platform and the substrate are close to each other .

The term "alignment" refers to the relative position between components. For example, when the adhesive layer has been placed on the overhanging platform, the substrate has been placed on the adhesive layer, the bump has been inserted and aligned with the opening, and the via has been aligned with the opening, regardless of whether the bump is inserted into the via or under the via And keeping a distance therefrom, the bumps are all aligned with the through holes.

The term "disposed on" includes both contact and non-contact with a single or multiple support elements. For example, a semiconductor device is disposed on a bump, regardless of whether the semiconductor device actually contacts the bump or is separated from the bump by a die-bonding material.

The phrase "adhesive layer...in the gap" means the adhesive layer located in the gap. For example, "the adhesive layer extends across the dielectric layer in the gap" means that the adhesive layer within the gap extends across the dielectric layer. Likewise, "the adhesive layer is in contact with the notch and is between the bump and the dielectric layer" means that the adhesive layer in the notch is in contact with and interposed between the bump on the inner wall of the notch and the dielectric layer on the outer wall of the notch.

The phrase "the base extends laterally from the bump" means that the base extends laterally adjacent to the bump. For example, in the state where the recess is facing upwards, the base extends laterally from the bump and thus contacts the adhesive layer. Blocks are irrelevant. Likewise, if the base and the bump occupy the same space at the bottom of the bump, the base does not extend laterally beyond the bump.

The term "above" means extending upward and includes adjoining and non-adjacent elements as well as overlapping and non-overlapping elements. For example, in a state where the recess is facing upwards, the protrusion extends above the base, and at the same time adjoins, overlaps and protrudes from the base. Likewise, the bump may extend above the dielectric layer even if it does not adjoin or overlap the dielectric layer.

The term "beneath" means extending downward and includes adjoining and non-adjacent elements as well as overlapping and non-overlapping elements. For example, in a state where the recess is facing upward, the base extends below the protrusion, adjoins the protrusion, is overlapped by the protrusion, and protrudes downward from the protrusion. Likewise, the terminals may extend below the flange layer even if they are not adjacent to or overlapped by the flange layer.

The "first vertical direction" and "second vertical direction" do not depend on the orientation of the semiconductor chip assembly body (or heat conduction plate), and those who are familiar with this technology can easily understand the actual directions they point to. For example, the bump vertically extends out of the base along the first vertical direction, and extends vertically out of the flange layer along the second vertical direction, which is related to whether the semiconductor chip assembly body is inverted and/or whether the semiconductor chip assembly body is disposed on A heatsink has nothing to do with it. Likewise, the flange layer protrudes "laterally" from the bump along a lateral plane, regardless of whether the semiconductor chip assembly body is inverted, rotated, or tilted. Thus, the first and second vertical directions are opposite each other and perpendicular to the lateral direction, and furthermore, the laterally aligned elements are coplanar with each other in a lateral plane perpendicular to the first and second vertical directions. Furthermore, when the recess is upward, the first vertical direction is the upward direction, and the second vertical direction is the downward direction; when the recess is downward, the first vertical direction is the downward direction, and the second vertical direction is the upward direction.

The invention has several advantages. The heat sink can provide excellent heat dissipation effect and prevent heat energy from flowing through the adhesive layer. Therefore, the adhesive layer can be a low-cost dielectric with low thermal conductivity and is not prone to delamination. The bump and the flange layer can be integrated to improve reliability. The bump can have a tapered side wall and a highly reflective surface layer, so as to collect the light emitted by an LED chip disposed in the cavity of the bump, thereby increasing the light output. In addition, since the cavity can provide a well-defined space for a color-converting encapsulating material to be deposited on the LED chip, the amount of the color-converting encapsulating material in the cavity is not only small but also fixed, thus, It can not only improve the optical performance, but also reduce the cost. For improved reliability, the submount can include a selected portion of the conductive layer overlying the dielectric layer. The adhesive layer can be located between the bump and the substrate, between the base and the substrate, and between the flange layer and the substrate to provide a strong mechanical connection between the heat sink and the substrate. The wires can form simple circuit patterns to provide signal routing, or form complex circuit patterns to realize flexible multi-layer signal routing. The wire can also provide vertical signal routing between the pad and the terminal using a coated via extending through the adhesive layer and the dielectric layer. In addition, the covered through-hole can be formed after the adhesive layer is solidified, and maintain a hollow tube shape, or be split at the peripheral edge of the semiconductor chip assembly body, so that the solder reflowed to the surface of the terminal can be wetted and flow into the covered through-hole In order to avoid the formation of voids in the solder due to the coating through hole being filled with the adhesive layer or other non-wettable insulating materials, this design helps to improve reliability. The base can provide mechanical support for the substrate and prevent it from being bent and deformed. The semiconductor chip assembly can be manufactured by a low-temperature process, which not only reduces stress, but also improves reliability. The semiconductor chip assembly body can also be manufactured using a high control process that can be easily implemented by circuit board, lead frame and tape and reel manufacturing plants.

The above and other features and advantages of the present invention will be further illustrated by various embodiments below.

Description of drawings

1 and 2 are cross-sectional views illustrating a method for fabricating a bump and an overhang platform in an embodiment of the present invention;

Fig. 3 and Fig. 4 are respectively the top view and the bottom view of Fig. 2;

5 and 6 are cross-sectional views illustrating a method for making an adhesive layer in an embodiment of the present invention;

Fig. 7 and Fig. 8 are respectively the top view and the bottom view of Fig. 6;

9 and 10 are cross-sectional views illustrating a method for fabricating a substrate in an embodiment of the present invention;

Figure 11 and Figure 12 are the top view and the bottom view of Figure 10 respectively;

13 to 25 are cross-sectional views illustrating a method for manufacturing a heat conducting plate in an embodiment of the present invention;

Fig. 26 and Fig. 27 are respectively the top view and the bottom view of Fig. 25;

Fig. 28, Fig. 29 and Fig. 30 are respectively the sectional view, top view and bottom view of a heat conduction plate in an embodiment of the present invention, the peripheral edge of the heat conduction plate is provided with coating perforation;

Fig. 31, Fig. 32 and Fig. 33 are respectively the sectional view, top view and bottom view of a heat conduction plate in an embodiment of the present invention, the protrusion of the heat conduction plate and the base have the same spatial range;

Fig. 34, Fig. 35 and Fig. 36 are respectively a sectional view, a top view and a bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate has a thickened base and terminals;

Fig. 37, Fig. 38 and Fig. 39 are respectively the sectional view, top view and bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate and the lower surface respectively have a layer of solder resist green paint;

Fig. 40, Fig. 41 and Fig. 42 are respectively the sectional view, top view and bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate has a layer of embedded solder resist green paint;

Fig. 43, Fig. 44 and Fig. 45 are respectively a sectional view, a top view and a bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate can provide horizontal signal routing;

Fig. 46, Fig. 47 and Fig. 48 are respectively a sectional view, a top view and a bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate has a raised edge;

Fig. 49, Fig. 50 and Fig. 51 are respectively a sectional view, a top view and a bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate, a semiconductor element and a packaging material;

Fig. 52, Fig. 53 and Fig. 54 are respectively the sectional view, top view and bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate, a semiconductor element, a packaging material and a lens ;

Fig. 55, Fig. 56 and Fig. 57 are respectively the sectional view, top view and bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate, a semiconductor element and double-layer packaging materials;

Fig. 58, Fig. 59 and Fig. 60 are respectively the sectional view, the top view and the bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate with a raised edge, a semiconductor element and a double layer packaging materials;

Fig. 61, Fig. 62 and Fig. 63 are respectively the sectional view, top view and bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate with raised edges, a semiconductor element, and a package material and a cover;

Fig. 64, Fig. 65 and Fig. 66 are respectively the sectional view, top view and bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate with raised edges, a semiconductor element and an upper build.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments. The embodiments described herein are for illustration purposes, and the related elements or steps of the present technology are simplified or omitted to avoid obscuring the characteristics of the present invention. Likewise, elements and reference numerals that are repeated or not necessary in the drawings may be omitted for clarity of the drawings.

1 and 2 are cross-sectional views illustrating a method for manufacturing a bump and an overhanging platform in an embodiment of the present invention, and FIGS. 3 and 4 are a top view and a bottom view of FIG. 2, respectively.

FIG. 1 is a cross-sectional view of a metal plate 10 including opposing major surfaces 12 and 14 . The illustrated metal plate 10 is a copper plate having a thickness of 70 microns. Copper has the advantages of high thermal conductivity, good bonding and low cost. Metal plate 10 may be made of various metals such as copper, aluminum, iron-nickel alloy 42, iron, nickel, silver, gold, mixtures thereof, and alloys thereof.

2 , 3 and 4 are respectively a cross-sectional view, a top view and a bottom view of the metal plate 10 after forming the bump 16 , the outrigger platform 18 and the recess 20 . The protrusions 16 and the recesses 20 are formed by stamping the metal plate 10 mechanically. Therefore, the bump 16 is the part of the metal plate 10 that is stamped, and the overhanging platform 18 is the part of the metal plate 10 that is not stamped.

The protruding block 16 is adjacent to the extended platform 18 , integrally formed with the extended platform 18 , and extends from the extended platform 18 in a downward direction. The bump 16 includes bent corners 22 and 24 , tapered sidewalls 26 and a bottom plate 28 . The bent corners 22 and 24 are bent due to the stamping operation. The bent corner 22 is adjacent to the overhanging platform 18 and the tapered side wall 26 , while the bent corner 24 is adjacent to the tapered side wall 26 and the floor 28 . The tapered sidewall 26 expands in an upward direction, and the bottom plate 28 extends in a lateral direction (eg, left and right) perpendicular to the aforementioned upward and downward directions. Therefore, the protrusion 16 is in the shape of a flat-topped cone (similar to a frustum), and its diameter decreases downwards from the overhanging platform 18 toward the bottom plate 28 , that is to say, increases upwards from the bottom plate 28 towards the overhanging platform 18 . The height of bump 16 (relative to outrigger 18 ) is 250 microns, the diameter at outrigger 18 is 1500 microns, and the diameter at base 28 is 1000 microns. Additionally, the bumps 16 have an inconsistent thickness due to the stamping operation. For example, the elongated tapered side walls 26 are thinner than the base plate 28 due to the stamping. For ease of illustration, the bumps 16 have a uniform thickness in the figures.

The flat protruding platform 18 protrudes from the bump 16 along the lateral direction, and has a thickness of 70 microns.

The pocket 20 is facing upwards and extends into the bump 16 and is covered by the bump 16 from below. The pocket 20 has an entrance at the overhanging platform 18 . Furthermore, the shape of the recess 20 corresponds to the bump 16 . Therefore, the recess 20 is also in the shape of a flat-topped cone (similar to a frustum), and its diameter decreases downwards from its entrance at the overhanging platform 18 towards the bottom plate 28, that is to say from the bottom plate 28 towards its outer position. The entrance of the extension platform 18 increases upwards. Furthermore, the cavity 20 covers most of the bump 16 along the vertical and lateral directions, and the depth of the cavity 20 is 250 micrometers.

5 and 6 are cross-sectional views illustrating a method for making an adhesive layer in an embodiment of the present invention. 7 and 8 are respectively a top view and a bottom view drawn according to FIG. 6 .

5 is a cross-sectional view of the adhesive layer 30, wherein the adhesive layer 30 is a film of B-stage uncured epoxy resin, which is an uncured and patternless sheet with a thickness of 150 microns.

The adhesive layer 30 can be various dielectric films or films made of various organic or inorganic electrical insulators. For example, the adhesive layer 30 may initially be a film in which a resin-type thermosetting epoxy resin is impregnated into a reinforcing material and then partially cured to a medium-term stage. The epoxy resin may be FR-4, but other epoxy resins such as multifunctional and bismaleimide-triazine (BT) resins may also be used. Cyanate esters, polyimides, and polytetrafluoroethylene (PTFE) are also useful epoxy resins in certain applications. The reinforcing material can be electronic grade glass, or other reinforcing materials, such as high-strength glass, low-permeability glass, quartz, kevlar aramid and paper. The reinforcing material may also be woven, non-woven or non-directional microfibres. Fillers such as silicon (powdered fused silica) can be added to the film to improve thermal conductivity, thermal shock resistance, and thermal expansion matching. Commercially available prepregs can be used, such as the SPEEDBOARD C film of W.L. Gore & Associates in Oakley, Wisconsin, USA, as an example.

FIG. 6 , FIG. 7 and FIG. 8 are respectively a cross-sectional view, a top view and a bottom view of the adhesive layer 30 having the opening 32 . The opening 32 is a window which penetrates the adhesive layer 30 and has a diameter of 1550 microns. The opening 32 is formed by mechanically drilling through the film, but can also be made by other techniques, such as punching and punching.

9 and 10 are cross-sectional views illustrating a method for manufacturing a substrate in an embodiment of the present invention, while FIGS. 11 and 12 are top and bottom views drawn according to FIG. 10 , respectively.

FIG. 9 is a cross-sectional view of the substrate 34 . The substrate 34 includes a conductive layer 36 and a dielectric layer 38 . Conductive layer 36 is an electrical conductor that contacts dielectric layer 38 and extends over dielectric layer 38 . The dielectric layer 38 is an electrical insulator. For example, the conductive layer 36 is an unpatterned copper plate with a thickness of 30 microns, and the dielectric layer 38 is an epoxy resin plate with a thickness of 120 microns.

10 , 11 and 12 are respectively a cross-sectional view, a top view and a bottom view of the substrate 34 having the through hole 40 . The via 40 is a window that penetrates the substrate 34 and has a diameter of 1550 microns. The via hole 40 is formed by mechanically drilling through the conductive layer 36 and the dielectric layer 38 , but it can also be made by other techniques, such as stamping and stamping. The opening 32 has the same diameter as the through hole 40 . In addition, the opening 32 and the through hole 40 can be formed in the same way on the same drill floor with the same drill, or formed in the same way on the same punch with the same punch.

The substrate 34 is shown here as a laminated structure, but the substrate 34 may also be other electrically connected objects, such as a ceramic board or a printed circuit board. Likewise, the substrate 34 may further include a plurality of layers embedded with circuits.

13 to 25 are cross-sectional views illustrating a method for manufacturing a heat conducting plate according to an embodiment of the present invention. The heat conducting plate includes a bump 16 , an adhesive layer 30 and a substrate 34 . 26 and 27 are a top view and a bottom view of FIG. 25, respectively.

The structures in FIGS. 13 and 14 are in an inverted state with the cavity 20 facing down, so that the adhesive layer 30 and the substrate 34 can be placed on the overhanging platform 18 by gravity. The structure in Fig. 15 to Fig. 17 still keeps the recess downward. The structures in FIGS. 18 to 27 are turned over again to the state of the recesses as shown in FIGS. 1 to 4 . Briefly, the pocket 20 faces downwards in FIGS. 13-17 and upwards in FIGS. 18-27. Despite this, the relative orientation of the structure has not changed. Regardless of whether the structure is inverted, rotated or tilted, the cavity 20 always faces a first vertical direction and is covered by the bump 16 in a second vertical direction. Likewise, regardless of whether the structure is inverted, rotated or tilted, the bumps 16 extend out of the base plate 34 along the first vertical direction, and out of the overhang platform 18 along the second vertical direction. Therefore, the first and second perpendicular directions are directions relative to the structure, always opposite to each other, and always perpendicular to the aforementioned side directions.

FIG. 13 is a cross-sectional view of the adhesive layer 30 disposed on the overhanging platform 18 . The adhesive layer 30 is lowered onto the overhanging platform 18 , so that the bump 16 is inserted upwards and passes through the opening 32 , and finally the adhesive layer 30 is contacted and positioned on the overhanging platform 18 . Preferably, the protrusion 16 is aligned with the opening 32 after being inserted and penetrated through the opening 32 and is located in the center of the opening 32 without contacting the adhesive layer 30 .

In the structure shown in FIG. 14 , the substrate 34 is disposed on the adhesive layer 30 . The substrate 34 is lowered onto the adhesive layer 30 , so that the bump 16 is inserted upward into the through hole 40 , and finally the substrate 34 is contacted and positioned on the adhesive layer 30 .

The protrusion 16 is aligned with the through hole 40 after being inserted into (but not penetrated through) the through hole 40 and is located in the center of the through hole 40 without contacting the substrate 34 . Therefore, the notch 42 is located in the through hole 40 and interposed between the bump 16 and the substrate 34 . The cutout 42 laterally surrounds the projection 16 and is at the same time surrounded laterally by the base plate 34 . In addition, the opening 32 and the through hole 40 are aligned with each other and have the same diameter.

At this time, the substrate 34 is disposed on and in contact with the adhesive layer 30 , and extends above the adhesive layer 30 . After the bump 16 extends through the opening 32 , enters the via 40 and reaches the dielectric layer 38 . The bump 16 is 50 microns lower than the top surface of the conductive layer 36 and is exposed upward through the through hole 40 . The adhesive layer 30 is in contact with and interposed between the outrigger platform 18 and the substrate 34 . Adhesive layer 30 contacts dielectric layer 38 but is spaced from conductive layer 36 . At this stage, the adhesive layer 30 is still a B-stage film of uncured epoxy resin, and the gap 42 is filled with air.

FIG. 15 shows that the adhesive layer 30 flows into the gap 42 after being heated and pressed. In this figure, the method of forcing the adhesive layer 30 to flow into the gap 42 is to exert downward pressure on the conductive layer 36 and/or apply upward pressure to the overhanging platform 18, that is to say, press the overhanging platform 18 and the substrate 34 relative to each other. , so as to apply pressure to the adhesive layer 30; at the same time, the adhesive layer 30 is also heated. The heated adhesive layer 30 can be arbitrarily shaped under pressure. Therefore, after being squeezed, the adhesive layer 30 between the overhanging platform 18 and the substrate 34 changes its original shape and flows upward into the notch 42 . The overhanging platform 18 and the substrate 34 continue to be pressed against each other until the adhesive layer 30 fills the gap 42 . In addition, after the gap between the overhanging platform 18 and the substrate 34 is narrowed, the adhesive layer 30 still fills up the narrowed gap.

For example, the outrigger platform 18 and the conductive layer 36 can be disposed between the upper and lower press tables (not shown) of a laminating machine. In addition, an upper baffle and an upper buffer paper (not shown) can be sandwiched between the conductive layer 36 and the upper pressing table, and a lower baffle and a lower buffer paper (not shown) can be sandwiched between the overhanging platform 18 Between the pressing table. From top to bottom, the laminated body thus constituted is an upper press table, an upper baffle plate, an upper buffer paper, a base plate 34, an adhesive layer 30, an overhanging platform 18, a lower buffer paper, a lower baffle plate and a lower press table. In addition, tool pins (not shown) extending upwardly from the down table and through alignment holes (not shown) in the outrigger platform 18 can be used to position the laminate on the down table.

Then, the upper and lower pressing tables are heated and mutually pushed, thereby heating and pressing the adhesive layer 30 . The baffle can dissipate the heat of the pressing table, so that the heat is evenly applied to the outrigger platform 18 , the substrate 34 and even the adhesive layer 30 . The buffer paper disperses the pressure of the pressing table, so that the pressure is evenly applied to the outrigger platform 18 , the substrate 34 and even the adhesive layer 30 . Initially, the dielectric layer 38 contacts and is pressed against the adhesive layer 30 . As the pressing table continues to operate and heat, the adhesive layer 30 between the outrigger platform 18 and the substrate 34 is squeezed and begins to melt, thus flowing upward into the notch 42 and reaching the conductive layer 36 after passing through the dielectric layer 38 . For example, after the uncured epoxy resin is heated and melted, it is squeezed into the gap 42 by pressure, but the reinforcing material and the filler remain between the overhanging platform 18 and the base plate 34 . The speed of the adhesive layer 30 rising in the through hole 40 is higher than that of the bump 16 , and finally fills the gap 42 . The adhesive layer 30 also rises to a position slightly higher than the notch 42 , and overflows to the top surface of the bump 16 and the top surface of the conductive layer 36 adjacent to the notch 42 before the pressing platform stops. This can happen if the film thickness is slightly larger than necessary. In this way, the adhesive layer 30 forms a covering thin layer on the top surface of the bump 16 and the top surface of the conductive layer 36 . The press platform stops moving after touching the bump 16 , but continues to heat the adhesive layer 30 .

The direction of the upward flow of the adhesive layer 30 in the gap 42 is shown by the upward thick arrow in the figure, and the upward movement of the bump 16 and the overhanging platform 18 relative to the substrate 34 is shown by the upward thin arrow, and the substrate 34 is relative to the raised arrow. The downward movement of block 16 and outrigger platform 18 is then shown by the downward thin arrow.

The adhesive layer 30 in FIG. 16 has been cured.

For example, after the pressing table stops moving, it still continues to clamp the protrusion 16 and the outrigger platform 18 and supply heat, thereby converting the melted B-stage epoxy resin into a C-stage solidified or C-stage epoxy resin. hardened epoxy resin. Thus, the epoxy is cured in a manner similar to existing multilayer laminations. After the epoxy has cured, the press table separates to allow the structure to be removed from the press.

The cured adhesive layer 30 can provide a strong mechanical connection between the bump 16 and the substrate 34 and between the outrigger platform 18 and the substrate 34 . The adhesive layer 30 can withstand general operating pressure without deformation and damage, and only temporarily distorts under excessive pressure. Furthermore, the adhesive layer 30 can absorb the thermal expansion mismatch between the bump 16 and the substrate 34 and between the outrigger platform 18 and the substrate 34 .

At this stage, the bump 16 is substantially coplanar with the conductive layer 36 , and the adhesive layer 30 extends to the top surface of the conductive layer 36 facing upward. For example, the thickness of the adhesive layer 30 between the overhanging platform 18 and the dielectric layer 38 is 100 microns, which is 50 microns less than its initial thickness of 150 microns; that is to say, the bump 16 is raised by 50 microns relative to the substrate 34 in the through hole 40, The substrate 34 is lowered by 50 microns relative to the bump 16 . The height 250 microns of the bump 16 is substantially equal to the combined height of the conductive layer 36 (30 microns), the dielectric layer 38 (120 microns) and the underlying adhesive layer 30 (100 microns). In addition, the bump 16 is still located at the center of the opening 32 and the through hole 40 and keeps a distance from the substrate 34 , while the adhesive layer 30 fills the space between the protruding platform 18 and the substrate 34 and fills the gap 42 . For example, the width of the notch 42 (ie, the adhesive layer 30 between the bump 16 and the substrate 34 ) at the bottom plate 28 is 275 μm ((1550−1000)/2). The adhesive layer 30 extends across the dielectric layer 38 within the gap 42 . In other words, the adhesive layer 30 in the notch 42 is the thickness of the dielectric layer 38 extending in the upward and downward directions and spanning the outer sidewall of the notch 42 . Adhesive layer 30 also includes a thin top portion above notch 42 that contacts the top surface of bump 16 and the top surface of conductive layer 36 and extends 10 microns above bump 16 .

In the structure shown in FIG. 17 , the bumps 16 , the tops of the adhesive layer 30 and the conductive layer 36 have been removed.

The tops of the bumps 16, the adhesive layer 30, and the conductive layer 36 are removed by grinding, for example, using a rotating diamond wheel and distilled water to treat the top of the structure. Initially, the diamond grinding wheel only removes the adhesive layer 30 . With continuous grinding, the adhesive layer 30 becomes thinner due to the downward movement of the ground surface. The diamond grinding wheel will eventually contact the bumps 16 and the conductive layer 36 (not necessarily at the same time), thus beginning to grind the bumps 16 and the conductive layer 36 . After continuous grinding, the bumps 16 , the adhesive layer 30 and the conductive layer 36 all become thinner due to the downward movement of the ground surface. Grinding continues until the desired thickness is removed. The structure was then rinsed with distilled water to remove dirt.

The grinding step above grinds away the tops of the adhesive layer 30 by 25 microns, the tops of the bumps 16 by 15 microns, and the tops of the conductive layer 36 by 15 microns. The thickness reduction has no significant effect on the bumps 16 or the adhesive layer 30, but the thickness of the conductive layer 36 is greatly reduced from 30 microns to 15 microns.

So far, the polished and planarized lateral upper surfaces of the bumps 16 , the adhesive layer 30 and the conductive layer 36 , that is, the surfaces above the dielectric layer 38 and facing upward, are coplanar with each other.

Figure 18 shows the above structure upside down.

The structure shown in FIG. 19 has holes 44 . The hole 44 is a through hole penetrating the outrigger platform 18 , the adhesive layer 30 , the conductive layer 36 and the dielectric layer 38 , and has a diameter of 300 microns. The hole 44 is formed by mechanical drilling, but it can also be made by other techniques, such as laser drilling and plasma etching.

The structure shown in FIG. 20 has a covering layer 46 . The coating layer 46 is deposited on the bumps 16 , the overhanging platform 18 , the adhesive layer 30 , the conductive layer 36 and the dielectric layer 38 , and the coating layer 46 forms the upper coating layer 48 , the lower coating layer 50 and the coating through hole 52 .

The upper cladding layer 48 is deposited on the bumps 16 and the surface 12 of the outrigger platform 18 , contacting and covering both from above. The upper cladding layer 48 is an unpatterned copper layer with a thickness of 20 microns.

The lower coating layer 50 is deposited on the lateral bottom surfaces of the bumps 16 , the adhesive layer 30 and the conductive layer 36 , while contacting and covering the three from below. The lower cladding layer 50 is an unpatterned copper layer with a thickness of 20 microns.

The coated through-hole 52 is deposited on and contacts the outrigger platform 18 , the adhesive layer 30 , the conductive layer 36 and the dielectric layer 38 inside the hole 44 , while covering the inner sidewall of the hole 44 in the lateral direction. The coating through-hole 52 is a copper tube with a thickness of 20 microns, which adjoins the upper coating layer 48 and the lower coating layer 50 and is integrated with them, and is electrically connected to each other.

For example, the structure may be dipped in an activator solution, thereby catalyzing the adhesion layer 30 and dielectric layer 38 with the electroless copper plating, followed by electroless coating of a first copper layer on the bumps. Block 16, outrigger platform 18, adhesive layer 30, conductive layer 36 and dielectric layer 38, and then a second copper layer is electroplated on the first copper layer. The thickness of the first copper layer is about 2 microns, and the thickness of the second copper layer is about 18 microns, so the total thickness of the covering layer 46 (and the covering layers 48 , 50 and the covering through hole 52 ) is about 20 microns. In this way, the thicknesses of the bumps 16 and the overhanging platforms 18 substantially increase in the upward direction, and the thickness of the conductive layer 36 substantially increases in the downward direction. In addition, the cavity 20 rises about 20 microns in the upward direction and still covers most of the bump 16 in the vertical and lateral directions, while the depth of the cavity 20 remains at 250 microns.

The upper cladding layer 48 is a thickened layer for the bump 16 and the overhanging platform 18 . The lower cladding layer 50 serves as a bottom of the bump 16 , a thickened layer of the conductive layer 36 , and a bridge structure between the bump 16 and the conductive layer 36 . The coated through hole 52 serves as an electrical interconnection between the outrigger platform 18 and the conductive layer 36 .

For ease of illustration, the bump 16 , the outrigger platform 18 , the upper coating layer 48 and the coating through-hole 52 are shown as a single layer. Likewise, for ease of illustration, the bump 16 , the conductive layer 36 and the lower cladding layer 50 are also shown as a single layer. Since the copper is homogeneously coated, the boundary between the bump 16 and the upper coating layer 48, the boundary between the overhanging platform 18 and the upper coating layer 48, the boundary between the overhanging platform 18 and the coating through hole 52, the boundary between the bump 16 and the lower coating The boundaries between layers 50 , between conductive layer 36 and lower cladding layer 50 , and between conductive layer 36 and coated through-holes 52 (both shown in dashed lines) may be imperceptible or even imperceptible. However, the boundary between the adhesive layer 30 and the lower coating layer 50 outside the hole 44 , the boundary between the adhesive layer 30 and the covering through hole 52 inside the hole 44 , and the boundary between the dielectric layer 38 and the covering through hole 52 inside the hole 44 are clearly visible.

The coating layers 48 and 50 of the structure shown in FIG. 21 are respectively provided with patterned etch stop layers 54 and 56 .

The patterned etch stop layers 54 and 56 shown in the figure are photoresist layers deposited on the coating layers 48 and 50 respectively, which are produced by pressing the photoresist layers to the coating layers respectively with a hot roller at the same time using dry press molding technology. 48, 50. Wet spin coating and curtain coating are also suitable photoresist forming techniques.

A first photomask (not shown) and a second photomask (not shown) are attached to the photoresist layers 54, 56 respectively, and then according to the prior art, light rays are selectively passed through the first and second photomasks respectively. The second photomask makes the part of the photoresist that is exposed to light insoluble; and then removes the part of the photoresist that is not exposed to light and is still soluble with a developer, so that the photoresist layers 54 and 56 are patterned. Therefore, the photoresist layer 54 has a pattern for selectively exposing the upper cladding layer 48 , and the photoresist layer 56 has a pattern for selectively exposing the lower cladding layer 50 . However, the photoresist layers 54 , 56 cover the bumps 16 and the coated through-holes 52 from above and below, respectively.

In the structure shown in FIG. 22 , the overhanging platform 18 and the upper cladding layer 48 have been etched to remove selected portions thereof to form a pattern defined by the patterned etch stop layer 54, and the conductive layer 36 and the lower cladding layer 50 have also been etched. Selected portions thereof have been removed by etching to form the pattern defined by the patterned etch stop layer 56 .

The etch is a double sided wet chemical etch. For example, a top nozzle (not shown) and a bottom nozzle (not shown) are used to spray the chemical etching solution on the top surface and the bottom surface of the structure respectively, or the structure is immersed in the chemical etching solution. The chemical etchant can etch through the overhanging platform 18 and the upper covering layer 48 , so that the adhesive layer 30 is exposed upward, thus transforming the originally non-patterned overhanging platform 18 and the upper covering layer 48 into a patterned layer. The chemical etchant also etches through the conductive layer 36 and the lower covering layer 50 , exposing the dielectric layer 38 toward the downward direction, thus transforming the originally non-patterned conducting layer 36 and the lower covering layer 50 into a patterned layer. Therefore, the adhesive layer 30 is only exposed upward but not downward, and the dielectric layer 38 is only exposed downward but not upward.

Chemical etchant solutions suitable for the above etching operations and highly selective to copper may be solutions containing alkaline ammonia or dilute mixtures of nitric and hydrochloric acids. In other words, the chemical etchant can be acidic or alkaline. The ideal etch time sufficient to form the pattern without over-exposing the overhanging mesa 18, conductive layer 36, and coating layers 48, 50 to the chemical etchant can be found by trial and error.

In FIG. 23 , the patterned etch stop layers 54 and 56 on the structure have been removed. The photoresist layers are removed by solvent treatment. For example, the solvent used may be a strongly alkaline potassium hydroxide solution with a pH of 14.

The etched outrigger platform 18 and upper cladding layer 48 include pads 60 and flange layer 62 . The bonding pad 60 and the flange layer 62 are defined and selected portions of the patterned etch stop layer 54 on the overhang platform 18 and the upper cladding layer 48 , and the bonding pad 60 and the flange layer 62 are kept at a distance from each other. The pad 60 is adjacent to the covered through hole 52 and extends laterally from the covered through hole 52 , while being electrically connected to the covered through hole 52 and keeping a distance from the bump 16 . The flange layer 62 adjoins the bump 16 , is integrally formed with the bump 16 , extends laterally from the bump 16 , is thermally connected to the bump 16 , and maintains a distance from the coating through hole 52 . After the flange layer 62 is disposed, the protrusion 16 and the recess 20 are located in the central area of the periphery of the flange layer 62 . In addition, both the pad 60 and the flange layer 62 are in contact with the adhesive layer 30 , but are also kept at a distance from the dielectric layer 38 . The welding pad 60 and the flange layer 62 extend above the adhesive layer 30 and the dielectric layer 38 , and are flat and have a thickness of 90 (70+20) microns. The pad 60 is coplanar with the upper surface of the flange layer 62 facing upward.

The etched conductive layer 36 and the lower cladding layer 50 include a base 64 and a terminal 66 . The pedestal 64 and the terminal 66 are defined and selected portions of the patterned etch stop layer 56 on the conductive layer 36 and the lower cladding layer 50 , and the pedestal 64 and the terminal 66 are kept at a distance from each other. The base 64 adjoins the bump 16 and extends below the bump 16 and extends laterally from the bump 16 while being thermally connected to the bump 16 . The base 64 covers the bump 16 and the flange layer 62 from below, and keeps a distance from the coating through hole 52 . The thickness of pedestal 64 is 20 microns adjacent to bump 16 and 35 microns adjacent to dielectric layer 38 (15+20). In addition, the portion of the base 64 adjacent to the adhesive layer 30 and at a distance from the dielectric layer 38 is 20 microns thick, and the base 64 is at a corner formed by a side surface adjacent to the adhesive layer 30 and a bottom surface of the dielectric layer 38. 35 microns thick. The terminal 66 is adjacent to and electrically connected to the covered through-hole 52 and keeps a distance from the bump 16 . The thickness of the terminal 66 is 35 microns (15+20). Moreover, the base 64 is in contact with the adhesive layer 30 and the dielectric layer 38 , and the terminal 66 is in contact with the dielectric layer 38 but keeps a distance from the adhesive layer 30 . The base 64 and the terminal 66 both extend under the adhesive layer 30 and the dielectric layer 38 , the thickness of the base 64 and the terminal 66 are equal adjacent to each other, but the thickness of the base 64 adjacent to the bump 16 is different from that of the terminal 66 . The base 64 is coplanar with the lower surface of the terminal 66 facing downward.

The covered through hole 52 , the pad 60 and the terminal 66 together form a wire 70 . Accordingly, the wire 70 includes selected portions of both the overhanging platform 18 and the upper cladding layer 48 and selected portions of both the conductive layer 36 and the lower cladding layer 50 that adjoin the cladding through-hole 52 and are in contact with the bump. 16. Keep your distance. The wire 70 is located outside the pocket 20 . In addition, the covered through hole 52 is a conductive path between the pad 60 and the terminal 66 .

Wire 70 not only provides horizontal (lateral) routing from pad 60 to coated via 52 , but also provides vertical (top-to-bottom) routing from pad 60 to terminal 66 through coated via 52 . The wire 70 is not limited to this configuration. For example, bonding pad 60 may be electrically connected to coated via 52 using a routing line over adhesive layer 30 and dielectric layer 38 and defined by patterned etch stop layer 54, while terminal 66 may be electrically connected to coated via 52 using a routing line located above adhesive layer 30 and dielectric layer 38. The adhesive layer 30 is electrically connected to the coated through hole 52 with the routing line under the dielectric layer 38 and defined by the patterned etch stop layer 56 . In addition, the above-mentioned conductive paths may also include conductive holes through the adhesive layer 30 and/or the dielectric layer 38, additional routing lines (which are located above and/or below the adhesive layer 30 and/or the dielectric layer 38), and passive components. (such as resistors and capacitors placed on other pads).

The bump 16 , the flange layer 62 and the base 64 jointly form a heat sink 72 . Accordingly, heat sink 72 includes: selected portions of both overhanging platform 18 and upper cladding layer 48, wherein the selected portions adjoin bumps 16 and are spaced from leads 70; a selected portion of conductive layer 36, wherein The selected portion is distanced from the bump 16 and the wire 70 ; and a selected portion of the lower cladding layer 50 , wherein the selected portion is adjacent to the bump 16 and distanced from the wire 70 . Additionally, bump 16 provides a thermally conductive path to base 64 .

The heat sink 72 is essentially an inverted T-shaped heat sink, which includes a column (bump 16), wing (the portion of the base 64 extending laterally from the column) and a thermal pad (flange layer 62). .

The conductive wire 70 and the heat sink 72 of the structure shown in FIG. 24 are provided with covered contacts 74 .

Covered contact 74 is a multilayer metal plating that contacts the exposed copper surface. Thus, the covered contact 74 contacts the bump 16, the covered through-hole 52, the solder pad 60 and the flange layer 62 and covers them from above, and also contacts the covered through-hole 52, the base 64 and the terminal 66 and covers them from below. three. For example, a nickel layer is electrolessly coated on the exposed copper surface, and then a silver layer is electrolessly coated on the nickel layer, wherein the inner nickel layer is about 3 microns thick, and the silver The textured surface layer is about 0.5 microns thick, so the thickness of the coated contact 74 is about 3.5 microns.

The surface treatment of bumps 16, solder pads 60, flange layer 62, base 64, and terminals 66 with covered contacts 74 has several advantages. The inner nickel layer provides the primary mechanical and electrical connections and/or thermal connections, while the silver surface layer provides a wettable surface for solder reflow, for soldering and wire bonding. The coated contact 74 also protects the wire 70 and the heat sink 72 from corrosion. Covered contacts 74 may comprise various metals to suit the needs of the external connection medium. For example, an inner nickel layer may be coated with a gold layer, or a nickel surface layer may be used alone.

For ease of illustration, the conductive wire 70 with the covered contact 74 and the heat sink 72 are represented as a single layer. The boundary (not shown) between the wire 70 and the covered contact 74 and the boundary (not shown) between the heat sink 72 and the covered contact 74 is a copper/nickel interface.

So far, the fabrication of the heat conducting plate 80 is completed.

Fig. 25, Fig. 26 and Fig. 27 are the sectional view, top view and bottom view of the heat conduction plate 80 respectively, in which the edge of the heat conduction plate 80 has been separated from the supporting frame and/or adjacent heat conduction plates produced in the same batch along the cutting line.

The heat conducting plate 80 includes an adhesive layer 30 , a substrate 34 , a wire 70 and a heat sink 72 . Substrate 34 includes dielectric layer 38 . The wire 70 includes a covered through-hole 52 , a pad 60 and a terminal 66 . The heat sink 72 includes the bump 16 , the flange layer 62 and the base 64 .

The lug 16 abuts the flange layer 62 at the bent corner 22 (see FIG. 2 ), and abuts the base 64 at the bent corner 24 and the bottom plate 28 (see FIG. 2 ). The protrusion 16 extends upward from the base 64 , extends downward from the flange layer 62 , and is integrally formed with the flange layer 62 . After the bump 16 extends into the opening 32 and the through hole 40 , it is still located at the center of the opening 32 and the through hole 40 (see FIG. 14 ). The bottom of the bump 16 is coplanar with an adjacent portion of the adhesive layer 30 that contacts the base 64 . The bump 16 also contacts the adhesive layer 30 and maintains a distance from the dielectric layer 38 , while maintaining a flat-topped cone shape with a diameter increasing upward from the base 64 toward the flange layer 62 .

The recess 20 facing upward extends into the protrusion 16 , the opening 32 and the through hole 40 , and is always located at the center of the protrusion 16 , the opening 32 and the through hole 40 . The bump 16 covers the pocket 20 from below and separates the pocket 20 from the base 64 . The cavity 20 has a shape conforming to the bump 16, covering most of the bump 16 vertically and sideways on the one hand, and maintaining a flat-topped cone shape with a diameter extending from the bottom surface at the bottom plate 28 toward the flange. The entrances at level 62 are incremented upwards.

The flange layer 62 extends laterally from the bump 16 , extends over and overlaps the adhesive layer 30 , the dielectric layer 38 , the opening 32 and the via 40 . The flange layer 62 contacts the adhesive layer 30 but keeps a distance from the dielectric layer 38 and the base 64 . The thickness of the flange layer 62 is greater than the thickness of the base 64 .

The base 64 protrudes from the protrusion 16 , extends laterally beyond the opening 32 , the through hole 40 and the flange layer 62 , and covers the protrusion 16 , the opening 32 , the through hole 40 and the flange layer 62 from below. The base 64 is in contact with the adhesive layer 30 and the dielectric layer 38 , and extends outside of the two towards the downward direction. The base 64 supports the adhesive layer 30 and the substrate 34 , and keeps a distance from the peripheral edge of the heat conducting plate 80 . The pedestal 64 has a first thickness (20 microns) adjacent to the bump 16 and a second thickness (35 microns) greater than the first thickness adjacent to the dielectric layer 38. The pedestal 64 also has a side facing downward facing flat surface. In addition, a portion of the base 64 adjacent to the adhesive layer 30 and at a distance from the dielectric layer 38 also has the first thickness, and a corner of the base 64 adjacent to the adhesive layer 30 and the dielectric layer 38 also has the first thickness. Two thickness.

The adhesive layer 30 is in contact with the gap 42 and interposed between the bump 16 and the dielectric layer 38 , and fills the space between the bump 16 and the dielectric layer 38 . The adhesive layer 30 contacts the dielectric layer 38 , the coating through hole 52 and the flange layer 62 outside the gap 42 . The adhesive layer 30 contacts the base 64 but keeps a distance from the terminals 66 . The adhesive layer 30 not only extends across the dielectric layer 38 in the gap 42, but also extends between the bump 16 and the flange layer 62, between the bump 16 and the base 64, and is located between the bump 16 and the coated through hole 52 and the flange. Layer 62 and base 64 . The adhesive layer 30 also extends laterally from the bump 16, over the wire 70, and finally to the peripheral edge of the semiconductor chip package body. At this time, the adhesive layer 30 is cured.

The adhesive layer 30 covers and surrounds the bump 16 along the side direction, covers the portion of the base 64 outside the periphery of the bump 16 from above, covers the dielectric layer 38 and the terminal 66 from above, and covers the pad 60 and the flange layer from below. 62. Adhesive layer 30 also conformally coats sidewall 26 (see FIG. 2 ) of bump 16 , a top surface of dielectric layer 38 , and a top surface portion of submount 64 , wherein the top surface portion adjoins bump 16 and exits from the bump 16 . The protrusion 16 extends laterally and faces upward.

The dielectric layer 38 is in contact with and interposed between the adhesive layer 30 and the base 64 and between the adhesive layer 30 and the terminal 66 .

Both the pad 60 and the flange layer 62 are in contact with the adhesive layer 30 , but also keep a distance from the dielectric layer 38 .

The coating through hole 52 contacts and penetrates the adhesive layer 30 and the dielectric layer 38 in the hole 44 (see FIG. 19 ), and extends above and below the adhesive layer 30 and the dielectric layer 38 . The covered through hole 52 maintains a tubular shape and has vertical inner and outer side walls, wherein the diameter of the covered through hole 52 is constant along the vertical direction extending from the solder pad 60 to the terminal 66 .

The bottoms of the bumps 16 and the adhesive layer 30 are coplanar at the base 64 . In addition, the bonding pad 60 and the flange layer 62 have the same thickness (90 μm) and are coplanar with the upward facing surface on the adhesive layer 30 and the dielectric layer 38 . The pedestal 64 has the same thickness adjacent to the terminal 66 (35 microns), but the thickness of the pedestal 64 adjacent to the bump 16 is different from that of the terminal 66 (20 and 35 microns, respectively). The base 64 is coplanar with the downward facing surface of the terminal 66 located under the adhesive layer 30 and the dielectric layer 38 .

After the heat conduction plate 80 produced in the same batch is cut, the adhesive layer 30 and the dielectric layer 38 both extend to the vertical edge formed by cutting.

The welding pad 60 is an electrical interface tailor-made for semiconductor components such as LED chips, which will be disposed on the bumps 16 in subsequent manufacturing processes. Terminal 66 is an electrical interface tailor-made for the next-level semiconductor chip assembly (eg, solderable wires from a printed circuit board). The base 64 is a tailor-made thermal interface for the next layer of semiconductor chip assembly (such as the aforementioned printed circuit board or a heat sink of an electronic device).

The pads 60 and the terminals 66 are offset from each other in the horizontal and vertical directions, and are respectively exposed on the top surface and the bottom surface of the heat conducting plate 80, so as to provide horizontal and vertical routing between the semiconductor device and the semiconductor chip assembly of the next layer.

For ease of illustration, the wire 70 is shown as a continuous circuit trace in the cross-sectional view. However, the wire 70 generally provides horizontal signal routing in the X and Y directions at the same time, that is to say, the bonding pad 60 and the terminal 66 are laterally displaced in the X and Y directions. Additionally, the coated perforations 52 may be located at the corners of the thermally conductive plate 80 .

The wire 70 and the heat sink 72 keep a distance from each other. Therefore, the wire 70 and the heat sink 72 are mechanically connected and electrically isolated from each other.

The heat sink 72 can dissipate the heat energy generated by the semiconductor device subsequently disposed on the bump 16 to the next layer of semiconductor chip assembly connected to the heat conducting plate 80 . The heat energy generated by the semiconductor element flows into the bump 16 and enters the base 64 through the bump 16 . Thermal energy is dissipated from the base 64 in a downward direction, for example to a heat sink below.

Covered contacts 74 occupy 85% to 95% of the top surface of thermally conductive plate 80, thus providing a highly reflective top surface. This highly reflective top surface is particularly useful if the component subsequently disposed in the cavity 20 of the bump 16 is an LED component.

Bump 16, coated via 52, pad 60, flange layer 62, base 64 and terminal 66 are all the same metal, ie copper/nickel/silver. Bump 16, coated via 52, pad 60, flange layer 62, base 64, and terminal 66 are composed of a silver surface layer, an inner copper core, and an inner nickel layer, wherein the inner nickel layer is in contact with and between between the silver surface layer and the inner copper core. The inner copper cores of bumps 16 , coated vias 52 , pads 60 , flange layer 62 , base 64 , and terminals 66 are primarily copper. The silver surface layer and the inner nickel layer are provided by coated contacts 74 , while the inner copper core is provided by various combinations of metal plate 10 (see FIG. 2 ), conductive layer 36 and coating layer 46 .

Conductor 70 includes an inner copper core shared by coated via 52 , pad 60 and terminal 66 , while heat sink 72 includes an inner copper core shared by bump 16 , flange layer 62 and base 64 . In addition, the coated through hole 52 of the wire 70, the pad 60 and the terminal 66 all include a covered contact point 74, and the bump 16 and the flange layer 62 of the heat sink 72 also include a covered contact point 74 (which is kept at a distance from the base 64), so as to dissipate heat. The base 64 of the seat 72 also includes a covered contact 74 (which is distanced from the bump 16 and flange layer 62). In addition, the wire 70 and the heat sink 72 are composed of copper/nickel/silver, and the inner copper core is mainly copper.

The heat conducting plate 80 may include a plurality of wires 70 formed by covering the through holes 52 , the pads 60 and the terminals 66 . For ease of illustration, only a single wire 70 is described and shown here. In the leads 70, the coated vias 52, pads 60, and terminals 66 are generally of similar shape and size. For example, some of the wires 70 are spaced, separated from each other, and electrically isolated, while some of the wires 70 cross each other or lead to the same pad 60 or terminal 66 and are electrically connected to each other. Likewise, some of the pads 60 can be used to receive independent signals, while some of the pads 60 share a signal, power or ground terminal.

The thermally conductive plate 80 is applicable to LED packages having blue, green and red LED chips, wherein each LED chip includes an anode and a cathode, and each LED package includes corresponding anode terminals and cathode terminals. In this example, the thermally conductive plate 80 may include six solder pads 60 and four terminals 66 so that each anode is directed from a separate solder pad 60 to a separate terminal 66 and each cathode is directed from a separate solder pad 60 A common ground terminal 66 .

Oxides and residues on exposed metal can be removed at various stages of fabrication by a simple cleaning step, such as a brief oxygen plasma cleaning step on the structure in this case. Alternatively, the present structure can be subjected to a brief wet chemical cleaning step using a potassium permanganate solution. Similarly, distilled water can also be used to rinse the structure of this case to remove dirt. This cleaning step cleans the desired surface without significantly affecting or damaging the structure.

The advantage of this embodiment is that, after the wire 70 is formed, there is no need to separate or divide the sink point or related circuit system therefrom. The junctions may be separated during the wet chemical etch step that forms pad 60 and flange layer 62 .

The heat conducting plate 80 may include alignment holes (not shown) formed by drilling or cutting through the adhesive layer 30 and the substrate 34 . In this way, when the heat conduction plate 80 needs to be arranged on a lower carrier in the subsequent process, the pins of the tool can be inserted into the alignment holes, so as to position the heat conduction plate 80 .

The heat conducting plate 80 can accommodate a plurality of semiconductor elements, instead of a single bump or a plurality of bumps can only accommodate a single semiconductor element. Therefore, a plurality of semiconductor devices can be disposed on a single bump, or a plurality of semiconductor devices can be disposed on different bumps respectively.

If a single bump of the thermally conductive plate 80 is intended to accommodate multiple semiconductor elements, additional holes can be drilled to define more coated through-holes 52, the patterned etch resist layer 54 is adjusted to define more solder pads 60, and the patterned The stop layer 56 is etched to define more terminals 66 . Covered vias 52, pads 60 and terminals 66 can be changed laterally to provide a 2x2 array of four semiconductor elements. In addition, the cross-sectional shape and height (that is, the side shape) of the pad 60 , the base 64 and the terminal 66 can also be adjusted.

If it is desired to form multiple bumps on the thermally conductive plate 80 to accommodate multiple semiconductor devices, additional bumps 16 can be stamped on the metal plate 10, the adhesive layer 30 can be adjusted to include more openings 32, and the substrate 34 can be adjusted to include more openings. Multiple vias 40, additional holes are drilled to define more covered vias 52, patterned etch stop layer 54 is adjusted to define more pads 60 and flange layers 62, and patterned etch stop layer 56 is adjusted to define more Base 64 and terminals 66 . Bumps 16 , plated vias 52 , pads 60 , flange layer 62 , pedestals 64 and terminals 66 can be changed laterally to provide a 2×2 array of four semiconductor devices. In addition, the cross-sectional shape and height (that is, the side shape) of the bump 16 , the welding pad 60 , the flange layer 62 , the base 64 and the terminal 66 can also be adjusted. Furthermore, the plurality of bumps 16 can have independent bases 64 or share a base 64 , depending on the design of the patterned etch stop layer 56 .

Fig. 28, Fig. 29 and Fig. 30 are respectively the sectional view, top view and bottom view of a heat conduction plate in an embodiment of the present invention, and the peripheral edge of the heat conduction plate is provided with coated perforations.

In this embodiment, the coating perforation is located on the peripheral edge formed by separating the heat conduction plate from the adjacent heat conduction plate produced in the same batch. For the sake of brevity, all relevant descriptions of the heat conducting plate 80 that are applicable to this embodiment are incorporated here, and the same descriptions will not be repeated. Likewise, components of the heat conducting plate in this embodiment are similar to those of the heat conducting plate 80 , and corresponding reference numerals are used.

The heat conducting plate 82 includes an adhesive layer 30 , a substrate 34 , a wire 70 and a heat sink 72 . Substrate 34 includes dielectric layer 38 . The wire 70 includes the covered through-hole 52 , the pad 60 and the terminal 66 . The heat sink 72 includes the bump 16 , the flange layer 62 and the base 64 .

The coated perforations 52 are located at the peripheral edge of the heat conducting plate 82 instead of keeping a distance from the peripheral edge of the heat conducting plate 82 . The covering perforation 52 is not tubular with a full circumference, but has a semi-tubular shape, that is to say has only a semicircular circumference. The adhesive layer 30 extends laterally from the bump 16 to the covered through hole 52 , the pad 60 and the terminal 66 , but does not go beyond the covered through hole 52 , the pad 60 and the terminal 66 . In addition, the heat conduction plate 82 is smaller than the heat conduction plate 80 .

The heat conduction plate 82 can be fabricated in a manner similar to that of the heat conduction plate 80 , as long as the coating perforation 52 is properly adjusted. For example, the adhesive layer 30 is disposed on the outreach platform 18 first, and then the substrate 34 is disposed on the adhesive layer 30 . Heat and pressurize the adhesive layer 30 to make the adhesive layer 30 flow and solidify. The lateral surfaces of the bump 16 , the adhesive layer 30 and the conductive layer 36 are made planar by grinding. Holes 44 are formed by drilling through the overhanging mesa 18, adhesive layer 30, conductive layer 36, and dielectric layer 38, and then coating layers 48, 50 and coating vias 52 are deposited on the structure in the manner previously described. Then etch the overhanging platform 18 and the upper cladding layer 48 to form the solder pad 60 and the flange layer 62, etch the conductive layer 36 and the lower cladding layer 50 to form the base 64 and the terminal 66, and then use the covered contact 74 as the bump 16 , welding pad 60 , flange layer 62 , base 64 and terminal 66 are surface treated. Finally, cut or split the adhesive layer 30 , the substrate 34 , the coating through hole 52 , the pad 60 , the base 64 and the terminal 66 at the peripheral edge of the heat conduction plate 82 to separate the heat conduction plate 82 from other heat conduction plates produced in the same batch. In this way, half of the tubular portion covering the through hole 52 is separated from the peripheral edge of the heat conducting plate 82 , while the other half of the tubular portion covering the through hole 52 remains completely on the peripheral edge of the heat conducting plate 82 .

Fig. 31, Fig. 32 and Fig. 33 are respectively a cross-sectional view, a top view and a bottom view of a heat conduction plate in an embodiment of the present invention, and the projection of the heat conduction plate has the same space range as the base.

In this embodiment, the bump and the base occupy the same space range. For the sake of brevity, all relevant descriptions of the heat conducting plate 80 that are applicable to this embodiment are incorporated here, and the same descriptions will not be repeated. Likewise, components of the heat conducting plate in this embodiment are similar to those of the heat conducting plate 80 , and corresponding reference numerals are used.

The heat conducting plate 84 includes the adhesive layer 30 , the substrate 34 , the wire 70 and the heat sink 72 . The substrate 34 includes a dielectric layer 38 and a conductive layer 36 . The wire 70 includes the covered through-hole 52 , the pad 60 and the terminal 66 . The heat sink 72 includes the bump 16 , the flange layer 62 and the base 64 .

The base 64 and the protrusion 16 have the same spatial extent at the bottom plate 28 . Therefore, the base 64 does not extend laterally from the bump 16 , and the adhesive layer 30 is exposed downward. In addition, the heat conduction plate 84 is smaller than the heat conduction plate 80 .

The heat conduction plate 84 can be fabricated in a manner similar to that of the heat conduction plate 80 , as long as the pads 60 , the base 64 and the terminals 66 are properly adjusted. For example, the adhesive layer 30 is disposed on the outreach platform 18 first, and then the substrate 34 is disposed on the adhesive layer 30 . Heat and pressurize the adhesive layer 30 to make the adhesive layer 30 flow and solidify. The lateral surfaces of the bump 16 , the adhesive layer 30 and the conductive layer 36 are planarized by grinding. Drilling through the overhanging platform 18, the adhesive layer 30, the conductive layer 36 and the dielectric layer 38 to form the hole 44, and then depositing the coating layers 48, 50 and the coating through-hole 52 on the structure in the aforementioned manner, wherein the hole 44 is positioned toward The lug 16 is laterally offset, and thus the position of the coated perforation 52 is also offset laterally toward the lug 16 . Then patterned etch stop layers 54, 56 are respectively formed on the coating layers 48, 50, wherein the patterned etch stop layer 54 is adjusted to reduce the size of the pad 60, and the patterned etch stop layer 56 is also adjusted. , so that the base 64 is aligned with the bottom plate 28 of the bump 16 , and the position of the terminal 66 is shifted laterally toward the bump 16 . Then etch the overhanging platform 18 and the upper coating layer 48 to form the pad 60 and the flange layer 62, etch the conductive layer 36 and the lower coating layer 50 to form the base 64 and the terminal 66, and then use the covered contact 74 as the bump 16 , welding pad 60 , flange layer 62 , base 64 and terminal 66 are surface treated. Finally, the adhesive layer 30 and the substrate 34 are cut or split at the peripheral edge of the heat conduction plate 84 to separate the heat conduction plate 84 from other heat conduction plates produced in the same batch.

Fig. 34, Fig. 35 and Fig. 36 are respectively a sectional view, a top view and a bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate has a thickened base and terminals.

In this embodiment, the substrate is a thick conductive layer without a dielectric layer. For the sake of brevity, all relevant descriptions of the heat conducting plate 80 that are applicable to this embodiment are incorporated here, and the same descriptions will not be repeated. Likewise, components of the heat conducting plate in this embodiment are similar to those of the heat conducting plate 80 , and corresponding reference numerals are used.

The heat conducting plate 86 includes the adhesive layer 30 , the wire 70 and the heat sink 72 . The wire 70 includes the covered through-hole 52 , the pad 60 and the terminal 66 . The heat sink 72 includes the bump 16 , the flange layer 62 and the base 64 .

The conductive layer 36 in this embodiment is thicker than the conductive layer 36 in the previous embodiments. For example, the thickness of the conductive layer 36 is 130 micrometers (instead of 30 micrometers), so that the conductive layer 36 can be prevented from being bent or shaken during transportation, and the base 64 and the terminal 66 are thus thickened. Thermally conductive plate 86 lacks a dielectric layer corresponding to dielectric layer 38 .

The heat conduction plate 86 can be fabricated in a manner similar to that of the heat conduction plate 80 , as long as the conductive layer 36 is properly adjusted. For example, firstly the adhesive layer 30 is disposed on the overhanging platform 18 , and then the conductive layer 36 is separately disposed on the adhesive layer 30 . Heat and pressurize the adhesive layer 30 to make the adhesive layer 30 flow and solidify. The lateral surfaces of the bump 16 , the adhesive layer 30 and the conductive layer 36 are planarized by grinding. Holes 44 are formed by drilling through the overhanging mesa 18, adhesive layer 30, and conductive layer 36, and then coating layers 48, 50 and coating vias 52 are deposited on the structure in the manner previously described. Then etch the overhanging platform 18 and the upper cladding layer 48 to form the pad 60 and the flange layer 62, etch the conductive layer 36 and the lower cladding layer 50 to form the base 64 and the terminal 66, and then use the covered contact 74 as the bump 16 , welding pad 60 , flange layer 62 , base 64 and terminal 66 are surface treated. Finally, the adhesive layer 30 and the substrate 34 are cut or split at the peripheral edge of the heat conduction plate 86 to separate the heat conduction plate 86 from other heat conduction plates produced in the same batch.

Fig. 37, Fig. 38 and Fig. 39 are respectively the sectional view, top view and bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate and the lower surface respectively have a layer of solder resist green paint.

In this embodiment, the top layer and the bottom layer of solder resist green paint selectively expose the wires and the heat sink. For the sake of brevity, all relevant descriptions of the heat conducting plate 80 that are applicable to this embodiment are incorporated here, and the same descriptions will not be repeated. Likewise, components of the heat conducting plate in this embodiment are similar to those of the heat conducting plate 80 , and corresponding reference numerals are used.

The heat conducting plate 88 includes an adhesive layer 30 , a substrate 34 , a wire 70 , a heat sink 72 and solder resist green paints 76 , 77 . The substrate 34 includes a dielectric layer 38 and a conductive layer 36 . The wire 70 includes the covered through-hole 52 , the pad 60 and the terminal 66 . The heat sink 72 includes the bump 16 , the flange layer 62 and the base 64 .

The solder resist green paint 76 is an electrical insulating layer, which selectively exposes the bump 16 , the welding pad 60 and the flange layer 62 toward the upward direction, and covers the portion of the adhesive layer 30 that is originally exposed toward the upward direction. The solder resist green paint 77 is an electrical insulation layer, which selectively exposes the base 64 and the terminals 66 downward, and covers the portion of the dielectric layer 38 that is originally exposed downward.

The heat conduction plate 88 can be manufactured in a manner similar to that of the heat conduction plate 80, as long as the solder resist green paints 76 and 77 are properly adjusted. For example, the adhesive layer 30 is disposed on the outreach platform 18 first, and then the substrate 34 is disposed on the adhesive layer 30 . Heat and pressurize the adhesive layer 30 to make the adhesive layer 30 flow and solidify. The lateral surfaces of the bump 16 , the adhesive layer 30 and the conductive layer 36 are planarized by grinding. Holes 44 are formed by drilling through the overhanging mesa 18, adhesive layer 30, conductive layer 36, and dielectric layer 38, and then coating layers 48, 50 and coating vias 52 are deposited on the structure in the manner previously described. Then etch the overhanging platform 18 and the upper cladding layer 48 to form the solder pad 60 and the flange layer 62, etch the conductive layer 36 and the lower cladding layer 50 to form the base 64 and the terminal 66, and then form a solder resist green on the top surface of the structure paint 76 , and form solder resist green paint 77 on the bottom surface of the structure, and then use the covered contacts 74 as bumps 16 , solder pads 60 , flange layer 62 , base 64 and terminals 66 for surface treatment. Finally, cut or split the adhesive layer 30 , substrate 34 and solder resist green paint 76 , 77 at the peripheral edge of the heat conduction plate 88 to separate the heat conduction plate 88 from other heat conduction plates produced in the same batch.

Solder resist green paints 76 and 77 are initially photo-imageable liquid resins coated on the top and bottom surfaces of the structure respectively, and then patterns are formed. The method is to allow light to selectively pass through a mask (not shown) Part of the solder resist green paint becomes insoluble, and then a developer solution is used to remove the part of the solder resist green paint that has not been exposed to light and is still soluble, and finally hard baked. The above steps are the existing technology.

Fig. 40, Fig. 41 and Fig. 42 are respectively the sectional view, top view and bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate has a layer of embedded solder resist green paint.

In this embodiment, a layer of embedded solder resist green paint is in contact with and interposed between the solder pad and the flange layer. For the sake of brevity, all relevant descriptions of the heat conducting plate 80 that are applicable to this embodiment are incorporated here, and the same descriptions will not be repeated. Likewise, components of the heat conducting plate in this embodiment are similar to those of the heat conducting plate 80 , and corresponding reference numerals are used.

The heat conducting plate 90 includes an adhesive layer 30 , a substrate 34 , a wire 70 , a heat sink 72 and a solder resist green paint 76 . The substrate 34 includes a dielectric layer 38 and a conductive layer 36 . The wire 70 includes the covered through-hole 52 , the pad 60 and the terminal 66 . The heat sink 72 includes the bump 16 , the flange layer 62 and the base 64 .

The solder resist green paint 76 is an electrical insulating layer, which is in contact with and interposed between the solder pad 60 and the flange layer 62 , and is recessed relative to the solder pad 60 and the flange layer 62 . The solder resist green paint 76 contacts the adhesive layer 30 and covers the exposed portion of the adhesive layer 30 facing upward.

The heat conduction plate 90 can be manufactured in a manner similar to that of the heat conduction plate 80 , as long as the metal plate 10 and the solder resist green paint 76 are properly adjusted. For example, first utilize a patterned etch stop layer to etch the metal plate 10 (refer to FIG. 54 is similar but slightly wider. The groove protrudes into, but does not penetrate through, the metal plate 10 at a distance from the surface 12 , and defines the lower portion of the solder pad 60 and the lower portion of the flange layer 62 . Solder resist green paint 76 is formed in the groove, and then the metal plate 10 is stamped to form bumps 16 . Subsequently, the adhesive layer 30 is disposed on the outrigger platform 18 , and the substrate 34 is disposed on the adhesive layer 30 . Heat and pressurize the adhesive layer 30 to make the adhesive layer 30 flow and solidify. The lateral surfaces of the bump 16 , the adhesive layer 30 and the conductive layer 36 are planarized by grinding. Drilling through the overhanging platform 18, the adhesive layer 30, the conductive layer 36, and the dielectric layer 38 to form a hole 44 (see FIG. 19), and then depositing the coating layers 48, 50 and coating the via 52 on the structure in the manner described above superior. Then the upper covering layer 48 is etched separately to form the upper part of the welding pad 60 and the upper part of the flange layer 62, and the solder resist green paint 76 is exposed but the adhesive layer 30 is not exposed. In addition, the conductive layer 36 and the lower covering layer 50 are etched to form the base layer. The seat 64 and the terminal 66 are surface-treated with the covered contact 74 as the bump 16 , the welding pad 60 , the flange layer 62 , the base 64 and the terminal 66 . Finally, cutting or splitting the adhesive layer 30 , the substrate 34 and the solder resist green paint 76 at the peripheral edge of the heat conducting plate 90 separates the heat conducting plate 90 from other heat conducting plates produced in the same batch.

Initially, the solder resist green paint 76 is a photovisible liquid resin coated on the surface 14 of the metal plate 10 and fills up the aforementioned grooves. When coating the liquid resin, the metal plate 10 can be turned upside down so that the surface 14 faces upwards, so that the liquid resin can flow into the groove by gravity. The solder resist green paint 76 is then hardened by hard baking, which is known in the art. Then the metal plate 10 is turned over again so that the surface 14 faces downward, and then the lower part of the metal plate 10 and the lower part of the solder resist green paint 76 are removed by grinding. For example, a diamond grinding wheel can be rotated and distilled water can be used to treat the bottom of the structure. Initially, the diamond wheel only removes the solder mask green paint 76 . Continue to grind, then the solder resist green paint 76 becomes thinner because of the upward movement of the ground surface. The diamond grinding wheel will eventually contact the metal plate 10 and start grinding the metal plate 10 as well. After continuous grinding, both the metal plate 10 and the solder resist green paint 76 become thinner due to the upward movement of the ground surface. Grinding continues until the desired thickness is removed. Afterwards, the structure was rinsed with distilled water to remove dirt. So far, the ground and flattened lateral bottom surfaces of the metal plate 10 and the solder resist green paint 76 facing downward are coplanar with each other, and the solder resist green paint 76 is located in the aforementioned groove and fills up the groove.

43 , 44 and 45 are a cross-sectional view, a top view and a bottom view respectively of a heat conducting plate in an embodiment of the present invention, the heat conducting plate can provide horizontal signal routing.

In this embodiment, the pads and terminals are located above the adhesive layer and the dielectric layer. In addition, this embodiment omits covering through holes. For the sake of brevity, all relevant descriptions of the heat conducting plate 80 that are applicable to this embodiment are incorporated here, and the same descriptions will not be repeated. Likewise, components of the heat conducting plate in this embodiment are similar to those of the heat conducting plate 80 , and corresponding reference numerals are used.

The heat conducting plate 92 includes an adhesive layer 30 , a substrate 34 , a wire 70 , a heat sink 72 and a solder resist green paint 76 . The substrate 34 includes a dielectric layer 38 and a conductive layer 36 . The wire 70 includes a pad 60 , a routing line 65 and a terminal 66 . The heat sink 72 includes the bump 16 , the flange layer 62 and the base 64 .

Wire 70 provides horizontal (lateral) routing from pad 60 to terminal 66 , while routing wire 65 forms a conductive path between pad 60 and terminal 66 . The pads 60 , routing lines 65 and terminals 66 are located above the adhesive layer 30 , contact the adhesive layer 30 but keep a distance from the dielectric layer 38 , and overlap the dielectric layer 38 . The pads 60 are coplanar with the terminals 66 over the adhesive layer 30 . The base 64 covers the bump 16 , the adhesive layer 30 , the substrate 34 , the flange layer 62 , the wire 70 and the solder resist green paint 76 from below, and the base 64 extends to the peripheral edge of the heat conducting plate 92 . The solder resist green paint 76 is an electrical insulation layer, which selectively exposes the bump 16 , the pad 60 , the flange layer 62 and the terminal 66 , covers the routing line 65 from above, and extends to the peripheral edge of the heat conducting plate 92 . Therefore, the wire 70 is kept away from the dielectric layer 38 , and the thermally conductive plate 92 lacks a covered through hole corresponding to the covered through hole 52 .

The heat conduction plate 92 can be manufactured in a manner similar to that of the heat conduction plate 80 , as long as the base 64 , the wire 70 and the solder resist green paint 76 are properly adjusted. For example, the adhesive layer 30 is disposed on the outreach platform 18 first, and then the substrate 34 is disposed on the adhesive layer 30 . Heat and pressurize the adhesive layer 30 to make the adhesive layer 30 flow and solidify. The lateral surfaces of the bump 16 , the adhesive layer 30 and the conductive layer 36 are planarized by grinding, and then the coating layers 48 , 50 are deposited on the structure in the aforementioned manner. Due to the omission of holes 44 , coating perforations 52 are also absent. The overhanging platform 18 and the upper cladding layer 48 are then etched using a single patterned etch resist layer to form the pads 60, the flange layer 62, the routing lines 65 and the terminals 66, while the conductive layer 36 and the lower cladding layer 50 remain unpatterned. state. After the solder resist green paint 76 is formed on the top surface of the structure, the surface treatment is carried out by using the covered contacts 74 as the bumps 16 , the welding pads 60 , the flange layer 62 , the base 64 and the terminals 66 . Finally, cut or split the adhesive layer 30 , substrate 34 , base 64 and solder resist green paint 76 at the peripheral edge of the heat conduction plate 92 to separate the heat conduction plate 92 from other heat conduction plates produced in the same batch.

Solder resist green paint 76 is initially a light-developing liquid resin coated on the top surface of the structure before forming a pattern. The green paint becomes insoluble, and then a developing solution is used to remove the part of the solder resist green paint that has not been exposed to light and is still soluble, and finally hard baking is performed. The above steps are the existing technology.

Fig. 46, Fig. 47 and Fig. 48 are respectively a sectional view, a top view and a bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate has a raised edge.

In this embodiment, a raised edge is disposed on the top surface of the structure. For the sake of brevity, all relevant descriptions of the heat conducting plate 80 that are applicable to this embodiment are incorporated here, and the same descriptions will not be repeated. Likewise, components of the heat conducting plate in this embodiment are similar to those of the heat conducting plate 80 , and corresponding reference numerals are used.

The heat conducting plate 94 includes an adhesive layer 30 , a substrate 34 , a wire 70 , a heat sink 72 and a raised edge 78 . The substrate 34 includes a dielectric layer 38 and a conductive layer 36 . The wire 70 includes the covered through-hole 52 , the pad 60 and the terminal 66 . The heat sink 72 includes the bump 16 , the flange layer 62 and the base 64 .

The raised edge 78 is a square frame that contacts the pad 60 and extends above the pad 60 . Both the protrusion 16 and the flange layer 62 are located in the center of the periphery of the raised edge 78 . For example, the height of the raised edge 78 is 600 microns, the width (the distance between the inner sidewall and the outer sidewall) is 1000 microns, and the lateral distance between the raised edge 78 and the flange layer 62 is 500 microns.

The raised edge 78 includes a solder resist green paint, a laminate and a film adhesive; but for the convenience of illustration, the raised edge 78 is only shown as a single layer in the figure. The solder resist green paint contacts the laminate and extends over it, thereby forming a top surface. The film-like adhesive contacts the laminated body and extends below it, thus forming a bottom surface. The laminate is in contact with and pressed between the solder resist green paint and the film adhesive. The solder resist green paint, the composite body and the film adhesive are all electrical insulators. For example, the solder resist green paint is 50 microns thick, the lamination is 500 microns thick, and the film adhesive is 50 microns thick. Therefore, the height of the raised edge 78 is 600 microns (50+500+50).

The laminate can be various dielectric films made of various organic and inorganic electrical insulators. For example, the laminate can be polyimide or FR-4 epoxy, although other epoxies such as polyfunctional and bismaleimide-triazine (BT) can also be used. Alternatively, raised edge 78 may comprise a metal ring on the film adhesive.

Thermally conductive plate 94 may be fabricated in a manner similar to thermally conductive plate 80, with appropriate adjustments to raised edge 78. For example, the adhesive layer 30 is disposed on the outreach platform 18 first, and then the substrate 34 is disposed on the adhesive layer 30 . Heat and pressurize the adhesive layer 30 to make the adhesive layer 30 flow and solidify. The lateral surfaces of the bump 16, the adhesive layer 30, and the conductive layer 36 are planarized by grinding, and then the outrigger platform 18, the adhesive layer 30, the conductive layer 36, and the dielectric layer 38 are drilled to form holes 44, and then the coating layer 48 , 50 and coated perforations 52 are deposited on the structure in the manner described above. The overhanging platform 18 and upper cladding layer 48 are then etched to form pads 60 and flange layer 62, the conductive layer 36 and lower cladding layer 50 are etched to form bases 64 and terminals 66, and raised edges 78 are then placed on top of the structure. noodle. Then, surface treatment is performed on the covered contact 74 as the bump 16 , the pad 60 , the flange layer 62 , the base 64 and the terminal 66 . Finally, cutting or splitting the adhesive layer 30 and the substrate 34 at the peripheral edge of the heat conducting plate 94 separates the heat conducting plate 94 from other heat conducting plates produced in the same batch.

Fig. 49, Fig. 50 and Fig. 51 are respectively a sectional view, a top view and a bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate, a semiconductor element and a packaging material.

In this embodiment, the semiconductor element is a blue light-emitting LED chip, which is disposed on the bump, and is electrically connected to the welding pad by a bonding wire, and is thermally connected to the bump by a die-bonding material. The LED chip is covered by an encapsulation material that converts blue light into white light.

The semiconductor chip assembly body 100 includes a heat conducting plate 80 , an LED chip 102 , a bonding wire 104 , a die-bonding material 106 and a packaging material 108 . The LED chip 102 includes a top surface 110 , a bottom surface 112 and a bonding pad 114 . The top surface 110 is the active surface and includes the wire bonding pads 114, while the bottom surface 112 is the thermal contact surface.

The LED chip 102 is disposed on the heat sink 72 , electrically connected to the wire 70 , and thermally connected to the heat sink 72 . In detail, the LED chip 102 is disposed on the bump 16 , overlaps the bump 16 but does not overlap the substrate 34 or the wire 70 . The LED chip 102 is laterally surrounded by the bump 16 and the adhesive layer 30 , and is electrically connected to the pad 60 through the bonding wire 104 , and is thermally connected and mechanically adhered to the bump 16 by the die-bonding material 106 . In addition, the bump 16 covers the LED chip 102 from below, and provides a concave die seat and a reflector for the LED chip 102 .

The thickness of the LED chip 102 is 150 microns, and the thickness of the die-bonding material 106 is 25 microns. Therefore, the bonding height between the LED chip 102 and the die-bonding material 106 below is 175 microns, which is less than the depth of the cavity 20 (250 microns). 75 microns. The length and width of the LED chip 102 are both 500 microns.

Both the LED chip 102 and the die-bonding material 106 are located in the cavity 20 , the bonding wire 104 and the packaging material 108 are both extended inside and outside the cavity 20 , and the substrate 34 and the wire 70 are located outside the cavity 20 . The bonding wire 104 is connected to and electrically connected to the bonding pad 60 and the bonding pad 114 , thereby electrically connecting the LED chip 102 to the terminal 66 . The die-bonding material 106 contacts and is located between the bump 16 and the thermal contact surface 112 , and thermally connects and mechanically bonds the bump 16 to the thermal contact surface 112 , thereby thermally connecting the LED chip 102 to the submount 64 .

The encapsulation material 108 is a solid electrical insulating and protective coating for color conversion, which can provide environmental protection for the LED chip 102 and the bonding wire 104 against moisture and particles. The packaging material 108 contacts the bump 16, the LED chip 102, the bonding wire 104 and the die-bonding material 106 in the cavity 20, and contacts the dielectric layer 38, the welding pad 60 and the flange layer 62 outside the cavity 20, but the packaging material 108 maintains a distance from the adhesive layer 30 , the covering through hole 52 , the base 64 and the terminal 66 . The encapsulation material 108 fills up the remaining space in the cavity 20 and seals the LED chip 102 in the cavity 20 . In addition, the encapsulation material 108 covers the bump 16 , the flange layer 62 , the LED chip 102 , the bonding wire 104 and the die-bonding material 106 from above.

The pad 60 is provided with a nickel/silver covered metal pad to facilitate stable bonding with the bonding wire 104 , so as to improve signal transmission from the wire 70 to the LED chip 102 . The bump 16 is also provided with nickel/silver covered metal pads to facilitate firm bonding with the die-bonding material 106 , thereby improving heat transfer from the LED chip 102 to the heat sink 72 . In addition, nickel/silver coated metal pads are also disposed on the flange layer 62 . Therefore, the bump 16 , the bonding pad 60 and the flange layer 62 provide a highly reflective surface, which can reflect the light emitted by the LED chip 102 to the silver surface layer, thereby increasing the amount of light emitted upward.

The LED chip 102 is a compound semiconductor that can emit blue light, has high luminous efficiency, and forms a p-n junction. Applicable compound semiconductors include gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), gallium arsenide phosphide (GaAsP), gallium aluminum phosphide (GaAlP), gallium aluminum arsenide (GaAlAs), Indium Phosphide (InP) and Indium Gallium Phosphide (InGaP). In addition, the LED chip 102 has a high light output but also generates considerable heat energy.

Encapsulation material 108 includes transparent silicone and yellow phosphor (indicated by black dots in FIG. 49 ). For example, the silicone resin can be polysiloxane resin, and the yellow phosphor can be cerium-doped yttrium aluminum garnet (Ce:YAG) fluorescent powder. The yellow phosphor emits yellow light when irradiated by blue light, and the blue and yellow light mix to form white light. Therefore, the packaging material 108 can convert the blue light emitted by the LED chip 102 into white light, so that the semiconductor chip assembly 100 becomes a white light source. In addition, the encapsulation material 108 is in the shape of a hemispherical dome, which can provide a convex refraction surface to concentrate the white light upward.

To manufacture the semiconductor chip assembly body 100 , the LED chip 102 can be disposed on the bump 16 using the die-bonding material 106 , and then the bonding pad 60 and the bonding pad 114 are bonded by the wire bonding 104 , and finally the packaging material 108 is shaped.

For example, the die-bonding material 106 is originally a silver-containing epoxy resin paste with high thermal conductivity, and is selectively printed on a portion of the bump 16 inside the cavity 20 by screen printing. Then, the LED chips 102 are placed on the silver epoxy paste in a step-and-repeat manner by using a pick-up head and an automatic pattern recognition system. Then heat the epoxy resin silver paste to harden at a relatively low temperature (eg, 190° C.) to complete the die bonding. The bonding wire 104 is a gold wire, which is then thermosonically connected to the bonding pad 60 and the bonding pad 114 . Finally, the encapsulation material 108 is molded on the structure.

The LED chip 102 can be electrically connected to the pad 60 through various connection media, thermally connected and mechanically adhered to the heat sink 72 by various thermal adhesives, and packaged with various packaging materials.

The semiconductor chip assembly 100 is a first level single crystal package.

Fig. 52, Fig. 53 and Fig. 54 are respectively the sectional view, top view and bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate, a semiconductor element, a packaging material and a lens .

In this embodiment, the semiconductor element is covered by a color-changing packaging material and a transparent lens. For the sake of brevity, all relevant descriptions of the semiconductor chip assembly body 100 that are applicable to this embodiment are incorporated herein, and the same descriptions will not be repeated. Similarly, the components of the semiconductor chip set body in this embodiment are similar to the components of the semiconductor chip set body 100 , and the corresponding reference numerals are used, but the base number of the coding is changed from 100 to 200. For example, the LED chip 202 corresponds to the LED chip 102, the bonding wire 204 corresponds to the bonding wire 104, and so on.

The semiconductor chip assembly body 200 includes a heat conducting plate 80 , an LED chip 202 , a bonding wire 204 , a die-bonding material 206 , a packaging material 208 and a lens 216 . The LED chip 202 includes a top surface 210 , a bottom surface 212 and a bonding pad 214 . The top surface 210 is the active surface and includes the wire bonding pads 214, while the bottom surface 212 is the thermal contact surface.

The LED chip 202 is disposed on the heat sink 72 , electrically connected to the wire 70 , and thermally connected to the heat sink 72 . In detail, the LED chip 202 is disposed on the bump 16 , is electrically connected to the pad 60 through the bonding wire 204 , and is thermally connected and mechanically adhered to the bump 16 through the die-bonding material 206 .

The packaging material 208 contacts the bump 16 , the LED chip 202 , the bonding wire 204 and the die-bonding material 206 in the cavity 20 , but keeps a distance from the adhesive layer 30 , the dielectric layer 38 , the base 64 and the wire 70 . The packaging material 208 fills up the remaining space in the cavity 20 , seals the LED chip 202 in the cavity 20 , and covers the LED chip 202 from above. Encapsulation material 208 extends 10 microns above cavity 20 and is limited in lateral extent by cavity 20 . In addition, the encapsulation material 208 is almost entirely within the cavity 20 and only partially protects the bond wires 204 . Since the cavity 20 has a stamped, precisely controlled and well-defined space, only a small amount of encapsulating material 208 needs to be applied, and the amount is fixed.

The lens 216 is a transparent plastic cover with a curved hollow dome (similar to a hemisphere) on the top surface of the structure, which can provide environmental protection such as moisture resistance and particle resistance for the bonding wire 204 and the packaging material 208 . The lens 216 contacts the pad 60 , but keeps a distance from the adhesive layer 30 , the dielectric layer 38 , the covered through hole 52 , the terminal 66 , the heat sink 72 , the LED chip 202 , the bonding wire 204 , the die-bonding material 206 and the packaging material 208 . The lens 216 covers the bump 16 , the flange layer 62 , the LED chip 202 , the bonding wire 204 , the die-bonding material 206 and the packaging material 208 from above. In addition, the lens 216 contains transparent plastic but does not contain fluorescent powder, so it cannot convert light color.

The blue light emitted by the LED chip 202 is converted into white light by the encapsulation material 208 and then emitted through the lens 216 , thus making the semiconductor chip assembly 200 a white light source. In addition, the convex refraction surface formed by the hemispherical dome of the lens 216 can concentrate the white light emitted by the packaging material 208 upward. Since the volume of the encapsulation material 208 is much smaller than that of the encapsulation material 108, and the lens 216 does not need to contain phosphor or fluorescent powder, this structure is very cost-effective.

If it is desired to manufacture the semiconductor chip assembly body 200 , the LED chip 202 can be disposed on the bump 16 by using the die-bonding material 206 , and then the bonding pad 60 and the bonding pad 214 are bonded by wire. Then, by screen printing, or by step-and-repeat application through a nozzle, an encapsulation material 208 in the form of A-stage (A-stage) uncured epoxy resin is deposited in the cavity 20 and the LED chip 202 is bonded to the printed film. on line 204. The liquid epoxy will fill the remaining space in the cavity 20 and extend slightly above the cavity 20, where the cavity 20 acts as a dam to limit the lateral extent of the liquid epoxy. Then heat the liquid epoxy resin at a relatively low temperature (such as 190°C) to harden it, thereby converting the liquid A-stage (A-stage) uncured epoxy resin into a C-stage (C-stage) curing or hardening epoxy resin. Finally, the lens 216 is disposed on the structure.

The semiconductor chip assembly 200 is a first level single crystal package.

Fig. 55, Fig. 56 and Fig. 57 are respectively the cross-sectional view, top view and bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate, a semiconductor element and double-layer packaging materials.

In this embodiment, the semiconductor element is covered by a color-changing encapsulation material and a transparent encapsulation material. For the sake of brevity, all relevant descriptions of the semiconductor chip assembly body 200 that are applicable to this embodiment are incorporated herein, and the same descriptions will not be repeated. Similarly, the components of the semiconductor chip set body in this embodiment are similar to the components of the semiconductor chip set body 200 , and the corresponding reference numerals are used, but the base number of the codes is changed from 200 to 300. For example, the LED chip 302 corresponds to the LED chip 202, the bonding wire 304 corresponds to the bonding wire 204, and so on.

The semiconductor chip assembly body 300 includes a heat conducting plate 80 , an LED chip 302 , a bonding wire 304 , a die-bonding material 306 and packaging materials 308 , 318 . The LED chip 302 includes a top surface 310 , a bottom surface 312 and a bonding pad 314 . The top surface 310 is the active surface and includes the wire bonding pads 314, while the bottom surface 312 is the thermal contact surface.

The LED chip 302 is disposed on the heat sink 72 , electrically connected to the wire 70 , and thermally connected to the heat sink 72 . In detail, the LED chip 302 is disposed on the bump 16 , electrically connected to the pad 60 through the bonding wire 304 , and thermally connected and mechanically adhered to the bump 16 through the die-bonding material 306 .

The encapsulation material 308 covers the LED chip 302 from above and is located almost entirely within the cavity 20 .

The encapsulation material 318 is a solid electrical insulating transparent protective coating, which can provide environmental protection for the bonding wire 304 and the encapsulation material 308 against moisture and particles. The encapsulation material 318 is in contact with the adhesive layer 30, the solder pad 60, the flange layer 62, the bonding wire 304 and the encapsulation material 308, but is in contact with the bump 16, the dielectric layer 38, the covered through hole 52, the base 64, the terminal 66, and the LED chip 302. and the die-bonding material 306 to keep a distance. The encapsulation material 318 covers the bump 16 , the flange layer 62 , the LED chip 302 , the bonding wire 304 , the die-bonding material 306 and the encapsulation material 308 from above. In addition, the encapsulation material 318 contains transparent silicone resin but does not contain fluorescent powder, so it cannot convert light color.

The blue light emitted by the LED chip 302 is converted into white light by the encapsulation material 308 , and then passes through the encapsulation material 318 to emit light, thus making the semiconductor chip assembly 300 a white light source. In addition, since the encapsulation material 318 is in the shape of a hemispherical dome, the convex refraction surface formed therein can concentrate the white light emitted by the encapsulation material 318 upward. Furthermore, since the volume of the encapsulation material 308 is much smaller than that of the encapsulation material 108, and the encapsulation material 318 does not need to contain phosphor or fluorescent powder, this structure is very cost-effective.

If it is desired to manufacture the semiconductor chip assembly body 300 , the LED chip 302 can be disposed on the bump 16 by using the die-bonding material 306 , and then the bonding pad 60 and the bonding pad 314 are bonded by wire. Then, the cavity 20 is used as a dam, and the encapsulation material 308 is deposited therein and cured to shape, and finally the encapsulation material 318 is molded into shape.

The semiconductor chip assembly 300 is a first level single crystal package.

Fig. 58, Fig. 59 and Fig. 60 are respectively the sectional view, the top view and the bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate with a raised edge, a semiconductor element and a double layer packaging material.

In this embodiment, the semiconductor element is covered by a color-changing encapsulation material and a transparent encapsulation material. For the sake of brevity, all relevant descriptions of the semiconductor chip assembly body 300 that are applicable to this embodiment are incorporated herein, and the same descriptions will not be repeated. Similarly, the components of the semiconductor chip set body in this embodiment are similar to the components of the semiconductor chip set body 300 , and the corresponding reference numerals are used, but the base number of the coding is changed from 300 to 400. For example, the LED chip 402 corresponds to the LED chip 302, the bonding wire 404 corresponds to the bonding wire 304, and so on.

The semiconductor chip assembly body 400 includes a heat conducting plate 94 , an LED chip 402 , a wire bonding 404 , a die-bonding material 406 and packaging materials 408 , 418 . The LED chip 402 includes a top surface 410 , a bottom surface 412 and a bonding pad 414 . The top surface 410 is the active surface and includes the wire bonding pads 414, while the bottom surface 412 is the thermal contact surface.

The LED chip 402 is disposed on the heat sink 72 , electrically connected to the wire 70 , and thermally connected to the heat sink 72 . In detail, the LED chip 402 is disposed on the bump 16 , electrically connected to the pad 60 through the bonding wire 404 , and thermally connected and mechanically adhered to the bump 16 through the die-bonding material 406 .

The encapsulation material 408 covers the LED chip 402 from above and is located almost entirely within the cavity 20 . The encapsulation material 418 covers the bonding wire 404 and the encapsulation material 408 from above, and is located outside the cavity 20 . Encapsulating material 418 also contacts raised edge 78 and is limited in lateral extent by raised edge 78 .

The blue light emitted by the LED chip 402 is converted into white light by the encapsulation material 408 and then emitted through the encapsulation material 418 , thus making the semiconductor chip assembly 400 a white light source.

To manufacture the semiconductor chip assembly body 400 , the LED chip 402 can be disposed on the bump 16 by using the die-bonding material 406 , and then the bonding pad 60 and the bonding pad 414 are bonded by wire. Next, the cavity 20 is used as a dam, and the encapsulation material 408 is deposited therein and cured to form it. Finally, the raised edge 78 is used as a dam, and the encapsulation material 418 is deposited therein and solidified.

The semiconductor chip assembly 400 is a first level single crystal package.

Fig. 61, Fig. 62 and Fig. 63 are respectively the sectional view, top view and bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate with raised edges, a semiconductor element, and a package Materials and a cover.

In this embodiment, the semiconductor element is covered by a color-changing encapsulation material and a transparent upper cover. For the sake of brevity, all relevant descriptions of the semiconductor chip assembly body 400 applicable to this embodiment are incorporated herein, and the same descriptions are not repeated. Similarly, the components of the semiconductor chip set body in this embodiment are similar to the components of the semiconductor chip set body 400 , and the corresponding reference numerals are used, but the base number of the coding is changed from 400 to 500. For example, the LED chip 502 corresponds to the LED chip 402, the bonding wire 504 corresponds to the bonding wire 404, and so on.

The semiconductor chip assembly body 500 includes a heat conducting plate 94 , an LED chip 502 , a bonding wire 504 , a die-bonding material 506 , a package material 508 and a cover 520 . The LED chip 502 includes a top surface 510 , a bottom surface 512 and a bonding pad 514 . The top surface 510 is the active surface and includes the wire bonding pads 514, while the bottom surface 512 is the thermal contact surface.

The LED chip 502 is disposed on the heat sink 72 , electrically connected to the wire 70 , and thermally connected to the heat sink 72 . In detail, the LED chip 502 is disposed on the bump 16 , is electrically connected to the pad 60 through the bonding wire 504 , and is thermally connected and mechanically adhered to the bump 16 through the die-bonding material 506 .

The encapsulation material 508 covers the LED chip 502 from above and is located almost entirely within the cavity 20 .

The upper cover 520 is a glass plate disposed on the raised edge 78 , which can provide environmental protection for the wire bonding 504 and the packaging material 508 against moisture and particles. The upper cover 520 contacts the raised edge 78 , but keeps a distance from the adhesive layer 30 , the dielectric layer 38 , the wire 70 , the heat sink 72 , the LED chip 502 , the bonding wire 504 , the die-bonding material 506 and the packaging material 508 . The upper cover 520 covers the bump 16 , the flange layer 62 , the LED chip 502 , the bonding wire 504 , the die-bonding material 506 and the packaging material 508 from above. In addition, the upper cover 520 contains transparent glass but does not contain fluorescent powder, so it cannot convert light color.

The blue light emitted by the LED chip 502 is converted into white light by the encapsulation material 508 and then emitted through the upper cover 520 , thus making the semiconductor chip assembly 500 a white light source.

To manufacture the semiconductor chip assembly body 500 , the LED chip 502 can be disposed on the bump 16 by using the die-bonding material 506 , and then the bonding pad 60 and the bonding pad 514 are bonded by wire. Next, the cavity 20 is used as a dam, and the encapsulation material 508 is deposited therein and cured to form it. Finally, the upper cover 520 is disposed on the raised edge 78 .

The semiconductor chip assembly 500 is a first level single crystal package.

Fig. 64, Fig. 65 and Fig. 66 are respectively the sectional view, top view and bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate with raised edges, a semiconductor element and an upper build.

In this embodiment, the semiconductor element is a white light-emitting LED chip, and is covered by a transparent upper cover. For the sake of brevity, all relevant descriptions of the semiconductor chip assembly body 500 that are applicable to this embodiment are incorporated herein, and the same descriptions will not be repeated. Similarly, the components of the semiconductor chip set body in this embodiment are similar to those of the semiconductor chip set body 500 , and the corresponding reference numerals are used, but the base number of the coding is changed from 500 to 600. For example, the LED chip 602 corresponds to the LED chip 502, the bonding wire 604 corresponds to the bonding wire 504, and so on.

The semiconductor chip assembly body 600 includes a heat conducting plate 94 , an LED chip 602 , a bonding wire 604 , a die-bonding material 606 and an upper cover 620 . The LED chip 602 includes a top surface 610 , a bottom surface 612 and a bonding pad 614 . The top surface 610 is the active surface and contains the wire bonding pads 614, while the bottom surface 612 is the thermal contact surface.

The LED chip 602 is disposed on the heat sink 72 , electrically connected to the wire 70 , and thermally connected to the heat sink 72 . In detail, the LED chip 602 is disposed on the bump 16 , electrically connected to the pad 60 through the bonding wire 604 , and thermally connected and mechanically adhered to the bump 16 by the die-bonding material 606 .

The upper cover 620 is a glass plate disposed on the raised edge 78 , which can provide environmental protection for the LED chips 602 and the bonding wires 604 against moisture and particles. The upper cover 620 contacts the raised edge 78 , but keeps a distance from the adhesive layer 30 , the dielectric layer 38 , the wire 70 , the heat sink 72 , the LED chip 602 , the bonding wire 604 and the die-bonding material 606 . The upper cover 620 covers the bump 16 , the flange layer 62 , the LED chip 602 , the bonding wire 604 and the die-bonding material 606 from above. In addition, the upper cover 620 contains transparent glass but does not contain fluorescent powder, so it cannot convert light color.

The white light emitted by the LED chip 602 passes through the upper cover 620 and emits light. Therefore, the semiconductor chip assembly body 600 is a white light source.

To manufacture the semiconductor chip assembly body 600 , the LED chip 602 can be disposed on the bump 16 by using the die-bonding material 606 , and then the bonding pad 60 and the bonding pad 614 can be bonded by wire. Finally, the upper cover 620 is disposed on the raised edge 78 .

The semiconductor chip assembly 600 is a first-level single crystal package.

The above-mentioned semiconductor chip assembly body and heat conduction plate are only illustrative examples, and the present invention can also be realized through other various embodiments. In addition, the above-mentioned embodiments can be mixed and matched with each other or used with other embodiments according to design and reliability considerations. For example, the substrate may include multiple sets of single-layer wires and multiple sets of multi-layer wires. The heat conducting plate may include a plurality of bumps, and the bumps are arranged in an array for use by a plurality of semiconductor elements. In addition, the heat conducting plate may contain more wires to accommodate additional semiconductor components. The heat conducting plate may also include a solder resist green paint extending above the solder pad, the bump and the flange layer and selectively exposing them, and a raised edge is provided on the solder resist green paint. The heat conducting plate may also include coated perforations on the peripheral edge and embedded solder resist green paint. The semiconductor element can be covered by a transparent, semi-transparent or opaque encapsulation material in the first vertical direction, and/or covered by a transparent, semi-transparent or opaque upper cover. For example, the semiconductor element in this case can be a blue light-emitting LED chip, and is covered by a transparent encapsulation material or an upper cover, so that the semiconductor chip assembly becomes a blue light source; or, the LED chip is made of a color-changing Covered with packaging material or upper cover, thus making the semiconductor chip assembly a green, red or white light source. Likewise, the semiconductor device of this application can be an LED package with multiple LED chips, and the heat conduction plate can include more wires to match additional LED chips.

The semiconductor element of this case can use a heat dissipation seat alone, or share a heat dissipation seat with other semiconductor elements. For example, a single semiconductor device can be disposed on a heat sink, or multiple semiconductor devices can be disposed on a heat sink. For example, four small chips arranged in a 2×2 array can be attached to the bumps, and additional wires can be provided on the substrate to match the electrical connections of the chips. This approach is far more economical than disposing a tiny bump on each chip.

The semiconductor chip in this case may be optical or non-optical. For example, the chip can be an LED, an infrared (IR) detector, a solar cell, a microprocessor, a controller, or a radio frequency (RF) power amplifier. Likewise, the semiconductor package in this application can be an LED package or a radio frequency module. Therefore, the semiconductor device of this application can be a packaged or unpackaged optical or non-optical chip. In addition, various connection media can be used to mechanically, electrically and thermally connect the semiconductor element to the thermally conductive plate, including soldering and using conductive and/or thermally conductive adhesives.

The heat sink in this case can quickly, effectively and evenly dissipate the heat energy generated by the semiconductor element to the semiconductor chip assembly of the next layer without passing the heat flow through the adhesive layer, the substrate or other places on the heat conduction plate. This allows the use of an adhesive layer with lower thermal conductivity, resulting in a significant cost reduction. The heat sink may include an integral bump and flange layer, and a base metallurgically bonded and thermally connected to the bump, thereby increasing reliability and reducing cost. In addition, the bump can be customized according to the semiconductor element, and the base can be customized according to the semiconductor chip assembly of the next layer, so as to strengthen the thermal connection from the semiconductor element to the semiconductor chip assembly of the next layer. For example, the bottom plate of the bump can be square or rectangular, and the side shape of the bump can be the same or similar to that of the thermal contact of the semiconductor element. In any of the above designs, the heat sink can be constructed of a variety of different thermally conductive metals.

The heat sink can be electrically connected or electrically isolated from the semiconductor element and the substrate. For example, the die-bonding material can be conductive, or a routing line above the adhesive layer and the dielectric layer can electrically connect the pad and the flange layer, or a routing line below the adhesive layer and the dielectric layer can be The base is electrically connected with the terminal so as to electrically connect the heat sink to the semiconductor element. The heat sink can be further electrically grounded so as to electrically ground the semiconductor element.

The bumps can be integrally formed with the flange layer, thus being a single metal body (eg, copper or aluminum). The bump can also be integrally formed with the flange layer so that the interface between the two consists of a single metal (such as copper) and other metals elsewhere (such as a covered contact). The bumps can also be integrated with the flange layer so that the interface between the two consists of multiple layers of a single metal body (eg a nickel buffer layer on an aluminum core and a copper layer on top of the nickel buffer layer).

The base provides mechanical support for the substrate. For example, the pedestal prevents the substrate from warping during metal grinding, chip placement, wire bonding, and molding packaging materials. Additionally, the back of the base may include fins protruding in a downward direction. For example, the fins can be formed by cutting the exposed lateral surfaces of the base using a board drill to form lateral grooves. In this example, the thickness of the base can be 500 microns, and the depth of the aforementioned grooves can be 300 microns, that is to say, the height of the fins can be 300 microns. The fins increase the surface area of the base, and if the fins are exposed to the air rather than being disposed on a heat sink, improve the thermal conductivity of the base via convection.

After the adhesive layer is cured, the base can be made by a variety of deposition techniques, including electroplating, electroless coating, evaporation and sputtering to form a single-layer or multi-layer structure. The base can be made of the same or different metal material as the protrusion. Additionally, the pedestal can span the via and extend to the substrate, or sit within the perimeter of the via. Accordingly, the base may contact the substrate or be at a distance from the substrate. In either case, the base adjoins the protrusion and extends perpendicularly from the protrusion in a direction away from the recess.

The adhesive layer in this case can provide a strong mechanical connection between the heat sink and the substrate. For example, the adhesive layer can extend laterally from the bump and over the wire, and finally to the peripheral edge of the semiconductor chip package body. The adhesive layer can fill the space between the heat sink and the substrate, and is a non-hole structure with evenly distributed bonding lines. The adhesive layer can also absorb the mismatch between the heat sink and the substrate due to thermal expansion. The material of the adhesive layer can be the same as or different from that of the dielectric layer. In addition, the adhesive layer can be a low-cost dielectric and does not need to have high thermal conductivity. Furthermore, the adhesive layer in this case is not easy to delaminate.

The thickness of the adhesive layer can be adjusted so that the adhesive layer substantially fills the gap and almost all of the adhesive is located within the structure after curing and/or grinding. For example, the ideal film thickness can be determined by trial and error. Likewise, the thickness of the dielectric layer can also be adjusted to achieve this effect.

The substrate in this case can be a low-cost laminated structure and does not need to have high thermal conductivity. In addition, the substrate may comprise a single conductive layer or multiple conductive layers. Furthermore, the substrate may comprise or consist of a conductive layer.

The conductive layer can be separately disposed on the adhesive layer. For example, a through hole can be formed on the conductive layer first, and then the conductive layer is placed on the adhesive layer, so that the conductive layer contacts the adhesive layer and is exposed upward, and at the same time, the bump extends into the through hole, and exposed upward through the through hole. In this example, the thickness of the conductive layer can be 100 to 200 microns, such as 125 microns, which is thick enough so that it will not bend and shake during handling, and thin enough so that patterns can be formed without excessive etching .

The conductive layer and the dielectric layer can also be disposed on the adhesive layer together. For example, the conductive layer can be disposed on the dielectric layer first, then via holes are formed on the conductive layer and the dielectric layer, and then the conductive layer and the dielectric layer are disposed on the adhesive layer, so that the conductive layer faces exposed in the upward direction, and make the dielectric layer contact and between the conductive layer and the adhesive layer, thereby separating the conductive layer from the adhesive layer, at the same time, the bump extends into the through hole and passes through The through hole is exposed upward. In this example, the thickness of the conductive layer can be 10 to 50 microns, such as 30 microns, which is thick enough to provide reliable signal transmission and thin enough to reduce weight and cost. In addition, the dielectric layer is always a part of the thermally conductive plate.

The conductive layer and a carrier can also be disposed on the adhesive layer at the same time. For example, a thin film can be used to adhere the conductive layer to a carrier such as double-oriented polyethylene terephthalate film (Mylar), and then only through holes are formed on the conductive layer instead of the carrier, and then the The conductive layer and the carrier are arranged on the adhesive layer, so that the carrier covers the conductive layer and is exposed upward, and the film is in contact with and interposed between the carrier and the conductive layer, and the conductive layer is in contact with and interposed between the conductive layer. Between the film and the adhesive layer, at the same time, the bump is aligned with the through hole and is covered by the carrier from above. After the adhesive layer is cured, the film can be decomposed by ultraviolet light, so as to peel off the carrier from the conductive layer, so that the conductive layer is exposed upward, and then the conductive layer can be ground and patterned to form a substrate. seat and terminals. In this example, the thickness of the conductive layer can be 10 to 50 microns, such as 30 microns, which is thick enough to provide reliable signal transmission on the one hand, and thin enough to reduce weight and cost on the other hand; as for the carrier The thickness can be 300 to 500 microns, which is thick enough so that it will not bend and shake during handling, and thin enough to help reduce weight and cost. The carrier is only a temporary fixture and is not a permanent part of the heat conducting plate.

The pads and terminals can adopt various packaging forms depending on the needs of the semiconductor element and the semiconductor chip assembly of the next layer.

Pads and terminals can be formed by a variety of deposition techniques before or after the substrate is placed on the adhesive layer, including electroplating, electroless coating, evaporation and sputtering to form a single-layer or multi-layer structure. For example, the pattern of the conductive layer can be formed on the substrate before the substrate is disposed on the adhesive layer, or after the substrate is adhered to the bumps and the overhanging platforms by the adhesive layer, so as to form the terminals. Likewise, the pad and flange layers can be formed by patterning the overhanging mesa before the plated through holes are formed.

The process of surface treatment with covered contacts can be performed before or after the formation of pads and terminals. For example, the covering layer can be etched first to form pads, terminals, bases and flange layers, and then the covered contacts can be deposited on the covering layers; or the covered contacts can be deposited on the covering layers first, and then etched. The coating layers form the pad, the terminal, the base and the flange layer.

The raised edges of this case are available with or without reflective, transparent or opaque. For example, the raised edge may include highly reflective metals such as silver and aluminum, and has an inclined inner surface, so as to reflect the light irradiated on the inner surface toward the upward direction, thereby increasing the amount of light emitted toward the upward direction. Likewise, the raised edge may comprise a transparent material such as glass, or a non-reflective, opaque, and low cost material such as epoxy. Additionally, reflective raised edges may be used regardless of whether the raised edges contact or limit the encapsulation material.

The encapsulation material (or double-layer encapsulation material) of this case can be a variety of transparent, translucent or opaque materials, and can have different shapes and sizes. For example, the encapsulation material can be transparent silicone, epoxy or a combination thereof. Silicone resin is better than epoxy resin in terms of heat conduction and color stability, but silicone resin has higher cost, lower hardness and poor adhesion.

The top cover of this case can overlap or replace the packaging material. The top cover seals the die and wirebonds and provides environmental protection for both such as moisture and particles. The cover can be made from a variety of transparent, translucent or opaque materials and can have different shapes and sizes. For example, the upper cover can be clear glass or silicon dioxide.

The lens in this case can overlap or replace the encapsulation material. The lens hermetically encapsulates the die and wirebonds and provides both environmental protection such as moisture and particulate resistance. The lens can also provide a convex refracting surface to concentrate the light upward. Lenses can be made from a variety of transparent, translucent, or opaque materials, and can have different shapes and sizes. For example, a hollow hemispherical dome-shaped glass lens can be arranged on the heat conducting plate, and the lens can be kept at a distance from the packaging material; Heat conducting plates keep distance.

The wires in this case can include additional pads, terminals, covered vias, routing lines, conductive vias, and passive components, and can take different configurations. Wires can serve as signal layers, power layers, or ground layers, depending on the purpose of their corresponding semiconductor component pads. The wires may also comprise various conductive metals such as copper, gold, nickel, silver, palladium, tin, mixtures thereof, and alloys thereof. The ideal composition depends not only on the nature of the external connection medium, but also on design and reliability considerations. In addition, those skilled in the art should be able to understand that the copper used in the semiconductor chip assembly in this case can be pure copper, but it is usually an alloy dominated by copper, such as copper-zirconium (99.9% copper), copper-silver - Phosphorus-magnesium (99.7% copper) and copper-tin-iron-phosphorus (99.7% copper) to improve mechanical properties such as tensile strength and ductility.

In general, it is preferable to have the dielectric layer, covered via, upper and lower covered layers, covered contacts, solder resist green paint, packaging material, lens, raised edge and upper cover, but in some embodiments Can be omitted. For example, if only a single layer of signal routing is used, the dielectric layer can be omitted to reduce cost. If the light emitted by the LED chip is originally the desired color, the encapsulation material used for color conversion can be omitted. Likewise, if a transparent encapsulant is molded onto the thermally conductive plate and the lateral extent of the transparent encapsulant is limited by dimples (or no encapsulant is provided at all), and no reflector is required, the raised edge can be omitted.

The heat conduction plate in this case may include a heat conduction hole, the heat conduction hole is kept at a distance from the bump, and extends outside the opening and the through hole through the adhesive layer and the dielectric layer, and at the same time adjoins and thermally connects the base and the flange layer, Thereby, the heat dissipation effect from the flange layer to the base is improved, and the heat energy is diffused in the base.

The semiconductor chip assembly in this case can provide horizontal or vertical single-layer or multi-layer signal routing.

U.S. Patent Application No. 12/616,773 filed by Lin Wenqiang et al. on November 11, 2009: "Semiconductor chip assembly with heat sink and substrate with bosses/pedestals" discloses a horizontal single-layer signal Routing Structures Where Pads, Terminals, and Routing Lines Are All Over a Dielectric Layer, the contents of this US patent application are hereby incorporated by reference.

US Patent Application No. 12/616,775 filed by Lin Wenqiang et al. on November 11, 2009: "Semiconductor chip assembly with heat sink and wires with bosses/pedestals" discloses another horizontal single-layer Signal Routing Structures Where Pads, Terminals, and Routing Lines are Over Adhesive Layers and No Dielectric Layer Is Provided, The contents of this US patent application are hereby incorporated herein by reference.

No. 12/557,540 U.S. patent application filed by Wang Jiazhong et al. on September 11, 2009: "Semiconductor chip assembly with heat sink with boss/pedestal and horizontal signal routing" discloses a multi-horizontal The structure of layer signal routing, wherein the pads and terminals above the dielectric layer are electrically connected by using the first and second conductive holes passing through the dielectric layer and the routing lines below the dielectric layer. This US patent The content of the application is hereby incorporated by reference.

The No. 12/557,541 U.S. patent application filed by Wang Jiazhong et al. on September 11, 2009: "Semiconductor chip assembly with heat sink with boss/pedestal and vertical signal routing" discloses a vertical The structure of multi-layer signal routing, wherein the pads above the dielectric layer and the terminals below the adhesive layer use the first conductive holes passing through the dielectric layer, the routing lines below the dielectric layer and the terminals passing through the adhesive layer The second conductive via makes the electrical connection, the content of this US patent application is hereby incorporated by reference.

The operating format of the heat conduction plate in this case can be single or multiple heat conduction plates, depending on the manufacturing design. For example, a single heat conducting plate can be fabricated separately. Alternatively, a single metal plate, a single adhesive layer, a single substrate, and a single coating layer can be used to manufacture multiple heat conducting plates in batches at the same time, and then separated. Similarly, for each heat conduction plate in the same batch, a single metal plate, a single adhesive layer, a single substrate, and a single coating layer can also be used to simultaneously batch-manufacture multiple sets of heat sinks and wires for a single semiconductor element.

For example, a plurality of bumps can be punched out on a metal plate; then an uncured adhesive layer with openings corresponding to the bumps can be placed on the overhanging platform so that each bump extends through a corresponding opening; A substrate having a single conductive layer, a single dielectric layer, and through holes corresponding to the bumps is then disposed on the adhesive layer such that each bump extends through a corresponding opening and into a corresponding through hole; Then use a pressure table to press the outrigger platform and the substrate against each other, forcing the adhesive layer into the gap between the bumps and the substrate in the through holes; then solidify the adhesive layer, and then grind the bumps block, the adhesive layer, and the conductive layer to form a lateral surface; then drill through the structure to form a plurality of holes; then place the coating on the structure to form upper and lower coatings, and respectively forming coated through-holes in the holes; then etching the overhanging platform and the upper cladding layer to form a plurality of flange layers corresponding to the bumps, and a plurality of pads corresponding to the covered through-holes; etching the conductive layer and the The lower coating layer is used to form a plurality of bases corresponding to the bumps, and a plurality of terminals corresponding to the covered through holes; and then the bumps, the bases, the flange layers, the covered contacts are formed The solder pads and the terminals are subjected to surface treatment; finally, the substrate and the adhesive layer are cut or split at appropriate positions on the peripheral edge of each heat conduction plate, so that individual heat conduction plates are separated from each other.

The operating format of the semiconductor chip set body in this case can be a single semiconductor chip set body or multiple semiconductor chip set bodies, depending on the manufacturing design. For example, a single semiconductor chip assembly body can be manufactured separately, or a plurality of semiconductor chip assembly bodies can be manufactured in batches at the same time, and then each heat conducting plate is separated one by one. Likewise, a plurality of semiconductor elements can also be electrically, thermally and mechanically connected to each heat conducting plate in mass production.

For example, a plurality of die-bonding materials can be respectively deposited in the cavities of a plurality of bumps, and then a plurality of chips are respectively placed on the die-bonding materials in the cavities, and then the die-bonding materials are heated simultaneously to harden them. And form multiple solid crystals. Then wire-bond the chips to the corresponding pads outside the cavities, deposit color-changing encapsulation materials on the chips and wires in the cavities, and heat the encapsulation materials at the same time to make them harden And become a color-switchable encapsulation material. After the transparent encapsulation material is molded on the encapsulation material for changing colors simultaneously, each heat conducting plate can be separated one by one.

The thermally conductive plates can be separated from each other in a single step or in multiple steps. For example, a plurality of heat conducting plates can be made into a flat plate in batches, and then a plurality of semiconductor elements are arranged on the flat plate, and then the plurality of semiconductor chip assemblies formed by the flat plate are separated one by one. Alternatively, a plurality of heat conduction plates can be made into a flat plate in batches, and then the plurality of heat conduction plates formed by the plate are cut into a plurality of heat conduction strips, and then a plurality of semiconductor elements are respectively arranged on the heat conduction strips , and finally separate the plurality of semiconductor chip assemblies formed by the heat-conducting slats into individuals. Additionally, mechanical cutting, laser cutting, cleaving, or other suitable techniques may be utilized in dividing the thermally conductive plate.

The semiconductor chip assembly of the present invention has several advantages. The semiconductor chipset has high reliability, low price and is very suitable for mass production. The semiconductor chip assembly is especially suitable for high-power semiconductor components that are prone to high heat and require excellent heat dissipation to operate effectively and reliably, such as LED chips, large semiconductor chips, and multiple small semiconductor components that are used simultaneously (for example, arranged in an array. multiple small semiconductor chips).

To sum up, the manufacturing process of this case is highly applicable, and combines various mature electrical connection, thermal connection and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing process in this case can be implemented without expensive tools. Therefore, this manufacturing process can greatly improve the yield, yield, performance and cost-effectiveness of existing packaging technologies. Furthermore, the semiconductor chip assembly of this case is very suitable for copper chips and lead-free environmental protection requirements.

Those skilled in the art can readily conceive of various variations and modifications to the embodiments described herein. For example, the aforementioned materials, dimensions, shapes, sizes, contents of steps and sequence of steps are just examples. These changes, adjustments and equivalent techniques can be carried out by the above-mentioned persons without departing from the spirit and scope of the present invention, and the scope of the present invention is defined by the scope of claims.

Claims (81)

1. a semiconductor chip group body comprises: semiconductor element, an adhesion layer, a radiating seat, and a lead; Wherein this adhesion layer has an opening, and radiating seat comprises a projection, a pedestal and a flange layer, and this lead comprises a weld pad and a terminal; It is characterized in that: this projection is in abutting connection with this pedestal and this flange layer, and is integrally formed with this flange layer, and this projection extends along one first vertical direction from this pedestal, and certainly this flange layer along second a vertical direction extension opposite with this first vertical direction; This pedestal extends along this second vertical direction from this projection; This flange layer is stretched along the side surface direction side perpendicular to these vertical direction from this projection, and keeps at a distance with this pedestal; In this projection, have one face this first vertical direction depression, this depression is to be covered by this projection on this second vertical direction, this projection is also separated this depression and this pedestal, this depression have one be positioned at this flange layer place inlet; Wherein this semiconductor element extends into this depression, and is electrically connected to this weld pad, thereby is electrically connected to this terminal, and this semiconductor element also is thermally coupled to this projection, thereby is thermally coupled to this pedestal; This adhesion layer this projection of contact and this flange layer, and this projection extends laterally to this terminal or crosses this terminal certainly; This lead is positioned at outside this depression; This projection extends into this opening, and covers this semiconductor element in this second vertical direction; This depression extends into this opening.

2. semiconductor chip group body according to claim 1 is characterized in that: this semiconductor element is a light-emitting diode chip for backlight unit.

3. semiconductor chip group body according to claim 1; It is characterized in that: this semiconductor element is to be positioned at this depression; Extend the inside and outside routing of this depression through one and be electrically connected to this weld pad, and through one be positioned at this depression solid brilliant material be thermally coupled to this projection.

4. semiconductor chip group body according to claim 1 is characterized in that: this this lead of adhesion layer contact.

5. semiconductor chip group body according to claim 1 is characterized in that: this adhesion layer side direction cover and around and similar shape be coated on a sidewall of this projection.

6. semiconductor chip group body according to claim 1 is characterized in that: this adhesion layer extends to the peripheral edge of this semiconductor chip group body.

7. semiconductor chip group body according to claim 1 is characterized in that: this projection and this adhesion layer are in this pedestal place copline.

8. semiconductor chip group body according to claim 1 is characterized in that: this projection comprises the first bending corner and second a bending corner in abutting connection with this flange layer in abutting connection with this pedestal.

9. semiconductor chip group body according to claim 1 is characterized in that: this projection has the peculiar inconsistent thickness that is stamped to form.

10. semiconductor chip group body according to claim 1 is characterized in that: this depression is contained the major part of this projection along said vertical direction and said side surface direction.

11. semiconductor chip group body according to claim 1 is characterized in that: this pedestal has the flat surfaces that a single thickness and one faces this second vertical direction.

12. semiconductor chip group body according to claim 1, it is characterized in that: this pedestal is stretched from this nub side.

13. semiconductor chip group body according to claim 1 is characterized in that: this flange layer and this weld pad in one face this first vertical direction the surface be copline.

14. semiconductor chip group body according to claim 1 is characterized in that: this pedestal and this terminal in one face this second vertical direction the surface be copline.

15. semiconductor chip group body according to claim 1 is characterized in that: this weld pad extends the outside of this adhesion layer towards this first vertical direction, this terminal extends the outside of this adhesion layer towards this second vertical direction.

16. semiconductor chip group body according to claim 1 is characterized in that: this lead comprises the lining perforation on the conductive path that is positioned between this weld pad and this terminal.

17. semiconductor chip group body according to claim 1 is characterized in that: this projection, this pedestal, this flange layer, this weld pad are identical metal with this terminal.

18. semiconductor chip group body according to claim 1 is characterized in that: this projection, this pedestal, this flange layer, this weld pad and this terminal comprise gold, silver or a nickel matter superficial layer and an internal copper core, and are mainly copper.

19. semiconductor chip group body according to claim 1 is characterized in that: this radiating seat comprises one by the shared copper core of this projection, this pedestal and this flange layer, and this lead comprises one by this weld pad and the shared copper core of this terminal.

20. a semiconductor chip group body comprises: semiconductor element, an adhesion layer, a radiating seat, and a lead; This adhesion layer has an opening, and this radiating seat comprises a projection, a pedestal and a flange layer, and this lead comprises a weld pad and a terminal; It is characterized in that: this projection is in abutting connection with this pedestal and this flange layer, and is integrally formed with this flange layer, and this projection extends along one first vertical direction from this pedestal, and certainly this flange layer along second a vertical direction extension opposite with this first vertical direction; This pedestal extends along this second vertical direction from this projection, and stretches along the side surface direction side perpendicular to these vertical direction from this projection; This flange layer is stretched from this nub side, and keeps at a distance with this pedestal; In this projection, have one face this first vertical direction depression, this depression is to be covered by this projection on this second vertical direction, this projection is also separated this depression and this pedestal, this depression have one be positioned at this flange layer place inlet; Wherein, this semiconductor element extends into this depression, and is electrically connected to this weld pad, thereby is electrically connected to this terminal, and this semiconductor element also is thermally coupled to this projection, thereby is thermally coupled to this pedestal; This adhesion layer contact this projection, this pedestal and this flange layer, and be positioned between this pedestal and this flange layer, this adhesion layer extends laterally to this terminal or crosses this terminal from this projection; This lead is positioned at outside this depression; This projection extends into this opening, and covers this semiconductor element in this second vertical direction; This depression extends into this opening.

21. semiconductor chip group body according to claim 20 is characterized in that: this semiconductor element is a light-emitting diode chip for backlight unit.

22. semiconductor chip group body according to claim 20; It is characterized in that: this semiconductor element is to be positioned at this depression; Extend the inside and outside routing of this depression through one and be electrically connected to this weld pad, and through one be positioned at this depression solid brilliant material be thermally coupled to this projection.

23. semiconductor chip group body according to claim 20 is characterized in that: this this lead of adhesion layer contact.

24. semiconductor chip group body according to claim 20 is characterized in that: this adhesion layer side direction cover and around and similar shape be coated on a sidewall of this projection.

25. semiconductor chip group body according to claim 20 is characterized in that: this adhesion layer extends to the peripheral edge of this semiconductor chip group body.

26. semiconductor chip group body according to claim 20 is characterized in that: this projection and this adhesion layer are in this pedestal place copline.

27. semiconductor chip group body according to claim 20 is characterized in that: this projection comprises the first bending corner and second a bending corner in abutting connection with this flange layer in abutting connection with this pedestal.

28. semiconductor chip group body according to claim 20 is characterized in that: this projection has the peculiar inconsistent thickness that is stamped to form.

29. semiconductor chip group body according to claim 20 is characterized in that: this depression is contained the major part of this projection along said vertical direction and said side surface direction.

30. semiconductor chip group body according to claim 20 is characterized in that: this pedestal is in having a single thickness in abutting connection with this projection place, this pedestal also have one face this second vertical direction flat surfaces.

31. semiconductor chip group body according to claim 20 is characterized in that: this pedestal covers this flange layer in this second vertical direction, extends laterally and crosses this flange layer, supports this adhesion layer, and keeps at a distance with the peripheral edge of this semiconductor chip group body.

32. semiconductor chip group body according to claim 20 is characterized in that: this flange layer and this weld pad have a same thickness, and in one face this first vertical direction the surface be copline.

33. semiconductor chip group body according to claim 20; It is characterized in that: this pedestal and this terminal have a same thickness at place adjacent one another are; But this pedestal is then different with the thickness of this terminal in abutting connection with the thickness at this projection place, this pedestal and this terminal in one face this second vertical direction the surface be copline.

34. semiconductor chip group body according to claim 20 is characterized in that: this weld pad extends the outside of this adhesion layer towards this first vertical direction, this terminal extends the outside of this adhesion layer towards this second vertical direction.

35. semiconductor chip group body according to claim 20 is characterized in that: this lead comprises the lining perforation on the conductive path that is positioned between this weld pad and this terminal.

36. semiconductor chip group body according to claim 20 is characterized in that: this projection, this pedestal, this flange layer, this weld pad are identical metal with this terminal.

37. semiconductor chip group body according to claim 20 is characterized in that: this projection, this pedestal, this flange layer, this weld pad and this terminal comprise gold, silver or a nickel matter superficial layer and an internal copper core, and are mainly copper.

38. semiconductor chip group body according to claim 20 is characterized in that: this radiating seat comprises one by the shared copper core of this projection, this pedestal and this flange layer, and this lead comprises one by this weld pad and the shared copper core of this terminal.

39. a semiconductor chip group body comprises semiconductor element, an adhesion layer, a radiating seat, a substrate, and a lead; This adhesion layer has an opening, and this radiating seat comprises a projection, a pedestal and a flange layer, and this substrate comprises a dielectric layer, and this lead comprises a weld pad and a terminal; It is characterized in that: this projection is in abutting connection with this pedestal and this flange layer, and is integrally formed with this flange layer, and this projection extends along one first vertical direction from this pedestal, and certainly this flange layer along second a vertical direction extension opposite with this first vertical direction; This pedestal extends along this second vertical direction from this projection, and covers this projection in this second vertical direction, and stretches along the side surface direction side perpendicular to these vertical direction from this projection; This flange layer is stretched from this nub side, and keeps at a distance with this pedestal; In this projection, have one face this first vertical direction depression, this depression is to be covered by this projection on this second vertical direction, this projection is also separated this depression and this pedestal, this depression have one be positioned at this flange layer place inlet; Wherein, a through hole extends through this substrate; This semiconductor element extends into this depression, and is electrically connected to this weld pad, thereby is electrically connected to this terminal, and this semiconductor element also is thermally coupled to this projection, thereby is thermally coupled to this pedestal; This this projection of adhesion layer contact, this pedestal, this flange layer and this dielectric layer; And be positioned between this projection and this dielectric layer, between this flange layer and this dielectric layer and between this pedestal and this flange layer, this adhesion layer extends laterally to the peripheral edge of this semiconductor chip group body from this projection; This lead is positioned at outside this depression; This projection extends into this opening and this through hole, and covers this semiconductor element in this second vertical direction; This depression extends into this opening and this through hole.

40. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this semiconductor element is a light-emitting diode chip for backlight unit.

41. according to the described semiconductor chip group of claim 39 body; It is characterized in that: this semiconductor element is to be positioned at this depression; Extend the inside and outside routing of this depression through one and be electrically connected to this weld pad, and through one be positioned at this depression solid brilliant material be thermally coupled to this projection.

42., it is characterized in that: this this lead of adhesion layer contact according to the described semiconductor chip group of claim 39 body.

43., it is characterized in that according to the described semiconductor chip group of claim 39 body: this adhesion layer side direction cover and around and similar shape be coated on a sidewall of this projection.

44., it is characterized in that according to the described semiconductor chip group of claim 39 body: be coated on a surface portion of this pedestal this adhesion layer similar shape, this surface portion in abutting connection with this projection and certainly this projection extend laterally, and face this first vertical direction.

45. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this projection and this adhesion layer are in this pedestal place copline.

46. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this projection comprises the first bending corner and second a bending corner in abutting connection with this flange layer in abutting connection with this pedestal.

47. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this projection has the peculiar inconsistent thickness that is stamped to form.

48. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this depression is contained the major part of this projection along said vertical direction and said side surface direction.

49. according to the described semiconductor chip group of claim 39 body; It is characterized in that: this pedestal is in having one first thickness in abutting connection with this projection place; And in having second thickness greater than this first thickness in abutting connection with this dielectric layer place, this pedestal also have one face this second vertical direction flat surfaces.

50. according to the described semiconductor chip group of claim 39 body; It is characterized in that: this pedestal covers this flange layer in this second vertical direction; Extend laterally and cross this flange layer, support this substrate and this adhesion layer, and keep at a distance with the peripheral edge of this semiconductor chip group body.

51. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this flange layer and this weld pad have a same thickness, and in one face this first vertical direction the surface be copline.

52. according to the described semiconductor chip group of claim 39 body; It is characterized in that: this pedestal and this terminal have a same thickness at place adjacent one another are; But this pedestal is then different with the thickness of this terminal in abutting connection with the thickness at this projection place, this pedestal and this terminal in one face this second vertical direction the surface be copline.

53. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this weld pad this adhesion layer of contact but keep at a distance with this dielectric layer, this weld pad extend this adhesion layer and this dielectric layer outside towards this first vertical direction; This dielectric layer of this termination contact but keep at a distance with this adhesion layer, this terminal are positioned at this adhesion layer and this dielectric layer outside towards this second vertical direction.

54. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this lead comprises the lining perforation on the conductive path that is positioned between this weld pad and this terminal.

55. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this projection, this pedestal, this flange layer, this weld pad are identical metal with this terminal.

56. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this projection, this pedestal, this flange layer, this weld pad and this terminal comprise gold, silver or a nickel matter superficial layer and an internal copper core, and are mainly copper.

57. according to the described semiconductor chip group of claim 39 body, it is characterized in that: this radiating seat comprises one by the shared copper core of this projection, this pedestal and this flange layer, and this lead comprises one by this weld pad and the shared copper core of this terminal.

58. a semiconductor chip group body comprises: semiconductor element, an adhesion layer, a radiating seat, a substrate, and a lead; This adhesion layer has an opening; This radiating seat is to be made up of a projection, a pedestal and a flange layer, and this substrate comprises a dielectric layer, and this lead is to be made up of a weld pad, a terminal and a lining perforation; It is characterized in that: this projection is in abutting connection with this pedestal and this flange layer, and is integrally formed with this flange layer, and this projection extends along one first vertical direction from this pedestal, and certainly this flange layer along second a vertical direction extension opposite with this first vertical direction; This pedestal extends along this second vertical direction from this projection, and covers this projection in this second vertical direction, and stretches along the side surface direction side perpendicular to said vertical direction from this projection; This flange layer is stretched from this nub side, and keeps at a distance with this pedestal; This projection have one face this first vertical direction depression, this depression is to be covered by this projection on this second vertical direction, this projection is also separated this depression and this pedestal, this depression have one be positioned at this flange layer place inlet; One through hole extends through this substrate; This lining perforation is the conductive path between this weld pad and this terminal; This semiconductor element extends into this depression, and is electrically connected to this weld pad, thereby is electrically connected to this terminal, and this semiconductor element also is thermally coupled to this projection, thereby is thermally coupled to this pedestal; This adhesion layer is in this dielectric layer of the inside and outside contact of this through hole; This adhesion layer be positioned between this projection and this dielectric layer, between this projection and this lining perforation, between this flange layer and this dielectric layer and between this pedestal and this flange layer, and this projection extends laterally to the peripheral edge of this semiconductor chip group body certainly; This lead is positioned at outside this depression; This weld pad contacts this adhesion layer but keeps at a distance with this dielectric layer; This weld pad is positioned at this adhesion layer and this dielectric layer outside towards this first vertical direction; This dielectric layer of this termination contact but keep at a distance with this adhesion layer, this terminal are positioned at this adhesion layer and this dielectric layer outside towards this second vertical direction, this lining perforation contact and extend through this adhesion layer and this dielectric layer; This projection contacts this adhesion layer but keeps at a distance with this dielectric layer, and this projection extends into this opening and this through hole, and covers this semiconductor element in this second vertical direction, for this semiconductor element one spill chip carrier is provided simultaneously; This adhesion layer of this pedestal contact and this dielectric layer, and in this this flange layer of second vertical direction covering, and extend laterally and cross this flange layer, this pedestal are positioned at this adhesion layer and this dielectric layer outside towards this second vertical direction; This flange layer this adhesion layer of contact but keep at a distance with this dielectric layer, this flange layer are positioned at this adhesion layer and this dielectric layer outside towards this first vertical direction; This depression extends into this opening and this through hole, and contains the major part of this projection along said vertical direction and said side surface direction.

59. according to the described semiconductor chip group of claim 58 body; It is characterized in that: this semiconductor element is a light-emitting diode chip for backlight unit; And be positioned at this depression; This semiconductor element extends the inside and outside routing of this depression through one and is electrically connected to this weld pad, and through one be positioned at this depression solid brilliant material be thermally coupled to this projection.

60. according to the described semiconductor chip group of claim 58 body; It is characterized in that: this projection and this adhesion layer are in this pedestal place copline; And this flange layer is thick than this pedestal; This flange layer and this weld pad have a same thickness, and this flange layer and this weld pad in one face this first vertical direction the surface be copline; This pedestal and this terminal have a same thickness at place adjacent one another are, but this pedestal is then different with the thickness of this terminal in abutting connection with the thickness at this projection place, this pedestal and this terminal in one face this second vertical direction the surface be copline.

61. according to the described semiconductor chip group of claim 58 body; It is characterized in that: this projection, this pedestal, this flange layer, this weld pad, this terminal and this lining perforation comprise gold, silver or nickel matter superficial layer and are mainly copper; This radiating seat comprises one by the shared copper core of this projection, this pedestal and this flange layer, and this lead comprises one by this weld pad, this terminal and the shared copper core of this lining perforation.

62. a semiconductor chip group body comprises: a light-emitting diode chip for backlight unit, an adhesion layer, a radiating seat, and a lead; This adhesion layer has an opening, and radiating seat comprises a projection, a pedestal and a flange layer, and this lead comprises a weld pad, a terminal and an encapsulating material; It is characterized in that: this projection is in abutting connection with this pedestal and this flange layer, and is integrally formed with this flange layer, and this projection extends along one first vertical direction from this pedestal, and certainly this flange layer along second a vertical direction extension opposite with this first vertical direction; This pedestal extends along this second vertical direction from this projection, and stretches along the side surface direction side perpendicular to said vertical direction from this projection; This flange layer is stretched from this nub side, and keeps at a distance with this pedestal; This projection have one face this first vertical direction depression, this depression is to be covered by this projection on this second vertical direction, this projection is also separated this depression and this pedestal, this depression have one be positioned at this flange layer place inlet; This light-emitting diode chip for backlight unit is positioned at this depression, and is electrically connected to this weld pad, thereby is electrically connected to this terminal, and this light-emitting diode chip for backlight unit also is thermally coupled to this projection, thereby is thermally coupled to this pedestal; This encapsulating material extends into this depression, and covers this light-emitting diode chip for backlight unit in this first vertical direction; This adhesion layer contact this projection, this pedestal and this flange layer, and be positioned between this pedestal and this flange layer, this adhesion layer extends laterally to this terminal or crosses this terminal from this projection; This lead is positioned at outside this depression; This projection extends into this opening, and covers this light-emitting diode chip for backlight unit in this second vertical direction; This depression extends into this opening.

63. according to the described semiconductor chip group of claim 62 body, it is characterized in that: this light-emitting diode chip for backlight unit utilizes one to extend the inside and outside routing of this depression and be electrically connected to this weld pad, and utilize one be positioned at this depression solid brilliant material be thermally coupled to this projection.

64., it is characterized in that according to the described semiconductor chip group of claim 62 body: this lead of this adhesion layer contact, side direction cover and around and similar shape be coated on a sidewall of this projection, and extend to the peripheral edge of this semiconductor chip group body.

65. according to the described semiconductor chip group of claim 62 body, it is characterized in that: this encapsulating material is the encapsulating material that a converting colors is used.

66. according to the described semiconductor chip group of claim 65 body; It is characterized in that: this semiconductor chip group body also comprises the transparent encapsulation material of the encapsulating material used of this converting colors of contact, and this transparent encapsulation material covers the encapsulating material that this converting colors is used in this first vertical direction.

67. according to the described semiconductor chip group of claim 66 body, it is characterized in that: the encapsulating material that this converting colors is used comprises silica resin and phosphor, this transparent encapsulation material comprises silica resin but does not contain phosphor.

68. according to the described semiconductor chip group of claim 62 body, it is characterized in that: this projection comprises the first bending corner and second a bending corner in abutting connection with this flange layer in abutting connection with this pedestal; This depression is contained the major part of this projection along said vertical direction and said side surface direction; This pedestal covers this flange layer in this second vertical direction, extends laterally and crosses this flange layer, supports this adhesion layer, and keeps at a distance with the peripheral edge of this semiconductor chip group body.

69. according to the described semiconductor chip group of claim 62 body, it is characterized in that: this projection and this adhesion layer are in this pedestal place copline; This flange layer and this weld pad have a same thickness, and in one face this first vertical direction the surface be copline; This pedestal and this terminal have a same thickness at place adjacent one another are, but this pedestal is then different with the thickness of this terminal in abutting connection with the thickness at this projection place, this pedestal and this terminal in one face this second vertical direction the surface be copline.

70. according to the described semiconductor chip group of claim 62 body; It is characterized in that: this weld pad extends the outside of this adhesion layer towards this first vertical direction; This terminal extends the outside of this adhesion layer towards this second vertical direction; One lining perforation extends through this adhesion layer, and is positioned on the conductive path between this weld pad and this terminal.

71. according to the described semiconductor chip group of claim 62 body; It is characterized in that: this projection, this pedestal, this flange layer, this weld pad are identical metal with this terminal; All comprise gold, silver or nickel matter superficial layer; And be mainly copper, this radiating seat comprises one by the shared internal copper core of this projection, this pedestal and this flange layer, and this lead comprises one by this weld pad and the shared internal copper core of this terminal.

72. a semiconductor chip group body comprises: a light-emitting diode chip for backlight unit, an adhesion layer, a radiating seat, and a lead; This adhesion layer has an opening, and this radiating seat comprises a projection, a pedestal and a flange layer, and this lead comprises a weld pad and a terminal and an encapsulating material; It is characterized in that: this projection is in abutting connection with this pedestal and this flange layer, and is integrally formed with this flange layer, and this projection extends along one first vertical direction from this pedestal, and certainly this flange layer along second a vertical direction extension opposite with this first vertical direction; This pedestal extends along this second vertical direction from this projection, and covers this projection in this second vertical direction, and stretches along the side surface direction side perpendicular to said vertical direction from this projection; This flange layer is stretched from this nub side, and keeps at a distance with this pedestal; This projection have one face this first vertical direction depression, this depression is to be covered by this projection on this second vertical direction, this projection is also separated this depression and this pedestal, this depression have one be positioned at this flange layer place inlet; This light-emitting diode chip for backlight unit is to be positioned at this depression, and is electrically connected to this weld pad through a routing, thereby is electrically connected to this terminal, and this light-emitting diode chip for backlight unit also utilizes a solid brilliant material to be thermally coupled to this projection, thereby is thermally coupled to this pedestal; This encapsulating material contacts this light-emitting diode chip for backlight unit, this routing, this solid brilliant material and this projection in this depression; And this encapsulating material and this lead, this pedestal and this adhesion layer are kept at a distance, and this encapsulating material also covers this light-emitting diode chip for backlight unit in this first vertical direction; This adhesion layer contact this projection, this pedestal and this flange layer, and be positioned between this pedestal and this flange layer, this adhesion layer extends laterally to this terminal or crosses this terminal from this projection; Should solid brilliant material be to be positioned at this depression, this routing extends the inside and outside of this depression, and this lead then is positioned at outside this depression; This projection extends into this opening, and covers this light-emitting diode chip for backlight unit in this second vertical direction, for this light-emitting diode chip for backlight unit one a spill chip carrier and a reflector is provided simultaneously; This depression extends into this opening.

73. according to the described semiconductor chip group of claim 72 body, it is characterized in that: this adhesion layer contacts this weld pad but keeps at a distance with this terminal, and this adhesion layer extends laterally and cross this terminal from this projection.

74., it is characterized in that according to the described semiconductor chip group of claim 72 body: this lead of this adhesion layer contact, side direction cover and around and similar shape be coated on a sidewall of this projection, and extend to the peripheral edge of this semiconductor chip group body.

75. according to the described semiconductor chip group of claim 72 body, it is characterized in that: this encapsulating material is the encapsulating material that a converting colors is used.

76. according to the described semiconductor chip group of claim 75 body; It is characterized in that: this semiconductor chip group body also comprises the transparent encapsulation material of this converting colors of contact is used outside this depression encapsulating material, this flange layer, this weld pad and this routing; And this transparent encapsulation material and this light-emitting diode chip for backlight unit, this solid brilliant material, this pedestal and this terminal are kept at a distance, this transparent encapsulation material and encapsulating material, this flange layer and this routing used in this this converting colors of first vertical direction covering.

77. according to the described semiconductor chip group of claim 76 body, it is characterized in that: the encapsulating material that this converting colors is used comprises silica resin and phosphor, this transparent encapsulation material comprises silica resin but does not contain phosphor.

78. according to the described semiconductor chip group of claim 72 body, it is characterized in that: this projection comprises the first bending corner and second a bending corner in abutting connection with this flange layer in abutting connection with this pedestal; This depression is contained the major part of this projection along said vertical direction and said side surface direction; This pedestal covers this flange layer in this second vertical direction, extends laterally and crosses this flange layer, supports this adhesion layer, and keeps at a distance with the peripheral edge of this semiconductor chip group body.

79. according to the described semiconductor chip group of claim 72 body, it is characterized in that: this projection and this adhesion layer are in this pedestal place copline; This flange layer and this weld pad have a same thickness, and in one face this first vertical direction the surface be copline; This pedestal and this terminal have a same thickness at place adjacent one another are, but this pedestal is then different with the thickness of this terminal in abutting connection with the thickness at this projection place, this pedestal and this terminal in one face this second vertical direction the surface be copline.

80. according to the described semiconductor chip group of claim 72 body; It is characterized in that: this weld pad extends the outside of this adhesion layer towards this first vertical direction; This terminal extends the outside of this adhesion layer towards this second vertical direction; One lining perforation extends through this adhesion layer, and is positioned on the conductive path between this weld pad and this terminal.

81. according to the described semiconductor chip group of claim 72 body; It is characterized in that: this projection, this pedestal, this flange layer, this weld pad are identical metal with this terminal; All comprise gold, silver or nickel matter superficial layer; And be mainly copper, this radiating seat comprises one by the shared internal copper core of this projection, this pedestal and this flange layer, and this lead comprises one by this weld pad and the shared internal copper core of this terminal.

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