Summary of the invention
The object of the present invention is to provide a kind of serial port TXD spool reason to check instruction type 2
4N/ 2 groups of home electronic appliance junction blocks, it is main frame with the computer, four input interconnections by serial port detect the variation of the state of the situation of 3 digital quantity output type transducers and 1 transducer, sending data wire by serial port cooperates binary counter to produce 4N (N=1,2,3 ...) the bit binary data instruction, make comparisons management 2 by comparator and the command code that presets
4N/ 2 groups of domestic electronics or electrical equipment; Comprise: RS232C interface, USB interface, USB change serial port circuit, the 4 pairs of sensor interface terminals, RS232 → TTL/CMOS level shifting circuit, 4N (N=1,2,3 ...) position binary counter circuit, instruction match circuit, data-latching circuit, 2
4N/ 2 groups of electronic switching circuits, voltage-stabilized power supply circuit, anti-lightning strike and surge circuit and power line and plug thereof.
The technical solution adopted for the present invention to solve the technical problems is:
USB interface is connected to the corresponding signal input part that USB changes the serial port circuit, the corresponding port line parallel of the latter's signal output part and RS232C interface; The first pin CD of RS232C interface, the 6th pin DSR, the 8th pin CTS are connected a pull-up resistor respectively to positive source with nine kinds of needles RI, and this four pin and power cathode have constituted 4 pairs of sensor interface terminals respectively; The 3rd pin TXD of RS232C interface, the 4th pin DTR, the 7th pin RTS are connected respectively to three signal input parts of RS232 → TTL/CMOS level shifting circuit, three signal output parts of corresponding level shifting circuit are connected respectively to 4N (N=1,2,3 ...) the output enable end of the position clock signal input terminal of binary counter circuit and reset terminal thereof, instruction match circuit; 4N (N=1,2,3 ...) and the position binary counter circuit 4N (N=1,2,3 ...) and individual signal output part be connected respectively to the instruction match circuit 4N (N=1,2,3.......) individual comparison signal input, the instruction match circuit 2
4NIndividual signal output part A=B is connected respectively to 2 of data-latching circuit
4N/ 2 opposed 1 end S and reset terminal R; 2 of data-latching circuit
4N/ 2 output Q are connected to the control signal input of 1 group of electronic switching circuit separately; The ac input end of voltage-stabilized power supply circuit is received civil power with anti-lightning strike in parallel with the surge circuit by power line and plug thereof, and power cathode links to each other with the 5th pin GND of RS232C interface.
Described voltage-stabilized power supply circuit is made up of power transformer, diode bridge rectifier circuit, capacitor filter and circuit of three-terminal voltage-stabilizing integrated 7812, and two outputs of 7812 have constituted positive source and the power cathode of this device respectively.
Described anti-lightning strike the polyphone by a fuse and a piezo-resistance with the surge circuit formed.
Described RS232 → TTL/CMOS level shifting circuit is divided into three the tunnel, and the structure on each road is identical, comprising: triode, base resistance, collector resistance, schmitt inverter and working station indicator circuit; Wherein, one end of base resistance is as the signal input part of this road level shifting circuit, the other end is connected to the base stage of triode, the collector electrode of positive source and collector resistance, triode, emitter and power cathode are formed series circuit, the collector electrode of triode is also connected to the input of a schmitt inverter, and the output of this schmitt inverter is as the signal output part of this road level shifting circuit; The working station indicator circuit comprises a current-limiting resistance and a light-emitting diode, and positive source is connected with light-emitting diode and current-limiting resistance thereof and received the output of schmitt inverter.
Described 2
4NThe structure of/2 groups of electronic switching circuits is identical, comprises separately: No. 1 alternating current electronic switching circuit and No. 1 direct current relay electronic switching circuit.
Described alternating current electronic switching circuit comprises: 1 NPN triode, 1 PNP triode, 1 base resistance, 1 base biasing resistor, 1 collector resistance, 1 current limliting collector resistance, a light-emitting diode and a solid-state relay; Wherein, the base stage of one termination NPN triode of base resistance, the other end is as the control signal input of this electronic switching circuit, base biasing resistor is connected in parallel on the emitter junction of PNP triode, the emitter of this PNP triode connects positive source, its base stage and collector resistance, light emitting diode string is connected to the collector electrode of NPN triode, the emitter of NPN triode is connected to power cathode, current limliting of the collector electrode of PNP triode series connection is connected to the positive pole in the control signal input of solid-state relay with collector resistance, the negative pole in the control signal input of solid-state relay is connected to power cathode; Two outputs of solid-state relay constitute the output of this alternating current electronic switching circuit.
Described direct current relay electronic switching circuit comprises: triode and base resistance, a diode and a direct current relay; Wherein, the base stage of one termination triode of base resistance, the other end is as the control signal input of this electronic switching circuit, the emitter of triode is connected to power cathode, its collector electrode is connected respectively to an end of the coil of the positive pole of diode and direct current relay, and the other end of the negative pole of diode and the coil of direct current relay all is connected to positive source; Six terminals of two pairs of single-pole double-throw switch (SPDT)s of direct current relay have constituted the output of this direct current relay electronic switching circuit.
Described 4N (N=1,2,3, ...) position binary counter circuit become by N piece tetrad counter stage joint group, every tetrad counter has four count signal outputs, constitutes 4N (N=1,2 altogether, 3, ...) position count signal output, their clock signal input terminal parallel connection is as the clock signal input terminal of this counting circuit, their reset terminal parallel connection is as the reset terminal of this counting circuit.
Described instruction match circuit is by 2
4NIndividual 4N (N=1,2,3 ...) bit digital comparator composition, each digital comparator has a signal output part A=B, constitutes 2 of instruction match circuit altogether
4NIndividual signal output part A=B, each digital comparator has 4N (N=1,2,3 ...) individual comparison signal input, 4N (the N=1 that constitutes the instruction match circuit in parallel, 2,3 ...) individual comparison signal input, they respectively have an output enable end, the output enable end that constitutes the instruction match circuit in parallel.
Described 4N (N=1,2,3, ...) the bit digital comparator adopts the two-stage comparative approach to constitute with the parallel way expansion by 4 bit comparators: the first order is made up of
N piece 4 bit comparators, their one group of input A3A2A1A0 constitutes this 4N (N=1 altogether, 2,3, ...) 4N (N=1,2,3 of bit digital comparator, ...) individual comparison signal input, their another group input B3B2B1B0 arranges level according to default command code by switch respectively, and their cascade signal input A>B and A<B are connected to power cathode, and cascade signal input A=B is connected to positive source; The second level by
Piece 4 bit comparators are formed, in the formula,
Be the round numbers function,
Each
piece 4 bit comparator of the expression first order have two comparison output signal A>B, A<B need use one of two group of 4 bit comparison signal input part of partial 4 bit comparators right, 1 expression must use one of two group of 4 bit comparison signal input part of 4 bit comparators to doing the output control of matching result: partial 4 bit comparators are arranged in the P rank according to the height precedence order of binary data, wherein, cascade signal input A>B and the A<B of 4 bit comparators of lowest-order are connected to power cathode, its cascade signal input A=B is connected to positive source, signal output part A>the B of 4 bit comparators of low order, A<B and A=B are connected respectively to the cascade signal input A>B of
single order 4 bit comparators, A<B and A=B, one total 4P is to comparing signal input part A3A2A1A0 and B3B2B1B0, wherein, the signal input part A3 of 4 bit comparators of high-order receives positive source, its signal input part B3 and signal output part A=B constitute this 4N (N=1 respectively, 2,3 ...) output enable end and the signal output part A=B of bit digital comparator; The signal input part A3A2A1A0 of all the other 4P-1 of partial 4 bit comparators and B3B2B1B0 are connected to a pair of signal output part A>B and the A<B of each
piece 4 bit comparator of the first order respectively in pairs, and not busy surplus each all is connected to power cathode to signal input part.
Described data-latching circuit is by 2
4N/ 2 d type flip flops or rest-set flip-flop are formed.
The present invention has constituted the interface between computer and the home electronic appliance, under the management of program, send out serial signal from the serial data transmitting terminal TXD of serial port, generate director data through the multidigit binary counter circuit, reset terminal by output interconnection DTR control binary counter has guaranteed the correct of director data, and has used output interconnection RTS to confirm whether to export this instruction, guaranteed the safety of director data, management 2
4N/ 2 pairs of light current and forceful electric power electronic switching circuit; Though use 4 bit comparators more, but, its advantage is: two 4N (N=1,2,3, ...) bit digital comparator, a rest-set flip-flop and one group of electronic switching circuit make the unit, give each electronics or electrical equipment, namely give every electronics or electrical equipment two command codes, comprise starting sign indicating number and stop code, do not need singlechip technology also can networking manage a large amount of electronic apparatuss, cooperate digital quantity output type working sensor again, can make home electronic appliance realize the automation on the complete meaning, the technology facility can be for the reference of exploitation household electrical appliance.
Description of drawings
Below in conjunction with accompanying drawing, further specify the present invention.
Fig. 1 is the sensor interface circuitry figure of serial port.
Fig. 2 is the schematic diagram of RS232 → TTL/CMOS level shifting circuit.
Fig. 3 represent 4N (N=1,2,3 ...) and 1 4N in the match circuit of position binary counter circuit, instruction (N=1,2,3 ...) and 1 rest-set flip-flop and 1 group of electronic switching circuit in the bit digital comparator, data-latching circuit, wherein, N=2.
Fig. 4 is the schematic diagram of one group of electronic switching circuit.
Among the figure, 001. one group of electronic switching circuit, 5. voltage-stabilized power supply circuit, 51. anti-lightning strike and surge circuit, the 6.USB interface, 7.USB changes the serial port circuit, 8.RS232C interface, 21.4N (N=1,2,3, ...) position binary counter circuit (N=2), 211. low tetrad counters, 212. high tetrad counters, 22. 4N (N=1,2,3 ...) bit digital comparator (N=2), 221. low four bit comparators of the first order, 222. high four bit comparators of the first order, 223. partial (high-orders), four bit comparators, 23.RS trigger, 31. the single-pole double throw direct current electromagnetic relay, 32. solid-state relay SSR.
Embodiment
The transmission range of the RS232C interface of computer can reach 15 meters, corresponding level+the 3V of logical zero~+ 15V, corresponding level-the 3V of logical one~(15) V, detect the response signal of external equipment by the following event attribute of serial communication control MSComm32.OCX: 1) state of ComEvCTS:Clear_to_Send line changes; 2) state of ComEvDSR:Data_Set_Ready line changes to 0 from 1; 3) state of ComEvCD:Carrier_Detect line changes; 4) ComEvRing: detect bell signal, but, the attribute MSComm32.CTSholding/.DSRholding/.DCDholding that does not possess the serial communication control can't inquire about the height situation that detects its level, and some UART (asynchronous reception-transmitter) may not support this event.
Therefore, as shown in Figure 1, adopt pull-up resistor R1, R2, R3, R4 and transducer Rs1, Rs2, Rs3, the mode of Rs4 ground connection has constituted the serial interface circuit of transducer, the transducer of adaptation comprises: output signal be the switching value type ,+3V~+ the level type of 15V or the transducer of pulse signal type or resistance saltus step type.The working power of family expenses transducer is generally<DC power supply of 15V, be operated in indoorly, and need not consider at transducer Rs1, Rs2, Rs3 arranges the photoelectricity coupling circuit to make electrical isolation between Rs4 and the RS232C interface, reduced cost.But, be parallel with anti-lightning strike and surge circuit (51) at the input of civil power.
HCMOS, the operating voltage of cmos circuit is respectively: 2V-6V and 3V-15V (4500B)-18V (4000B).Therefore, as shown in Figure 2, adopt triode to design RS232 → TTL/CMOS level shifting circuit.Wherein, schmitt inverter is used for signal shaping.
Among Fig. 3,4N (N=2) position binary counter circuit (21) but adopt N=2 four presentable binary counter CD4516 of piece (211), (212) cascade to form, can use the binary counter of other type instead.
Serial port transmission line TXD is in high level when flat.The Settings attribute of serial communication control MSComm32.OCX determines the information format of asynchronous serial communication: " character+parity check bit of (1 low level) start bit+transmission+(1,1.5 or 2 high level) position of rest ".For example, MSComm1.Settings=" 9600, n, 8,1 " is its default parameter value, and the meaning is " employed communication port is not done parity check with the speed transmission of per second 9600Bit, and each data cell is 8 Bit, and position of rest is 1 Bit ".When program need transfer out a character string, use the Output attribute of control MSComm32.OCX that character string is write in the output register, for example: MSComm1.Output=" ABCDE ", this is about to five characters of ABCDE and sends out in regular turn by the RS232C interface, and its front of character of every transmission is superimposed with a low level beginning flag position.For example transmit letter " B ", its ASCII character is " 42H=01000010B ", and the waveform that serial port line TXD sends is:

Can produce 3 rising edge positive transition pulses; And transmit letter " A "=" 41H=01000001B ", the waveform that serial port line TXD sends is:
Only produce 2 rising edge positive transition pulses.Therefore, earlier by DTR output high level, 4N (N=1 resets, 2,3, ...) position binary counter circuit (21): q7q6...q1q0=Q3Q2Q1Q0Q3Q2Q1Q0=00000000, then, DTR=0 is set, make the reseting controling end of counting circuit (21) be in the invalid attitude of low level, send out several letters " B " continuously by TXD again, but can cause four presentable binary counter CD4516 of N=2 piece (21), (22) output produces following result: q7q6...q1q0=Q3Q2Q1Q0Q3Q2Q1Q0=00000011 (3) successively, 00000110 (6), 00001001 (9), 00001100 (12), 00001111 (15), 00010010 (18), 00010101 (21), 00011000 (24), 00011011 (27), 00011110 (30), 00100011 (33);As seen, 4N (N=1,2,3 ...) the counting output result of position binary counter circuit can comprise that the various of 8=4 * N bit may situations, one has 2
8=2
4N(N=2) plant.This all possible situation is through 2 in the instruction match circuit
4NIndividual 4N (N=1,2,3 ...) the bit digital comparator, all can make 2 at every turn
4NOne of individual signal output part is in the level available state.1 4N of instruction in the match circuit (N=1,2,3 ...) and the circuit of bit digital comparator (22) as shown in Figure 3, the level of one group of comparison signal input B3B2B1B0B3B2B1B0 of the comparator of its first order (221), (222) need set in advance.
Data-latching circuit is by 2
4N/ 2 d type flip flops or rest-set flip-flop are formed, each has a reset terminal R or puts 1 end S, need separately to use one independently line of instruction data manage, have the function of latch mode, make the electronic switching circuit that its back connects [(001) ... ] according to instruction works.But, the TXD line send serial signal with the process that produces the instruction of correct binary data in, 4N (N=1,2,3, ...) position binary counter circuit (21) and the instruction match circuit (22) that connects thereafter can produce some transitional status datas, their can to data latch cicuit (23) and electronic switching circuit [(001) ... ] exert an influence.For this reason, generally use ternary class device to guarantee in good time output order data.Among Fig. 3, this device is brought in control output with a pair of highest order comparison signal input of comparator: for partial (high-order) comparator (223), and A3=VCC=" 1 ", B3=RTS, the condition that the high level effective status appears in its output signal A=B is 1) RTS=1,2) 4N (N=1 of binary counter circuit (21), 2,3 ...) some 4N (N=1,2 in the output signal and instruction match circuit of position, 3 ...) command code that presets of bit digital comparator (22) is consistent.