CN102447015B - A kind of light emitting diode with vertical structure - Google Patents

Abstract

The present invention proposes a kind of structure and method of light emitting diode with vertical structure, it is characterized in that: one, chip is using multiple layer metal as the support substrates of epitaxial loayer, and its effect is heat conduction and conduction; Two, the multiple layer metal as support substrates is obtained by evaporation, sputtering or electric plating method growth; Three, the metal level as support substrates is made up of multiple layer metal.

Description

A Vertical Structure Light Emitting Diode

technical field

The present invention relates to a device structure and manufacturing method of a vertical light-emitting diode chip (LED), in particular to a manufacturing method of a substrate-replaced light-emitting diode chip, in which a metal substrate with high thermal conductivity is used instead of a sapphire lining with poor thermal conductivity end. This device structure is conducive to enhancing the heat dissipation capability of the light-emitting diode chip, and at the same time can improve the reliability of the chip. On the other hand, it can also make a rough light-emitting surface on the N-face GaN, which helps to increase the light-emitting efficiency of the chip.

Background technique

Vertical light-emitting diodes using substrate replacement technology are usually fabricated by depositing contact layer metal, reflective layer metal, and barrier layer metal on the surface of the gallium nitride epitaxial layer in sequence, then depositing metal solder, and then depositing contact metal and metal solder Thermally conductive substrate bonding (Waferbonding), the metal solder commonly used for bonding is gold-tin alloy. After that, laser lift-off technology is used to separate the epitaxial layer from the sapphire substrate, and the epitaxial layer is transferred to the heat-conducting substrate, so that the heat dissipation performance of the light-emitting diode chip will be better. Figure-1 is a schematic diagram of a vertical structure LED chip using substrate bonding. In the figure, 1 is a metal electrode, 2 is a GaN epitaxial layer, 3 is a contact and reflective layer, 4 is a metal solder, 5 is a thermally conductive substrate, and 6 is a back gold layer.

Using substrate bonding technology and laser lift-off technology to separate sapphire and epitaxial layers to achieve substrate replacement, there are two main problems: one is that the temperature in the substrate bonding process needs to reach the eutectic point of the metal solder. For gold-tin solder, The eutectic temperature is 283°C, which requires that the thermally conductive substrate not only has good thermal conductivity, but also has a thermal expansion coefficient similar to that of the GaN epitaxial layer and the sapphire substrate, so as to reduce the influence of thermal stress. Available materials include heat-conducting ceramics, copper-tungsten alloys, molybdenum-copper alloys, etc., and the use of these materials will directly lead to an increase in chip processing costs. The second is that the substrate bonding process window is narrow and requires high control of process conditions. After bonding, epitaxial layer cracks or wafer warping may sometimes occur, which affects the yield after laser lift-off.

In order to overcome the problems existing in the production of vertical structure LED chips by substrate bonding technology and laser lift-off technology, the present invention proposes a method of using metal thin film deposition to prepare metal heat-conducting substrates and realize substrate transfer to produce vertical structure LED chips.

Contents of the invention

The purpose of the present invention is to propose a vertical structure LED manufacturing method, which avoids the substrate bonding process, reduces the process cost of separating the sapphire and the epitaxial layer, and improves the yield without affecting the performance of the device.

In order to achieve the above objectives, the technical solution of the present invention is to provide a vertical structure LED manufacturing method. After depositing contact layer metal, reflective layer metal, and barrier layer metal on the surface of the gallium nitride epitaxial layer in sequence, evaporation, or sputtering, or electroplating Deposit one or more layers of metal as the heat sink substrate to make it thick and strong enough to support the gallium nitride epitaxial layer, and then remove the sapphire substrate by mechanical grinding or laser lift-off technology, so that the heat sink substrate becomes a gallium nitride epitaxial layer Layer a new supporting substrate. The following takes the evaporation scheme as an example. The method is as follows: first, deposit a metal contact and a reflective layer on the GaN epitaxial layer, then evaporate a 1-5um metal barrier layer, and then evaporate and deposit a layer of metal with good thermal conductivity, such as copper , silver and other metals, then deposit a layer of metals with higher Moss hardness, such as chromium, tungsten and other metals, so that the final thickness is between 150 and 500um at the end, and then evaporate the back gold layer. Secondly, the sapphire substrate is removed by mechanical grinding or laser lift-off technology, so that the electroplated metal layer becomes a new substrate for the epitaxial layer. Then, on the epitaxial layer with the sapphire substrate removed, through photolithography, wet etching, and dry etching, the epitaxial layer is scribed to the metal layer, so that the gallium nitride epitaxial layer becomes a discrete die unit. On this basis Make N electrode and passivation layer. The features are as follows: 1. The metal heat-conducting substrate is grown by electroplating, which avoids thermal stress factors in the wafer bonding process. 2. The chip unit manufacturing process is carried out after the substrate transfer is completed. Such a device structure is beneficial to significantly reduce the process cost.

Detailed ways

The present invention will be further described below in conjunction with drawings and embodiments.

1. Make metal reflective, contact layer and metal barrier layer on GaN epitaxial layer. Use evaporation or sputtering to deposit silver thin film as a reflective contact layer, and then evaporate or sputter to deposit refractory metal or alloy as a barrier layer, such as tungsten, tungsten alloy, molybdenum, molybdenum alloy, etc. Figure-2 is a schematic cross-sectional view of the epitaxial wafer after depositing the contact reflective layer and barrier layer. In the figure, 7 is a barrier metal; 8 is a contact and reflective layer; 9 is a gallium nitride epitaxial layer; 10 is a sapphire substrate.

2. Evaporation (?) Deposit a layer of metal with high thermal conductivity, such as copper or silver, or their alloys, with a thickness in the range of 50-300um. Figure-3 is a schematic cross-sectional view of the epitaxial wafer after depositing a high thermal conductivity metal layer. 11 among the figure is copper or silver.

3. Deposit a layer of high Moss hardness metal, such as chromium or WTi alloy, on the electroplating layer by evaporation or sputtering, with a typical thickness of 2-5um to improve the mechanical strength of the metal substrate and eliminate film stress. The effect of adjusting the thermal expansion coefficient of the entire metal substrate. Then repeat the process in 2, and then deposit a layer of high Moss hardness metal, so alternately, the total thickness of the metal substrate is between 150 and 500um, and finally deposit a layer of gold as a protective layer, and also as a P of the chip Type electrode, its typical thickness is 0.2 ~ 1um. Figure-4 is a schematic cross-sectional view of the epitaxial wafer after the metal substrate is prepared. 12 among the figure is a chromium layer, and 13 is a back gold layer.

4. Remove the sapphire substrate. The sapphire substrate is removed by laser lift-off technology or mechanical grinding. After removing the sapphire substrate, the gallium nitride epitaxial layer uses the multilayer metal deposited in steps 1, 2, and 3 as a new supporting substrate. Figure-5 is a schematic cross-sectional view of the epitaxial wafer after removing the sapphire substrate. In the figure, 7 is a barrier layer metal, 8 is a contact and reflective layer, 9 is a GaN epitaxial layer, 11 is copper or silver, 12 is a chromium layer, and 13 is a back gold layer.

5. Through photolithography, wet etching, dry etching and other processes, remove the gallium nitride epitaxial layer on the scribe groove, so that the gallium nitride epitaxial layer becomes a discrete die unit. Figure-6 is a schematic cross-sectional view after etching the scribe groove.

6. Use dry etching or wet etching, or a combination of dry etching and wet etching, to thin the epitaxial layer until the heavily doped n-type gallium nitride layer is exposed, and obtain Rough-surfaced n-type gallium nitride. Figure-7 is the roughened epitaxial layer

7. Make n-electrode on the surface of n-type gallium nitride by photolithography, evaporation, and lift-off technology, and use heat-conducting metal as p-type electrode. Figure-8 is the n-electrode prepared on the epitaxial layer. 14 in the figure is an n-electrode.

8. Deposit a passivation layer on the surface of the wafer in 7. The passivation layer usually uses one or more of materials such as silicon dioxide, silicon nitride or silicon oxynitride. The deposition method can be sputtering, evaporation or chemical vapor deposition, etc. Then, a window is opened on the passivation layer through co-processes such as photolithography, etching, and cleaning, so that the edge of the chip is covered by the passivation layer, exposing the electrodes and the light-emitting surface. Figure-9 is the epitaxial layer after preparing the passivation layer. 15 in the figure is a passivation layer.

9. Scribe and separate the die, as shown in Figure-10.

While the embodiments of the present invention have been described by the above examples, they are illustrative only. In fact, without violating the principle of the present invention, it can also be modified in various forms, such as order adjustment between some processes. Furthermore, the scope of the present invention is defined by the appended claims.

Claims (1)

1. A method for manufacturing a vertical structure light-emitting diode, characterized in that it comprises the steps of: 1. Fabricate metal light reflection, contact layer and metal barrier layer on the gallium nitride epitaxial layer on the sapphire substrate; use tungsten, tungsten alloy, molybdenum or molybdenum alloy as the metal barrier layer; 2. Depositing a metal layer of metal copper or silver on the metal barrier layer, the thickness of the metal layer is 300 μm; and depositing a high Moss hardness metal layer on the metal layer, the high Moss hardness metal layer The material is chromium or WTi alloy, and the thickness of the high Moss hardness metal layer is 2-5 μm; 3. Depositing a second metal layer of copper or silver on the high Moss hardness metal layer deposited in step 2 and depositing the high Moss hardness metal layer on the second metal layer, wherein the The total thickness of the metal layer, the two high Moss hardness metal layers and the second metal layer is 500 μm; 4. Depositing a gold layer as a protective layer on the high Moss hardness metal layer deposited in the step 3, the thickness of the gold layer is 0.2-1 μm; 5. Remove the sapphire substrate; remove the gallium nitride epitaxial layer, the metal reflective layer, the contact layer, the metal barrier layer, the metal layer, the high Moss hardness metal layer, the second The metal layer, the high Moss hardness metal layer and the gold layer are integrally reversed; 6. Etching the gallium nitride epitaxial layer to the metal reflective and contact layer, and forming an array of multiple gallium nitride epitaxial layers on the metal reflective and contact layer; 7. Perform dry etching and/or wet etching on the upper surfaces of all the gallium nitride epitaxial layers to reduce the thickness of each of the gallium nitride epitaxial layers until each of the gallium nitride epitaxial layers is exposed. A heavily doped N-type GaN layer in the layer to obtain an array of a plurality of N-type GaN epitaxial layers with rough upper surfaces; 8. Fabricating electrodes on the upper surfaces of each of the N-type gallium nitride epitaxial layers as N-type electrodes of each of the vertical structure light-emitting diodes; etching the gold layer to fabricate P-type electrodes of each of the vertical structure light-emitting diodes electrode; 9. Deposit passivation layer; 10. Scribing to form each vertical light emitting diode.