CN102437047A - Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method - Google Patents
Shallow trench isolation (STI) structure chemical mechanical polishing (CMP) method and STI structure manufacture method Download PDFInfo
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- CN102437047A CN102437047A CN2011102502668A CN201110250266A CN102437047A CN 102437047 A CN102437047 A CN 102437047A CN 2011102502668 A CN2011102502668 A CN 2011102502668A CN 201110250266 A CN201110250266 A CN 201110250266A CN 102437047 A CN102437047 A CN 102437047A
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000002955 isolation Methods 0.000 title claims abstract description 12
- 238000005498 polishing Methods 0.000 title claims abstract description 11
- 239000000126 substance Substances 0.000 title abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 234
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 116
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 116
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 111
- 238000000227 grinding Methods 0.000 claims abstract description 58
- 239000007788 liquid Substances 0.000 claims abstract description 39
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 37
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 12
- 238000001039 wet etching Methods 0.000 claims abstract description 9
- 239000011241 protective layer Substances 0.000 claims description 64
- 239000010410 layer Substances 0.000 claims description 62
- 230000004888 barrier function Effects 0.000 claims description 35
- 239000000758 substrate Substances 0.000 claims description 33
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 6
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 5
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 5
- 239000003082 abrasive agent Substances 0.000 claims description 3
- 238000002156 mixing Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 abstract description 5
- 230000000903 blocking effect Effects 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 description 15
- 238000005516 engineering process Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 7
- 239000003795 chemical substances by application Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000004377 microelectronic Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 239000012530 fluid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- -1 silicon nitrides Chemical class 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
The invention discloses a shallow trench isolation (STI)-chemical mechanical polishing (CMP) method for a silicon oxide/silicon nitride double inner wall protection layer and a method for manufacturing an STI structure by the STI-CMP method. Grinding liquid with higher grinding speed ratio of the silicon oxide to the silicon nitride is used for removing a trench silicon dioxide filling layer, the operation is stopped on a silicon nitride protection layer, then, grinding liquid with a higher grinding speed ratio of the silicon nitride to the silicon oxide is used for grinding the silicon nitride protection layer, after the silicon nitride protection layer is completely removed, the original grinding liquid with the higher grinding speed ratio of the silicon oxide to the silicon nitride is used for grinding a silicon dioxide protection layer, and finally, the operation is stopped on a silicon nitride blocking layer. Therefore, the wet etching step for additionally removing the silicon nitride protection layer and the silicon dioxide protection layer in the traditional STI manufacture method is avoided, the process complexity is reduced, and the flatness of the wafer surface is favorably improved.
Description
Technical field
The present invention relates to a kind of production process of electronic elements, relate in particular to and a kind ofly be used for the cmp method of the two inner wall protection layer fleet plough groove isolation structure of silica/silicon nitride and adopt said method to make the method for said fleet plough groove isolation structure.
Background technology
In semiconductor fabrication process, shallow trench isolation is widely used as a kind of device separation from (Shallow Trench Isolation, or STI) technology.As shown in Figure 1; Common STI technological process is: earlier deposit one deck silica (pad oxide) and silicon nitride (pad nitride) successively on silicon substrate (substrate) 1; Wherein silicon oxide layer is as the protective layer of silicon substrate, and (Fig. 1 a) as the barrier layer of subsequent etching and CMP process for silicon nitride.Successively through photoetching and etching, on silicon substrate, form needed shallow trench (Fig. 1 b) afterwards.The degree of depth of general groove is between 300 ~ 700nm.Then at the inwall of groove with thermal oxidation method growth layer of silicon dioxide protective layer (liner oxide), repairing the damage that etching causes substrate, and to the wedge angle sphering (corner rounding) (Fig. 1 c) of channel bottom.Again with chemical gas-phase method deposit (chemical vapor deposition or CVD) silicon dioxide as the filling trench isolation.Because the characteristic of chemical gas-phase method; Also can be in groove deposit silicon dioxide at the silicon dioxide layer (Fig. 1 d) of the suitable thickness of surface deposition of silicon nitride barrier; Need use chemico-mechanical polishing (Chemical-mechanical polishing or CMP) technology to grind the silicon dioxide of removing in the silicon nitride surface deposit at last; And stop on the silicon nitride barrier, finally form a smooth surface (Fig. 1 e) at wafer.Last again through the silicon dioxide removal of wet etching with silicon nitride and silicon nitride lower floor, expose surface of silicon.So far, isolating shallow trench is completed into.
Though traditional STI technology can improve the performance and the integrated level of device, also produces many problems in the manufacture process.One of them is isolated groove marginal trough (divot) phenomenon.This phenomenon is in the process of the silicon dioxide of wet etching removal silicon nitride and silicon nitride lower floor; Because the local stress of the silicon dioxide at shallow trench edge is different with material, and wet processing has isotropic characteristics and different silicon dioxide had different etch rates and cause.Isolated groove marginal trough phenomenon can cause a lot of negative effects to device, reduces like gate voltage, and electric leakage increases or the like.
Present a kind of method of eliminating or improving isolated groove marginal trough phenomenon is that trench wall is adopted two protective layers; Promptly earlier with thermal oxidation method at trench wall one deck silica protective layer of growing; Follow deposit one deck silicon nitride protective layer again, form the two protective layers (oxide/nitride double liner) of silica/silicon nitride.This method can go up the three-layer thin-film structure that forms the silica-filled layer of silica protective layer (liner oxide), silicon nitride protective layer (liner nitride) and groove in silicon nitride barrier (pad nitride).This structure is brought very big challenge to STI-CMP technology.This is because STI-CMP technology is the flatness and the following substrate of protection that reaches higher usually, all adopts to have the lapping liquid of higher silica to the grinding rate ratio of silicon nitride, and grinding can stop on the silicon nitride barrier (pad nitride) like this.
For this trilamellar membrane structure; Common STI-CMP grinds when finishing and can be parked on silicon nitride (liner nitride) protective layer; Thereby need extra wet process steps to remove silicon nitride protective layer successively, silica protective layer, and silicon nitride barrier and silica barrier layer; Promptly increase process complexity, be unfavorable for the flatness of crystal column surface again.
Summary of the invention
The present invention proposes a kind of CMP method; Use has higher silica and the lapping liquid of the grinding rate ratio of silicon nitride is ground removes the silica-filled layer of groove and be parked on the silicon nitride protective layer (liner nitride); Then grind silicon nitride protective layer (liner nitride) with having the lapping liquid of higher silicon nitride to silica grinding rate ratio; Removing silicon nitride protective layer (liner nitride) fully afterwards; Re-use the original lapping liquid abrasive silica protective layer (liner oxide) of higher silica that have, finally rest on the silicon nitride barrier (pad nitride) the grinding rate ratio of silicon nitride.
The invention provides a kind of cmp method that is used for the two inner wall protection layer shallow ditch groove structure of silica/silicon nitride, it is characterized in that step comprises:
CMP method of the present invention is applicable to the CMP process (STI-CMP) of the shallow trench of the two inner wall protection layers (oxide/nitride double liner) of silica/silicon nitride, can overcome traditional STI-CMP technology and when grinding the two inner wall protection layer shallow trench of silica/silicon nitride, grind the problem less than silicon nitride barrier.
The present invention also provides a kind of sti structure manufacture method, and step comprises:
Step 5.1 use silica that the silicon nitride grinding rate is ground the silica-filled layer of groove than the lapping liquid greater than 1, and grinding stops on the silicon nitride protective layer;
Step 5.2 use silicon nitride that the silica grinding rate is ground the silicon nitride protective layer layer than the lapping liquid greater than 1, and grinding stops on the silica protective layer;
Step 5.3 reuses the abrasive silica of lapping liquid described in the step 5.1 protective layer, and finally stops on the silicon nitride barrier;
Step 5.4, the silicon nitride and the silicon dioxide layer of protection of the outer substrate surface of removal shallow trench.
In the above-mentioned method of the present invention, said silica to the silicon nitride grinding rate than greater than 1 lapping liquid abrasive material being one or both the mixing in silicon dioxide or the ceria; But this lapping liquid also can be other silica compares the lapping liquid greater than 1 to the silicon nitride grinding rate.
In the above-mentioned method of the present invention, said silicon nitride is hot phosphoric acid to the silica grinding rate than the lapping liquid greater than 1, but also can be other silicon nitrides to the silica grinding rate than greater than 1 lapping liquid.
In the above-mentioned method of the present invention, removing the silicon nitride of the outer substrate surface of shallow trench and the method for silicon dioxide layer of protection is wet etching.
The above-mentioned CMP process of the present invention can carry out on same abrasive disk, realizes the multistep polishing through switching lapping liquid; Also can on two ~ three abrasive disks of same CMP board, carry out the multistep polishing successively.
CMP method provided by the invention and STI manufacture method have been avoided the removal silicon nitride protective layer extra in the conventional art and the wet process steps of silica protective layer, have reduced process complexity, and help improving the flatness of crystal column surface.
Description of drawings
Fig. 1 is traditional sti structure manufacture method flow chart, wherein:
Fig. 1 a is silicon oxide deposition and a silicon nitride barrier successively on silicon substrate;
Fig. 1 b is a definition STI isolated area on silicon substrate;
Fig. 1 c is the silicon dioxide layer of protection successively of growing at the STI inwall;
Fig. 1 d is that the filling silica is isolated in deposit;
Fig. 1 e is for removing the silicon dioxide on silicon nitride barrier surface;
Fig. 2 is the two inner wall protection layer STI-CMP process charts of silica/silicon nitride of the present invention, wherein:
Fig. 2 a is STI inwall silicon oxide deposition and silicon nitride protective layer;
Fig. 2 b is that filling silicon dioxide is isolated in deposit;
Fig. 2 c is that CMP removes filling silicon dioxide, stops on the silicon nitride protective layer;
Fig. 2 d is that CMP removes silicon nitride protective layer, stops on the silica protective layer;
Fig. 2 e is that CMP removes the silica protective layer, stops on the silicon nitride barrier.
Embodiment
The invention provides a kind of cmp method that is used for the two inner wall protection layer shallow ditch groove structure of silica/silicon nitride, and a kind of usefulness method that said method is made sti structure is provided.With reference to specific embodiment the method for the invention is described in detail below and describe, so that better understand the present invention, but following embodiment does not limit the scope of the invention.
See figures.1.and.2, sti structure manufacture method of the present invention and CMP method step comprise:
Step 5.1 on abrasive disk, use the abrasive silica lapping liquid that the silica-filled layer of groove is ground, and grinding stops on the silicon nitride protective layer; Said abrasive silica grinding agent to the silica grinding rate to greater than the silicon nitride grinding rate;
Step 5.2 is switched lapping liquid, on same abrasive disk, use hot phosphoric acid lapping liquid that silicon nitride protective layer is ground, and grinding stops on the silica protective layer; Said hot phosphoric acid to the silicon nitride grinding rate greater than to the silica grinding rate;
Step 5.3 reuses the abrasive silica of lapping liquid described in the step 5.1 protective layer, and finally stops on the silicon nitride barrier;
Step 5.4, wet etching is removed the silicon nitride and the silicon dioxide layer of protection of the outer substrate surface of shallow trench.
See figures.1.and.2, sti structure manufacture method of the present invention and CMP method step comprise:
Step 5.1 on abrasive disk, use the ceria lapping fluid that the silica-filled layer of groove is ground, and grinding stops on the silicon nitride protective layer; Said abrasive silica grinding agent to the silica grinding rate to greater than the silicon nitride grinding rate;
Step 5.2 is switched lapping liquid, on same abrasive disk, use hot phosphoric acid lapping liquid that silicon nitride protective layer is ground, and grinding stops on the silica protective layer; Said hot phosphoric acid to the silicon nitride grinding rate greater than to the silica grinding rate;
Step 5.3 reuses the abrasive silica of lapping liquid described in the step 5.1 protective layer, and finally stops on the silicon nitride barrier;
Step 5.4, wet etching is removed the silicon nitride and the silicon dioxide layer of protection of the outer substrate surface of shallow trench.
See figures.1.and.2, sti structure manufacture method of the present invention and CMP method step comprise:
Step 5.1 on abrasive disk, use the ceria lapping fluid that the silica-filled layer of groove is ground, and grinding stops on the silicon nitride protective layer; Said abrasive silica grinding agent to the silica grinding rate to greater than the silicon nitride grinding rate;
Step 5.2 moves to another abrasive disk, uses hot phosphoric acid lapping liquid that silicon nitride protective layer is ground, and grinding stops on the silica protective layer; Said hot phosphoric acid to the silicon nitride grinding rate greater than to the silica grinding rate;
Step 5.3 moves in the 3rd abrasive disk or the step 2.1 on the abrasive disk, reuses the abrasive silica of lapping liquid described in the step 5.1 protective layer, and finally stops on the silicon nitride barrier;
Step 5.4, wet etching is removed the silicon nitride and the silicon dioxide layer of protection of the outer substrate surface of shallow trench.
The method that is used for the STI-CMP method of the two inner wall protection layers (oxide/nitride double liner) of silica/silicon nitride and adopts said method making sti structure disclosed by the invention; Have different oxidation silicon through use the lapping liquid of the grinding rate ratio of silicon nitride is removed silica-filled layer successively; Silicon nitride protective layer (liner nitride) and silica protective layer (liner oxide) finally are parked on the silicon nitride barrier (pad nitride).Thereby avoided the wet process steps of extra removal liner nitride and liner oxide, reduced process complexity, and helped improving the flatness of crystal column surface.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (8)
1. cmp method that is used for the two inner wall protection layer shallow ditch groove structure of silica/silicon nitride is characterized in that step comprises:
Step 1 use silica that the silicon nitride grinding rate is ground the silica-filled layer of groove than the lapping liquid greater than 1, and grinding stops on the silicon nitride protective layer;
Step 2 use silicon nitride that the silica grinding rate is ground the silicon nitride protective layer layer than the lapping liquid greater than 1, and grinding stops on the silica protective layer;
Step 3 reuses the abrasive silica of lapping liquid described in the step 1 protective layer, and finally stops on the silicon nitride barrier;
Step 4, the silicon nitride and the silicon dioxide layer of protection of the outer substrate surface of removal shallow trench.
2. cmp method according to claim 1 is characterized in that, the abrasive material of lapping liquid described in the step 1 is one or more the mixing in silicon dioxide or the ceria.
3. cmp method according to claim 1 is characterized in that, lapping liquid described in the step 2 is hot phosphoric acid.
4. cmp method according to claim 1 is characterized in that, the method for removing the substrate protective layer in the step 4 is a wet etching.
5. manufacturing method of shallow trench structure is characterized in that step comprises:
Step 1, deposit silicon dioxide barrier layer and silicon nitride barrier successively on the silicon substrate;
Step 2 through photoetching and etching, defines shallow channel isolation area on said silicon substrate;
Step 3 at said shallow trench deposit silicon dioxide layer of protection and silicon nitride protective layer successively, forms two inner wall protection layers;
Step 4, substrate surface silicon oxide deposition packed layer around shallow trench and shallow trench;
Step 5, barrier layer and protective layer are removed in chemico-mechanical polishing, and concrete steps comprise:
Step 5.1 use silica that the silicon nitride grinding rate is ground the silica-filled layer of groove than the lapping liquid greater than 1, and grinding stops on the silicon nitride protective layer;
Step 5.2 use silicon nitride that the silica grinding rate is ground the silicon nitride protective layer layer than the lapping liquid greater than 1, and grinding stops on the silica protective layer;
Step 5.3 reuses the abrasive silica of lapping liquid described in the step 5.1 protective layer, and finally stops on the silicon nitride barrier;
Step 5.4, the silicon nitride and the silicon dioxide layer of protection of the outer substrate surface of removal shallow trench.
6. manufacturing method of shallow trench structure according to claim 5 is characterized in that, the abrasive material of lapping liquid described in the step 5.1 is one or more the mixing in silicon dioxide or the ceria.
7. manufacturing method of shallow trench structure according to claim 5 is characterized in that, lapping liquid described in the step 5.2 is hot phosphoric acid.
8. manufacturing method of shallow trench structure according to claim 5 is characterized in that, the method for removing the substrate protective layer in the step 5.4 is a wet etching.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014026549A1 (en) * | 2012-08-13 | 2014-02-20 | 无锡华润上华科技有限公司 | Chemical mechanical polishing method for shallow trench isolation structure |
| CN104347413A (en) * | 2013-08-02 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing FinFET semiconductor device |
| CN104517884A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN105702573A (en) * | 2014-11-27 | 2016-06-22 | 联华电子股份有限公司 | Method for planarizing semiconductor device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5976951A (en) * | 1998-06-30 | 1999-11-02 | United Microelectronics Corp. | Method for preventing oxide recess formation in a shallow trench isolation |
| CN1540741A (en) * | 2003-04-24 | 2004-10-27 | 台湾积体电路制造股份有限公司 | Method for making shallow trench isolation even |
| KR20050067487A (en) * | 2003-12-29 | 2005-07-04 | 주식회사 하이닉스반도체 | Shallow trench isolation method of semiconductor device |
| US7294575B2 (en) * | 2004-01-05 | 2007-11-13 | United Microelectronics Corp. | Chemical mechanical polishing process for forming shallow trench isolation structure |
| CN101154618A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming device isolation region |
-
2011
- 2011-08-29 CN CN201110250266.8A patent/CN102437047B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5976951A (en) * | 1998-06-30 | 1999-11-02 | United Microelectronics Corp. | Method for preventing oxide recess formation in a shallow trench isolation |
| CN1540741A (en) * | 2003-04-24 | 2004-10-27 | 台湾积体电路制造股份有限公司 | Method for making shallow trench isolation even |
| KR20050067487A (en) * | 2003-12-29 | 2005-07-04 | 주식회사 하이닉스반도체 | Shallow trench isolation method of semiconductor device |
| US7294575B2 (en) * | 2004-01-05 | 2007-11-13 | United Microelectronics Corp. | Chemical mechanical polishing process for forming shallow trench isolation structure |
| CN101154618A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming device isolation region |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014026549A1 (en) * | 2012-08-13 | 2014-02-20 | 无锡华润上华科技有限公司 | Chemical mechanical polishing method for shallow trench isolation structure |
| CN104347413A (en) * | 2013-08-02 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing FinFET semiconductor device |
| CN104347413B (en) * | 2013-08-02 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | A kind of method making FinFET semiconductor device |
| CN104517884A (en) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN104517884B (en) * | 2013-09-27 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for making semiconductor devices |
| CN105702573A (en) * | 2014-11-27 | 2016-06-22 | 联华电子股份有限公司 | Method for planarizing semiconductor device |
| CN105702573B (en) * | 2014-11-27 | 2019-03-26 | 联华电子股份有限公司 | Method for planarizing semiconductor device |
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