CN102427368A - A High Speed Successive Approximation Register Analog-to-Digital Converter - Google Patents

Abstract

A successive approximation register analog-to-digital converter (SAR-ADC) predicts compensation values for future cycles. The compensation values are applied to the capacitors in the calibrated Y-side capacitor array to compensate for the capacitance errors of the binary-weighted X-side capacitor array. Two calculation engines pre-calculate predicted-0 and predicted-1 compensation values for the next bit to be converted. At the end of the current cycle, when the comparator determines the current bit, the comparator also controls the multiplexer to select one of the predicted compensation values. Therefore, the compensation value is available at the beginning of the next bit cycle, shortening the calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. The compensation values for the other bits are data dependent. During calibration, the calibration values are accumulated to produce the first conversion compensation value for the first bit to be converted.

Description

A High Speed Successive Approximation Register Analog-to-Digital Converter

【Technical field】

The present invention relates to analog-to-digital converters (ADCs), and more particularly to a pipelined method for increasing the speed of successive approximation register (SAR) ADCs.

【Background technique】

There are often various analog and digital circuits in the system chip. Signal transitions from the digital domain to the analog domain, or vice versa. Analog signals are converted to digital signals for complex digital processing, such as digital signal processors (DSP).

There are various types of analog-to-digital converters (ADCs) that have been widely used in various applications. A flash ADC compares an analog signal voltage to multiple voltage levels in an instant, producing a multi-bit digital value representing the analog voltage. Successive approximation ADCs use a series of stages to convert an analog voltage into digital bits. Each stage compares an analog voltage to a reference voltage and produces a digital bit. In a sub-ranging ADC, each stage compares an analog voltage to several voltage levels, so each stage produces several bits. In the pipeline, subsequent stages produce lower significant digit bits than previous stages.

Algorithmic, cyclic ADCs use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most significant digital bit. The digital bits are then converted back to analog and subtracted from the original analog voltage, producing a residual voltage. This residual voltage is then multiplied by 2 and returned to the comparator to generate the next digital bit. So digital bits are generated in multiple cycles within the same comparator stage.

Figure 1 is a successive approximation register ADC. The successive approximation register SAR 102 receives a clock CLK and contains a register value that is constantly changing to gradually approach the analog input voltage VIN. For example, when compared to VIN 0.312 volts, the value in SAR 102 may start at 0.5, then 0.25, then 0.375, then 0.312, then 0.281, then 0.296, then 0.304, then 0.308, then 0.31, then 0.311, Finally it was 0.312. SAR 102 outputs the current register value to digital-to-analog converter (DAC) 100, which receives a reference voltage VREF and converts the register value into an analog voltage VA.

The input analog voltage VIN is applied to the sample-and-hold circuit 104, which samples and holds the value of VIN. For example, a capacitor can be charged by VIN and then isolated from VIN, maintaining the analog voltage. The input voltage sampled by sample and hold circuit 104 is applied to the inverting input of comparator 106 . The converted analog voltage VA is applied to the non-inverting input of comparator 106 .

The comparator 106 compares the converted analog voltage VA with the sampled input voltage, and when the converted analog voltage is higher than the sampled VIN, a high output is generated, and the register value in the SAR 102 is too high. The register value in SAR 102 is then decremented.

When the converted analog voltage VA is lower than the sampled input voltage, the comparator 106 generates a low output to the SAR 102. The register value in SAR 102 is then too low, and then the register value in SAR 102 is raised for the next cycle.

Register values in SAR 102 are N-bit binary values, where D(N-1) is the most significant bit (MSB) and D0 is the least significant bit (LSB). The SAR 102 may first set the MSB D(N-1), then compare the converted analog voltage VA to the input voltage VIN, then adjust the MSB and/or set the next MSB D(N-2) based on the comparison. This set and compare cycle is repeated until the LSB is set after N cycles. After the last cycle, the end-of-cycle signal EOC is activated, indicating completion. A state machine or other controller can be used with or included within the SAR to control the sequence.

DAC 100 or sample-and-hold circuit 104 may have an array of capacitors. Capacitors have binary weighted values, such as 1, 2, 4, 8, 16, 32, ... multiplied by a minimum capacitor size. For example, a 6-bit DAC can have a bank of 1, 2, 4, 8, 16, 32 multiplied by a minimum capacitance C of capacitors. Higher precision DACs such as 11-bit DACs have larger capacitor values, such as 2 ^N-1 =1024.

Figure 2 shows a SAR ADC resolving an input voltage. The register value of the SAR 102 is initially set to 1/2, or 10000. Comparator 106 determines that input voltage VIN is lower than the converted value from SAR 102, so on the next cycle, SAR 102 is set to 1/4, or 01000. Comparator 106 determines that input voltage VIN is higher than the converted value from SAR 102, so in the third cycle, SAR 102 is set to 3/8, or 01100. Comparator 106 determines that input voltage VIN is lower than the converted value from SAR 102, so in the fourth cycle, SAR 102 is set to 5/6, or 01010. Comparator 106 now determines that the input voltage VIN is higher than the converted value from SAR 102, so in the fifth cycle, SAR 102 is set to 9/32, or 01011. The final comparison is that VIN is higher than the converted value, so the final result is 01011.

While such capacitor array DACs are useful, large size MSB capacitors require a large amount of charge transfer. The minimum capacitor size C can be reduced to reduce the total capacitance of the capacitor array, thus reducing dynamic power requirements. The minimum capacitor size is limited by processing technology. For example, for a metal-metal capacitor, submicron technology allows a minimum physical size of 4x4μm2, with a capacitance of about 16fF.

For accurate results, matching capacitor values in the binary weighted array is very important. In deep submicron processing, inherent device and impedance mismatches limit converter accuracy to around 10 bits.

Accuracy can be improved through calibration. Before the input voltage is converted to a digital value, a series of steps called calibration can be performed. Calibration can measure the mismatch of each capacitor by sharing charge with other array capacitors. Connect and disconnect other array capacitors until a voltage match occurs. Once a final voltage match occurs, a mismatch value is obtained by recording the enable signal for that capacitor.

The procedure is then repeated for the next capacitor in the main array, storing its mismatch value. Once the calibration procedure has been performed on all capacitors in the main array, the mismatch values for each of these capacitors are stored as capacitance coefficients. These capacitance coefficients can then program a second array to subtract out these mismatch errors when processing the analog input voltage VIN. Next the smaller capacitors in the main array are also evaluated and their stored capacitance coefficients are applied to the second capacitor array.

In the example of Figure 2, when MSB D4 is toggled, the MSB capacitor is switched to receive the shared charge and the less effective capacitor is switched off or isolated. The error of the MSB capacitors has been previously calibrated to 10000, and this calibration value of 10000 is applied to the second (calibration) array of DACs to compensate for the MSN capacitor errors in the main array. The value of MSB is determined to be 0. Then the penultimate MSB capacitor is switched to share the charge in the main DAC, but the MSB capacitor is isolated in the main array because the MSB digital value is determined to be 0 (D4=0). At calibration, the penultimate MSB error is determined to be 01000, and the calibration value of 01000 is applied to the second (calibration) array for compensation. The comparator asserts that the penultimate MSB D3 = 1.

On the next cycle, the MSB capacitors are isolated, but the MSB-1 and MSB-2 capacitors are connected to share charge in the main array. The calibration values for the MSB-1 and MSB-2 capacitors are read and added together, resulting in a compensation value of 01100, which is applied to the second array to compensate for the errors of the MSB-1 and MSB-2 capacitors. The comparator determines the MSB-2 digital value D2=0.

In the fourth cycle, the MSB and MSB-2 capacitors are isolated, but the MSB-1 and MSB-3 capacitors are connected to share charge in the main array. The calibration values for the MSB-1 and MSB-3 capacitors are read and added together, resulting in a compensation value of 01010, which is applied to the second array to compensate for the errors of the MSB-1 and MSB-3 capacitors. The comparator determines the MSB-3 digital value D1=1.

In the final cycle, the MSB and MSB-2 capacitors are isolated, but the MSB-1 and MSB-3 and LSB capacitors (D3, D1, D0) are connected to share charge in the main array. The calibration values for the MSB-1 and MSB-3 and LSB capacitors (D3, D1, D0) are read and added together to give a compensation value of 01011 which is applied to the second array to compensate for the connected capacitors D3, D1, D0 error. The comparator determines that the LSB digital value is D0=1. So the end result is that the digital value 01011 represents the analog input voltage.

Figure 3 is a schematic diagram of a SAR ADC with a binary weighted capacitor array and a calibration sub-DAC capacitor array. Binary weighted X-side capacitor array 40 has capacitors 22 - 28 connected to node VX carrying voltage VX and connected to the inverting input of comparator 20 .

The non-inverting input of comparator 20 is connected to the Y-side capacitor array, which is used for error calibration and compensation of capacitors 22-28 in binary-weighted X-side capacitor array 40.

Binary weighted Y-side capacitor array 42 has capacitors 55 - 58 connected to node VY carrying voltage VY and connected to the non-inverting input of comparator 20 . Calibration values Y5:Y0, YT are applied to switches 68-62. YT is the termination bit.

The accuracy of the ADC is one bit less than the number of binary bits stored in the successive approximation register SAR 206. In addition to binary bits X5:X0, SAR 206 also stores termination bits XT. SAR 206 also stores calibration Y side bits Y5:Y0, YT.

Before the differential analog input voltages VINP, VINN are converted to digital values, a calibration procedure is performed. The calibration procedure first finds the mismatch error for each capacitor 28-22 in the binary weighted X-side capacitor array 40, and stores this error coefficient for each X-side capacitor. The calibration procedure is then performed for each capacitor 58-52 in the binary weighted Y-side capacitor array 42, and a Y-side error coefficient is stored for each Y-side capacitor.

Once calibration is complete and normal operation is performed, the analog voltage is converted to a digital value. These error factors are used to continue to control the switches 68-62 in the calibration Y-side capacitor array 42 to subtract out these mismatch errors as each of the X-side capacitors 28-23 is evaluated.

During normal operation, the binary weighted X-side capacitor array 40 has switches 32-38 which switch the input voltage VINP to the bottom plates of capacitors 22-28 during the VIN sampling phase S1 and which switch bit X5 from the SAR 206 during the conversion phase :X0, XT. During the sampling phase S1, the grounding switch 112 is closed, and during the switching phase, the grounding switch 112 is open. The top plates of capacitors 22-28 are connected to the inverting input of comparator 20, which develops voltage VX.

Capacitors 22-28 add a binary weight or multiple of the minimum capacitance size C/64, termination capacitors 22 and 23 have a capacitance of C/64, capacitor 24 has a capacitance of C/32 and capacitor 26 has a capacitance of C/8. The capacitances of capacitors 28 and 27 are C/2 and C/4. The capacitance size and arrangement of the binary-weighted X-side capacitor array 40 on the X-side and the capacitance size and arrangement of the binary-weighted Y-side capacitor array 42 are matched.

During the conversion phase, the X-side bits X5:X0, XT from the SAR 206 are applied to the bottom plates of the capacitors 22-28 in the binary-weighted X-side capacitor array 40. During the sampling phase S1 of normal operation, the backplane is connected to VINP. The control logic 204 can generate a control signal such as S1 and adjust the value in the SAR 206 in response to the comparison result from the comparator 20. Once all bits in the SAR 206 have been adjusted, make the busy signal negative to indicate the end of the conversion.

The binary weighted Y side capacitor array 42 has switches 62-68 which switch the input voltage VINN to the bottom plates of capacitors 62-68 during the first sampling phase and which switch bits Y5:Y0 from the SAR 206 during the conversion phase of normal operation , YT. During the sampling phase S1 the grounding switch 114 is closed, and during the conversion phase the grounding switch 114 is open. The top plates of capacitors 52-58 are connected to the inverting input of comparator 20, which develops voltage VY.

During normal operation, a differential analog input voltage is applied to inputs VINP, VINN. If a single-ended analog input voltage is used, it will be applied to VINP, while a fixed voltage such as ground or VDD/2 can be applied to VINN. Binary-weighted X-side capacitor array 40 can serve as a sample-and-hold circuit, while binary-weighted Y-side capacitor array 42 can serve as DAC 100 in FIG. 1 .

FIG. 4A shows the DAC runtime of prior art FIG. 3 . During calibration, a calibration value is stored for each capacitor 22-28 in FIG. In the process of converting analog voltage to digital voltage, usage is a top-down process. The MSB is verified first by charge sharing with MSB capacitor 28 , whose calibration values Y5 : Y0 are applied to calibrate capacitors 62 - 68 in Y-side capacitor array 42 . The smaller capacitor in the binary weighted X-side capacitor array 40 is then used to check the next smaller digital bit. The calibration value applied to the calibration Y-side capacitor array 42 at each step depends on which of the capacitors 62-68 is connected to line VX and shares charge in that cycle, depending on the bit being checked, the earlier the result (the sooner High effective bit), the earlier the check is also. Therefore a compensation value must be calculated at each step and depends on earlier results.

The calibration value applied to calibrate the Y-side capacitor array 42 is called the compensation value because it is the sum of the calibration values of the currently connected capacitors in the X-side capacitor array 40 that are binary weighted.

In FIG. 4A, bit N+1 is converted from analog to digital value, then bit N, then bit N-1. A conversion-cycle clock CLK is synchronized with the conversion.

At the beginning of each bit period, during time period 120, a conversion value is calculated. During time period 120, the calibration values of the capacitors connected in the binary weighted X-side capacitor array 40 are read and added to obtain the converted value. The calculated conversion values are then applied to the capacitors in the calibration Y-side capacitor array 42 during time period 12, for example by switching voltages to these capacitors. Charge sharing then occurs and the voltage applied to comparator 20 changes. During time period 124, the comparator output will finally give a stable result. Analyze the comparator results to determine a digital value for bit N+1.

Once the digital value of bit N+1 is determined, the capacitors in the binary weighted X-side capacitor array 40 can be switched to verify the next bit N. The offset value for bit N cannot be determined until the result of bit N+1 is confirmed, which is not known until the comparator is determined during time period 124 .

When a higher frequency is used for the cycle clock CLK, such as 1GHz, then the time used for calculation and analog comparison is reduced. FIG. 4B is a graph showing reduced time at higher switching frequencies. The compensation value CAL_CAP is not available until the calculation is completed during time period 120 . A higher frequency of CLK means that these calculations take a larger portion of the time, and the time period 120 is stretched. That would allow less time to apply these compensation values to calibrate the Y-side capacitor array 42 . Analog comparisons would also take up more time periods 124 . Thus, there is not enough time 14 for analyzing the comparison result and the start-up time until the next CLK rising edge. Therefore higher frequency operation may not be feasible due to the considerable time required to read calibration values and calculate compensation values per bit period during conversion.

Desired ADC with a calibration DAC for measuring capacitance mismatch error. It is expected that the SAR ADC can generate conversion values from stored calibration values with higher efficiency to allow higher speed operation. It is also desirable to have a calibrated ADC that can run at high frequencies.

【Description of drawings】

Figure 1 is a successive approximation register ADC.

Figure 2 shows a SAR ADC resolving an input voltage.

Figure 3 is a schematic diagram of a SAR ADC with a binary weighted capacitor array and a calibration sub-DAC capacitor array.

FIG. 4A shows the DAC runtime of prior art FIG. 3 .

FIG. 4B is a graph showing reduced time at higher switching frequencies.

Figure 4C shows the precomputation of two compensation values in the previous bit period in a pipelined SAR-ADC.

Figure 5 is a block diagram of a SAR-ADC with precomputed compensation values.

Figure 6 is a more detailed block diagram of the compensation precalculated control logic.

Figure 7 is a flowchart of a calibration process.

FIG. 8 is a flowchart of a conversion process using precomputed predicted calibration values.

FIG. 9 is a more detailed block diagram of a SAR-DAC that pre-computes predicted offset values to reduce computation delay.

【Detailed ways】

The present invention relates to an improved calibrated SAR-DAC ADC. The following description enables one skilled in the art to make and use the invention presented herein in accordance with a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The inventors have recognized that the calculation of the compensation values can limit the high frequency operation of the SAR-ADC. The compensation value calculation for one bit depends on the result of the analog comparison of the previous bit. However, the inventors have realized that there are only two possible comparison outputs. Comparison result and bit can be 0 or 1. The offset value of a bit may be calculated twice. It can be assumed that the previous bit is 0 to calculate the compensation value, and it can be assumed that the comparison result of the previous bit is 1 to calculate the compensation value again.

When both possible compensation values are pre-calculated, then using a simple multiplexer (mux), one of the two possible values can be selected once the result of the comparison is known. Thus the computation latency can be reduced from a complex addition latency to a multiplexing latency.

Figure 4C shows the precomputation of two compensation values in the previous bit period in a pipelined SAR-ADC. For bit N+1, during time period 120, two calibration offset values are calculated, CAL_CAP_IF1 (which assumes that for bit N+1 the analog compare output will be 1) and CAL_CAP_IF0 (which assumes that for bit N+1 the analog The comparison output will be 0). In this example, CAL_CAP_IF1 is evaluated as 0D (00001101), and CAL_CAP_IF0 is evaluated as 0E (00001110). During analog compare time period 124, when comparator 20 (FIG. 3) determines that the result of bit N+1 is 0 or 1, there are already two precomputed offset values OD and 0E. In this example, bit N+1 is 1 after the output COMP of comparator 20 is asserted at time 128 (ie, the rising edge of CLK).

At time 128, the rising edge of CLK samples COMP as 1 and stores the result as 1 for the transition of bit N+1. The multiplexer logic selects the precomputed compensation value CAL_CAP_IF1, which is 0D, as the compensation value for bit N. Discard CAL_CAP_IF0. After a multiplexing delay of time period 120', CAL_CAP is available at 0D. Capacitors in binary weighted X-side capacitor array 40 and calibration Y-side capacitor array 42 are switched for switching bit N, and the value CAL_CAP is applied to the capacitors in calibration Y-side capacitor array 42, allowing an analog comparison to occur. A digital value of 0 is found for bit N because COMP is going low.

The compensation value for bit N-1 is pre-calculated at time period 120', and bit N is given as 02 and 05 to CAL_CAP_IF1 and CAL_CAP_IF0. On the next rising edge of CLK, select CAL_CAP_IF0 as CAL_CAP.

The comparison result COMP meets the setup time (Setup time) 14, so after the rising edge of time 128CLK, the multiplexer can select from CAL_CAP_IF1 and CAL_CAP_IF0. Once CAL_CAP has stabilized, at time period 12, the capacitor is switched. Note that time period 12 is greatly increased because there is no delay by CAL_CAP_IF1 or CAL_CAP_IF0, only the multiplex delay for CAL_CAP. Indeed, times 120 and 12 would overlap due to precalculation. Therefore CLK can use a higher frequency.

Figure 5 is a block diagram of a SAR-ADC with precomputed compensation values. SAR 102 continuously controls capacitor sharing charge in DAC 100, using reference voltage VREF to verify analog voltage VIN. A differential analog voltage can also be used instead. Successive bits are checked and the comparator 106 signals the SAR 102 when the digital value D(N-1):D0 is less than or greater than the analog voltage VIN.

Before the analog voltage is converted to a digital value, the calibration control logic 130 starts. For example, at initialization, the calibration control logic 130 may start. Calibration control logic 130 operates with SAR 102 to test each capacitor in the DAC array in DAC 100 to obtain a calibration value for each capacitor. The calibration value represents the error in the capacitance value of that capacitor, and the calibration value is stored in the calibration result register 132 .

After the calibration is completed, when the analog voltage VIN is to be converted into a digital value D, the compensation preprocessing 140 receives the current configuration of the capacitors of the DAC 100 from the SAR 102, and then reads the calibration values of these capacitors from the calibration result register 132. For each digital bit that is cycled or checked, two offset values are generated - one offset that assumes the previous bit was 1, and another offset that assumes the digital bit was 0.

Compensation preprocessing 140 runs one cycle ahead, so it precomputes compensation values for the next bit while the current bit is still being parsed. When the compensation preprocessing 140 calculates the two compensation values, the comparator 106 has not resolved its output.

Figure 6 is a more detailed block diagram of the compensation precalculated control logic. Calibration control 154 starts before the analog voltage is converted, such as after initialization. Calibration control 154 performs calibration for each capacitor of binary-weighted X-side capacitor array 40 (FIG. 3), determining their error, represented by a calibration value for the capacitor. Calibration values are stored in calibration registers 164 . Calibration accumulator 156 accumulates calibration values for use in generating calibration and compensation values for capacitor combinations.

In particular, the first conversion compensation engine 160 reads the accumulated calibration value from the calibration accumulator 156 and generates a compensation value for the first bit to be verified for each conversion, the first bit being the MSB from top to bottom conversion. Because the MSB is converted in the first conversion cycle, there is no pre-calculation of the previous cycle, so the pre-computation is performed by the first conversion compensation engine 160 . Since all conversions start with the MSB, precomputation for the MSB can be performed at once and used for all conversions. These conversions will be different after the MSB and subsequent bits have been converted, so the first conversion compensation engine 160 only generates precomputed conversion values for the first bit MSB.

Calibration accumulators 156 may also be used to assist calculation engines 150, 151 in pre-computing predicted compensation values upon conversion. The accumulated intermediate compensation values may be stored in compensation register 162 for later cycles.

The calculation engine 150 assumes that the analog comparator will determine that the current bit is 0, and calculates a predicted-0 compensation value based on this prediction. The computation engine 151 assumes that the analog comparator will determine that the current bit is 1, and computes a prediction-1 compensation value based on this prediction. The calculation engines 150, 151 may read from the calibration registers 164 the respective calibration values for the capacitors that are predicted to switch to charge sharing in the next cycle. Computation engines 150, 151 may also read previous compensation values or other intermediate values from compensation registers 162 to assist in calculations. For example, in the current forecast, there may be no change in the upper capacitor, only the lower capacitor. So the calculation engine 150, 151 can read the previous cycle's compensation value from the compensation register 162, and then adjust the lower capacitors, instead of calculating the compensation values directly from the calibration values for all capacitors.

During calibration and conversion, SAR control logic 155 controls the switching sequence of capacitors in the DAC array. During conversion, the analog comparison result COMP from comparator 106 (FIG. 5) is applied to multiplexer 152, and when the analog comparison result shows that the current bit is 0, a predicted-0 result is selected from calculation engine 150, or When the simulation comparison result shows that the current bit is 1, the prediction-1 result is selected from the calculation engine 151 . This happens at the end of the current bit period.

When the next bit is to be evaluated, at the beginning of the next cycle, the compensation value selected by the multiplexer 152 is applied to the calibration Y-side capacitor array 42, thus setting the error value for the next bit to be evaluated. The delay brought by the multiplexer 152 is much smaller than the delay brought by the calculation engines 150 and 151, so the next cycle has more time for the switch to switch, for the analog voltage to solve the charge sharing, and for the comparator 106 to output the result to the next bit.

The compensation value selected by the multiplexer 152 may also be stored in the compensation register 162 for use by the calculation engines 150, 151 in calculating the predicted compensation value.

Figure 7 is a flowchart of a calibration process. Calibration begins with the MSB capacitors in the binary weighted X-side capacitor array 40, and then all smaller capacitors are calibrated until the LSB capacitors are calibrated. The SAR DAC control logic sets the switch and voltage values in the binary weighted X-side capacitor array 40 and the calibration Y-side capacitor array 42 for calibrating the MSB capacitors, as in step 302.

To determine the calibration value for the MSB capacitor, the switches and voltages are first set at step 302, and then some switches are switched at step 304, moving the charge. When the switch is toggled, the voltage on the lines VX, VY (FIG. 3) changes. The amount of voltage change is related to charge and capacitance, and the charge conservation is Q=CV. Therefore, by measuring the voltage change, the capacitance change caused by the switching can be deduced.

After switching, the analog comparator compares the new voltages VX, VY, and outputs the result after a period of time, as in step 306 . The output value of the comparator shows which voltage VX, VY is greater. Sometimes, multiple verifications of the switch combination may be required to determine the error value of the capacitor being verified. If the error has not been determined, as in step 310 , switch the switches into different combinations, as in step 304 , and then repeat the analog comparison, as in step 306 .

Once the error value for the capacitor being calibrated has been determined, step 310 , the calibration value for that capacitor is written into a calibration register, step 314 . The calibration accumulator also adds the calibration value and performs an addition operation for calculating the MSB first conversion compensation value, as in step 316 .

When there are more capacitors to be calibrated, as in step 312 , then the next capacitor is selected to be calibrated, such as the MSB-1 capacitor, and the process repeats from step 320 . The calibration value for this capacitor is finally determined and stored (step 314 ), its calibration value is added to a calibration accumulator and the earlier calibration values are accumulated (step 316 ).

When all capacitors in the binary-weighted X-side capacitor array 40 have been calibrated, the calibration accumulator contains the final value of the MSB first converted offset value. Therefore the first transition offset value for the MSB does not have to be recalculated for each conversion since the switch setting for checking the MSB is the same for all transitions. Therefore during calibration, the converted value for the first period (converted MSB) is already precalculated.

FIG. 8 is a flowchart of a conversion process using precomputed predicted calibration values. After all calibration values have been determined, after the MSB's first conversion offset value has been calculated, the conversion begins.

The SAR-DAC control logic sets the switches and voltages for verifying the current bit to be converted, step 320 . The switch setting is the same as the first transition when checking the MSB, but depends on the higher order bits already transitioned when transitioning the middle and LSB bits. So the switch setting of the middle bit depends on the result of an earlier conversion, or is data-dependent.

To correct the capacitance error of the switched capacitors in the binary weighted X-side capacitor array 40 , a compensation value is applied to the capacitors in the calibration Y-side capacitor array 42 , as in step 322 . The compensation value, the predicted-1 value or the predicted-0 value, is selected by multiplexer 152 (FIG. 6). The selected compensation value is used to calculate two predicted compensation values for the next bit, as in step 330 .

The SAR-DAC control logic waits for the comparator output, step 324, and determines and stores the result of the current bit as 0 or 1, depending on the comparator output, step 326. If there are more bits to convert from analog to binary digital value, step 332, then the next most significant bit is selected for conversion. In step 334, the result of the analog comparator (steps 324, 326) is used by the multiplexer 152 to select the predicted-0 or predicted-1 compensation value produced in the earlier step 330, and then the process returns and the SAR-DAC control logic The switch is set for switching the next bit, as in step 320 . The compensation values selected in step 334 are applied to the capacitors in the calibration Y-side capacitor array 42 , as in step 322 , to compensate for errors in the switched capacitors in step 320 . Repeat the process for the next bit until the LSB is reached.

FIG. 9 is a more detailed block diagram of a SAR-DAC that pre-computes predicted offset values to reduce computation delay. The SAR control logic 155 reads the compare output COMP from the comparator 106 to determine the digital value of the current bit, and determines the switch settings for the next cycle to convert the next bit. DAC control 172 sets the switches in DAC 100 and adjusts capacitors for charge sharing to generate a voltage that is applied to comparator 106.

Compensation capacitor control 174 reads the compensation value from compensation register 162 and applies or switches a voltage representing the compensation value to the capacitors in calibration Y-side capacitor array 42 (FIG. 3) in DAC 100. The error representing this compensation value is therefore subtracted.

Computation engines 150, 151 precompute two predicted offset values, assuming that comparator 106 will determine that the current bit is 1 (prediction-1 offset value from calculation engine 151), and assuming comparator 106 will determine that current bit is 0 (from calculation Engine 150 prediction - 0 offset value). Once the output COMP of the comparator 106 is determined, the multiplexer 152 selects one of the predicted compensation values from the calculation engines 150 , 151 . The predicted compensation value selected by multiplexer 152 is stored in compensation register 162 and used by compensation capacitor control 174 for the next cycle to set the error value for calibration Y-side capacitor array 42 in DAC 100.

During calibration, calibration control 154 determines the sequence of switches and applies voltages to determine a calibration value for each capacitor, which is stored in calibration register 164 . These calibration values are accumulated by the calibration accumulator 156 so that when all capacitors are calibrated, the value in the calibration accumulator 156 can be used by the first conversion compensation engine 160 to calculate the first conversion value. The first converted value is the MSB. The first conversion value is not data dependent since no bits are higher than the MSB. The same first conversion offset value can therefore be used to convert the MSB for all analog voltages to be converted.

[alternative embodiment]

The inventors also contemplate some other embodiments. For example calibration values do not have to be stored for all capacitors, such as termination capacitors or one or more LSB capacitors, since larger errors tend to occur on larger capacitors. Although two compensation values are described to be calculated in parallel using two calculation engines, it is also possible to use a single calculation engine twice, if sufficient time is available. The precomputation can be extended to simulate comparison time 124 instead of being done at time period 120 . Alternatively, four conversion values can be precomputed in very short clock cycles, when the computation takes two clock cycles.

Instead of just one calibration value for a capacitor, there can be several calibration values or parameters used in one equation to calculate the calibration value for a particular arrangement or order of capacitors. Instead of just adding the capacitance values of several capacitors, there can be secondary effects which are different combinations of compensating capacitors. The calibration values can thus be more complex but still be used to generate compensation values which are a function of multiple factors. Calibration calculations and calibration values can be more complex than simply adding or accumulating individual capacitor error values. Each bit cycle can have several phases between which the switch settings and the value applied to the capacitor can be toggled or adjusted to move charge and adjust the voltage applied to the comparator. Additional stages can be inserted to isolate switching noise caused by opening switches.

For timing and pipeline purposes, latches, flip-flops, registers, and other storage devices can be inserted on the logic and data paths to allow clock synchronization. Buffers, capacitors, filters, resistors and other components may also be added for various purposes.

Instead of a full binary weighted capacitor array, a combination of a binary weighted capacitor array and an unweighted capacitor array can also provide the desired accuracy, but still reduce overall capacitance and dynamic power. Although the application in a SAR ADC is described, the circuit and calibration procedure can be used in other applications and systems.

The number of bits in the binary-weighted X-side capacitor array 40, the binary-weighted Y-side capacitor array 42, and the calibration sub-DAC array 44 can be adjusted. The smallest coefficient, for the control of the termination capacitor, may be discarded in some embodiments.

Instead of a top-down approach where the MSB capacitor is calibrated first, then the next MSB, repeating until the last LSB capacitor is calibrated, there can be instead a bottom-up sequence where the LSB capacitor is calibrated first and the MSB capacitor last .

Differential and single-ended analog voltages are interchangeable. A single-ended analog voltage can be applied to one differential input, while a reference voltage can be applied to the other differential input.

Binary weighted capacitor arrays can be thermometer weighted or use Gray codes, or other weighting arrangements. The binary bits from SAR 206 may be combined with other control or timing information, such as information from control logic 204 or sequencers or multi-stage non-overlapping clocks.

The number of bits of register values in SAR 206 can be adjusted to achieve the desired precision. For example, when N is 16 bits and VREF is 2 volts, the LSB represents 30 microvolts, which is the accuracy of the ADC. Different numbers of bits can substitute for different precisions, and the number of bits can be fixed or variable.

Some embodiments do not necessarily use all elements. For example, switches may be added or removed in some embodiments. Different switches can be used, such as two-way switches or three-way switches. Multiplexers can also be used as switches. Input resistance can also be added to VINP, VINN, or use more complex input filters. Multi-level switches can be used, such as two-way switches are used as switches, and then a master switch connects VDD or GND to these two-way switches.

Although binary weighted capacitors have been described, other weightings may be used, such as decimal weighted capacitors, prime number weighted capacitors, or linear weighted capacitors, or octal weighted capacitors. Numeric values can be in these other number systems, such as octal numbers, instead of binary numbers.

By interchanging the inverting and non-inverting inputs, inversion can be added without changing the overall functionality, so they can be considered equivalent. During the conversion phase, the digital value passing through the switch can be applied directly to the switch, either as data through the switch, or as a control for the switch. More complex switches can use this digital value to generate a high or low voltage, which is applied across the capacitor through the complex switch. Other embodiments of connecting the digital value to a capacitor via a switch are also possible.

The resistor and capacitor values can be varied in different ways. Capacitors, resistors and other filtering components can be added. Switches can be n-channel transistors, p-channel transistors, or transmission gates with n-channel and p-channel transistors in parallel, or more complex circuits, and can be passive or active, amplifying or non-amplifying of.

Additional components may be added at various nodes, such as resistors, capacitors, inductors, transistors, etc., and parasitic components may also be present. Enabling and disabling the circuit may be accomplished with additional transistors or otherwise. Pass-gate transistors or transmission gates can be added for isolation.

The final dimensions of transistors and capacitors may be chosen after circuit simulation or field testing. Metal masks or other programmable features may be used to determine final capacitor, resistor, or transistor dimensions. Capacitors can be connected in parallel to form a larger capacitor which has the same fringing or boundary effects as several capacitor sizes.

A reference voltage can be compared to a separate analog voltage, or a differential analog voltage can be compared. A differential input voltage can be latched, and this latched single-ended voltage is then compared to the DAC voltage. The first voltage can be sampled by a capacitor and then the second voltage can be sampled by the same appliance. The differential charge is stored in another capacitor via the amplifier's feedback. Another way to compare differential analog voltages is to place a differential amplifier across the input with a defined gain. While an op amp could be used, other types of amplifiers, such as unamplified compare registers, can also be used.

An equalization switch can be added between VX and VY. Two ground switches can be used on the true complement input line of the comparator 20 input. Instead of ground, some switches can be connected to another fixed voltage such as VDD or VDD/2.

The Background of the Invention section may contain background information about the problem or circumstances of the invention rather than describe other prior art. Accordingly, the inclusion of material in the Background section is not an admission by Applicants of prior art.

Any method or process described herein is machine-implemented or computer-implemented and is intended to be performed by a machine, computer or other device and is not intended to be performed by humans alone without the assistance of such machines. Tangible results produced may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio production devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result.

The foregoing description of embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims (18)

1. A pipeline compensation successive approximation register SAR digital-to-analog converter, including: a binary weighted X-side capacitor array having weighted capacitance values of first capacitors, wherein the first capacitors are connected to a first charge sharing line and a plurality of first switches; calibrating the Y-side capacitor array having second capacitors of weighted capacitance values, wherein the second capacitors are connected to a second charge sharing line and a plurality of second switches; an analog comparator that compares the first charge-sharing line and the second charge-sharing line to generate a comparison output; a compensation register storing a compensation value representing capacitance error; a calibration register, which stores calibration values of the capacitors in the binary-weighted X-side capacitor array, the calibration values representing capacitance errors; a compensation capacitor controller that reads a compensation value from the compensation register and applies the compensation value to the plurality of second switches such that the calibration Y-side capacitor array compensates capacitance errors in the binary-weighted X-side capacitor array; a first calculation engine that reads the calibration value from the calibration register and generates a predicted-zero compensation value by assuming that the analog comparator produces a comparison output in a first state; a second calculation engine that reads the calibration value from the calibration register and generates a predicted-1 compensation value by assuming that the analog comparator produces a comparison output in a second state; a multiplexer that receives a predicted-0 compensation value from the first calculation engine and a predicted-1 compensation value from the second calculation engine, the multiplexer outputs the predicted The -0 compensation value is used as the next compensation value, and when it is the comparison output of the second state, the multiplexer outputs the predicted -1 compensation value as the next compensation value; wherein the next compensation value from the multiplexer is stored in the compensation register as the compensation value for the next bit which is converted after the current bit; Compensation values are therefore pre-calculated based on the predictions of the comparative outputs. 2. pipeline compensation successive approximation type register SAR digital-to-analog converter as claimed in claim 1, Wherein the first calculation engine generates a predicted-0 compensation value before the analog comparator generates a comparison output; Wherein the second calculation engine generates a prediction-1 compensation value before the analog comparator generates a comparison output; The comparison output will determine a digital value for the current bit transition, and the compensation value required for the next bit will be completed during the current bit transition; Therefore the compensation value is converted in advance. 3. pipeline type compensation successive approximation type register SAR digital-to-analog converter as claimed in claim 2, also comprises: Calibration control logic for activating the first and second switches to continuously calibrate the first capacitor in the binary-weighted X-side capacitor array, determine a calibration value and apply it to calibrate the second capacitor in the Y-side capacitor array to compensate for the first The capacitance error of the capacitor, where the calibration value is stored in the calibration register, in response to the operation of the calibration control logic. 4. pipeline type compensation successive approximation type register SAR digital-to-analog converter as claimed in claim 3, also comprises: A calibration accumulator is used for accumulating the calibration values generated by the calibration control logic for multiple first capacitors in multiple calibration cycles to generate an accumulated calibration value; Calibration values are therefore cumulative. 5. pipeline compensation successive approximation type register SAR digital-to-analog converter as claimed in claim 4, also comprises: The first conversion compensation engine is used to generate the first compensation value for the first period, and the first conversion compensation engine reads the accumulated calibration value from the calibration accumulator; Wherein the first compensation value is used as the compensation value in the initial period. 6. The pipeline compensated successive approximation register SAR digital-to-analog converter as claimed in claim 5, wherein the most significant bit (MSB) digital value converted from the analog voltage is generated in the initial cycle. 7. The pipelined compensation successive approximation register SAR digital-to-analog converter as claimed in claim 2, further comprising: The SAR control logic, responsive to a bit clock, is used to enable the compensation register to latch the next compensation value from the multiplexer into the compensation register as the compensation value for the next bit, which is at is converted after the current bit in response to the first edge of the bit clock, Therefore the next offset value from the multiplexer is latched by the first edge of the bit clock. 8. A method of converting an analog voltage to a digital value, comprising: (a) setting switches in the first capacitor array such that target capacitors in the first capacitor array share charge with the first line; Read the compensation value from the compensation register; applying the compensation value to the second capacitor array, sharing the second charge with the second line; wherein the second charge compensates for an error in the target capacitor; The comparator compares the voltages of the first line and the second line to generate a comparison output; Before the output of the comparator is generated, when the output of the comparator is in the first state, the first predicted compensation value which is the next compensation value is generated, and when the output of the comparator is in the second state, the first predicted compensation value which is the next compensation value is generated. 2. Predictive compensation value; inputting the first predictive compensation value and the second predictive compensation value to a multiplexer; At the end of the bit period, use the comparator output to control the multiplexer to select the first predictive compensation value when the comparator output is in the first state, and select the second predictive compensation value when the comparator output is in the second state value; At the end of the bit period, store the bit result output by the comparator, which is the digital value of one bit; Repeat from (a) for the other bits of the digital value. 9. The method of claim 8, wherein the compensation value includes an error of the comparator output being in the first state at the earlier bit period of the target capacitor, but does not include an error at the second state of the comparator output of the target capacitor at the earlier bit period, Wherein the second charge compensates the error of the target capacitor in the earlier bit period, which is connected to the first line in the current bit period. 10. The method of claim 9, further comprising: calibrating the capacitors in the first array to generate a calibration value representing an error in the capacitors of the first array; Store the calibration value into the calibration register; Wherein generating the first predicted compensation value includes: reading the compensation value from the compensation register, from A calibration register reads a calibration value, and combines the compensation value and the calibration value in response to the configuration of the switches in the first capacitor array. 11. The method of claim 10, wherein the capacitors in the first capacitor array and in the second capacitor array have binary weighted capacitance values. 12. The method of claim 9, wherein the computation of the transition value for bit N is precomputed in the period of bit N-1, where N is an integer. 13. The method of claim 9, wherein the first predicted compensation value and the second predicted compensation value are generated in parallel at the same time in a previous cycle. 14. A precomputed compensated analog converter comprising: a first charge sharing line; a plurality of first switches; a first array of capacitors having weighted capacitance values, wherein the first array of capacitors is connected to a first charge sharing line and a plurality of first switches; the first terminating capacitor in the first array of capacitors, the first terminating capacitor and the smallest capacitor have the same minimum capacitance, wherein the two capacitors in the first array of capacitors have the same minimum capacitance; a first analog input having an analog input voltage; a plurality of first numerical values; wherein during a sampling phase of normal operation, the plurality of first switches connects the first analog input to the first array capacitor; wherein after the sampling phase of normal operation, during the conversion phase, the plurality of first switches connect the first digital value to the first array capacitor; a second charge sharing line; a plurality of second switches; a second array of capacitors having weighted capacitance values, wherein the second array of capacitors is connected to a second charge sharing line connection and a second plurality of switches; The second terminating capacitor in the second array of capacitors, the second terminating capacitor and the smallest capacitor have the same minimum capacitance, wherein the two capacitors in the second array of capacitors have the same minimum capacitance; a second analog input having an analog input voltage; multiple compensation digital values; wherein during a sampling phase of normal operation, the plurality of second switches connects the second analog input to the second array capacitor; wherein after the sampling phase of normal operation, during the conversion phase, a plurality of second switches connect the compensation digital value to the second array capacitor; a comparator, which receives a first comparison voltage of the first charge sharing line, and compares the first comparison voltage with a second voltage of the second charge sharing line to generate a comparison output; control logic for adjusting to first digital values of the plurality of first switches, for adjusting to second digital values of the plurality of second switches; The compensation register is used to store the compensation digital value of the current cycle; The first predictive calculation engine, which reads the compensation digital value from the compensation register, generates a next compensation digital value of prediction-0 by assuming that the comparison output of the current period produced by the comparator is 0; The second prediction calculation engine, which reads the compensation digital value from the compensation register, generates the next compensation digital value of prediction-1 by assuming that the comparison output of the current cycle produced by the comparator is 1; a multiplexer that outputs the next compensated digital value from the prediction-0 of the first prediction calculation engine when the comparison output is 0, and outputs the prediction-0 from the second prediction calculation engine when the comparison output is 1 next offset digital value of 1; Its compensation register stores the next compensated digital value of predict-0 or the next compensated digital value of predict-1 from the multiplexer for the next current cycle; The predicted next compensation digital value is thus selected by the multiplexer and precomputed in the previous cycle. 15. The precomputed compensated analog converter of claim 14, further comprising: a first ground switch that grounds the first charge-sharing line; a second ground switch that grounds the second charge-sharing line; Wherein the first charge sharing line is grounded, which is the response control logic. 16. The precomputed compensated analog converter of claim 15, further comprising: a calibration controller for generating a calibration value for each capacitor in the first higher bank of the first array of capacitors, the calibration value representing a mismatch in capacitance values; When calculating the next compensation digital value of prediction-0 and the next compensation digital value of prediction-1, the first prediction calculation engine and the second prediction calculation engine read the calibration value generated by calibration. 17. The precomputed compensated analog converter of claim 16, further comprising: a first conversion compensation engine activated by the calibration controller for generating a first conversion compensation value for the converted MSB; Wherein in the MSB conversion period, the first conversion compensation value is applied to the plurality of second switches as a compensation digital value. 18. The precomputed compensated analog converter of claim 14, further comprising: a first calibration means for generating a first calibration value for each capacitor in the first array of capacitors, the first calibration value being applied to the second switch during the sampling phase to cancel capacitance mismatch and switching noise; second calibration means for generating a second calibration value for each capacitor in the second array of capacitors, the second calibration value being applied to the first switch during the sampling phase to cancel capacitance mismatch and switching noise; Calibration values are therefore generated and applied to counteract the mismatch. the

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