CN102427365B - Clock conversion and locking method and its circuit - Google Patents

Abstract

A clock conversion and locking method, providing a clock A with a square wave waveform and a clock B with a sine wave waveform; calculating a common divisor frequency from the frequency values of the two clocks as the conventional frequency of the two clock conversions; The clock A obtains the conventional reference clock frequency of the clock A by counting frequency division according to the conventional frequency; the frequency of the conventional reference clock frequency is used as a parameter to perform A/D sampling on the clock B to obtain the clock B The sampling frequency; by the reference clock frequency of the convention and the sampling frequency as a parameter design phase-locked loop; the output frequency of the phase-locked loop is connected to the frequency control terminal of the clock B to complete the closed-loop work of the entire system, The locking and conversion of the clock A to the clock B is realized without frequency multiplication to a high multiple frequency.

Description

Clock conversion and locking means and circuit thereof

Technical field

The present invention relates to communication and navigation field, relate in particular to clock conversion and locking means and circuit thereof.

Background technology

In communication and navigation system, in order to realize frequency inverted and locking, commonly used is reference clock, radio frequency clock or other use clocks at present, and adopts the frequency translation mode of frequency multiplication or frequency division to obtain the required various frequencies of equipment, realizes by designing a suitable lock times assembly.

Can realize frequency multiplication with PHASE-LOCKED LOOP PLL TECHNIQUE, the frequency doubling clock of stable output, and output clock phase and the input clock phase relation constant, and some the design in, this phase relation can also be adjusted according to system's needs.But the shortcoming of this method is, phase-locked loop has certain bandwidth, frequency range to input clock has requirement, can only carry out process of frequency multiplication to the clock of certain frequency scope, for example the device with phase-locked loop of some logical device manufacturer production can only carry out process of frequency multiplication to the clock higher than 25MHz, so the method makes Change In Design restricted.In addition, if realize PHASE-LOCKED LOOP PLL TECHNIQUE in the logical device without phase-locked loop, resource occupation is large, and design cost is high; If realize PHASE-LOCKED LOOP PLL TECHNIQUE by circuit design, increased again complexity and the debugging difficulty of circuit, and design cost is higher.

Above content can application reference number is 200520132730.3, and name is called the Chinese utility model patent of clock synchronous doulbing circuit.Although this patent discloses a kind of clock synchronous doulbing circuit, can and need not under the condition of phase-locked loop at low cost, highly compatible, obtain the frequency doubling clock stable, that duty ratio is adjustable, phase relation is constant, but in some specific applications, may there be reference clock and uses clock not have the situation of integral frequency divisioil.Adopt the output of 10MHz clock as present atomic frequency standard, satellite navigation needs the 10.23MHz clock reference, if adopt a traditional minute frequency multiplier circuit to realize two kinds of clock lock conversions, needs frequency multiplication to higher frequency, and circuit is relative complex also.Under given conditions, if two kinds of clock lock multiple relations are complicated, may cause frequency to be difficult to lock situation.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of clock conversion and locking means and circuit thereof, solve the also problem of relative complex of the frequency limitation of minute frequency multiplier circuit in the conversion of traditional clock and locking design and circuit, particularly complicated for two kinds of clock lock multiple relations, the problem that may cause frequency to be difficult to lock.

In order to address the above problem, the invention provides a kind of clock conversion and locking means, it is characterized in that: it is that the clock A of square wave and waveform are sinusoidal wave clock B that waveform is provided; Frequency values by described two kinds of clocks calculates the common divisor frequency as the pact frequency of described two kinds of clock conversion; Described clock A obtains the pact reference clock frequency of described clock A by counting frequency division mode by described pact frequency; Frequency by described pact reference clock frequency carries out to described clock B the sample frequency that the A/D sampling obtains described clock B as parameter; By described pact reference clock frequency and described sample frequency as the parameter designing phase-locked loop; The frequency control terminal of the described clock B of the output frequency of described phase-locked loop access is namely completed the closed loop work of whole system, realized that described clock A is to locking and the conversion of described clock B.

Described pact frequency adopts the greatest common divisor frequency of the frequency of described two kinds of clocks.The loop filtering of described phase-locked loop adopts the bandwidth varying scheme, and closed loop transits to low bandwidth parameter from high bandwidth parameter, satisfies simultaneously frequency difference and catches and the precision tracking requirement.

In order to address the above problem, the present invention also provides a kind of clock conversion and lock-in circuit, comprise: waveform is that clock A generation module, the waveform of square wave is sinusoidal wave clock B generation module, pact frequency generation module, pact reference clock frequency generation module, AD sampling module, phase-locked loop module, it is characterized in that: clock A and clock B input described pact frequency generation module, generate the pact frequency of described two kinds of clock conversion; Input again by described pact frequency and described clock A the pact reference clock frequency that pact reference clock frequency generation module obtains described clock A; Input the A/D sampling module by the frequency values of described pact reference clock frequency and the frequency values of described clock B as parameter, obtain the sample frequency of described clock B; Input phase-locked loop module by described pact reference clock frequency and described sample frequency as parameter, obtain the required output clock frequency of synchronizeing with described clock A; The frequency control terminal of the described clock B of described output clock frequency access is namely completed the closed loop work of whole system, realizes that described clock A is to locking and the conversion of described clock B.

Obtain described pact frequency by described clock A and two kinds of frequency values of described clock B as the described pact frequency generation module of parameter input, by the program realization of division algorithm.

State pact reference clock frequency generation module and obtained by counting frequency division mode as parameter with the pact frequency by described clock A, counting is realized based on FPGA.

Described phase-locked loop module comprises a phase discriminator, a loop filter and a voltage controlled oscillator; Input described phase discriminator by described pact reference clock frequency and described sample frequency as parameter, obtain the Voltage-output signal; Described Voltage-output signal input loop filter, the control voltage of the described voltage controlled oscillator of generation is implemented to control to the output signal frequency of described voltage controlled oscillator; The frequency control terminal of the described clock B of described output signal frequency access is namely completed the closed loop work of whole system, realizes that described clock A is to locking and the conversion of described clock B.

Described loop filter closed loop as required adopts the bandwidth varying scheme, and closed loop transits to low bandwidth parameter from high bandwidth parameter, satisfies simultaneously frequency difference and catches and the precision tracking requirement.

The invention has the advantages that, clock conversion and locking means and circuit thereof are provided, by calculating the common divisor of two kinds of clock frequencies, the locking of design pact reference clock frequency and closed loop, two kinds of clock frequencies that can realize particularly have locking freely and conversion between two kinds of clock frequencies of complex relationship.

Description of drawings

Fig. 1 is described is clock conversion and locking means flow chart, comprising: step S1: it is the clock A of square wave that waveform is provided; Step S2: it is sinusoidal wave clock B that waveform is provided; Step S3: the pact Frequency Design of clock A and clock B; Step S4: pact reference clock frequency produces; Step S5: the A/D sampling of clock B; Step S6: closed loop locking.

Fig. 2 is hardware circuit Organization Chart of the present invention, comprising: the sinusoidal wave filtration module M2 of clock A square wave Shaping Module M1, clock B, the pact reference clock frequency generation module M4 of pact Frequency Design module M3, clock A, AD sampling module M5, phase discriminator M6, loop filter M7 and the voltage controlled oscillator M8 of clock B.

Embodiment

Be described in further detail below in conjunction with the embodiment of accompanying drawing to clock conversion provided by the invention and locking means and circuit thereof.

The described clock conversion of Fig. 1 and locking means flow chart comprise: step S1: it is the clock A of square wave that waveform is provided; Step S2: it is sinusoidal wave clock B that waveform is provided; Step S3: the pact Frequency Design of clock A and clock B; Step S4: clock A pact reference clock frequency produces; Step S5: the A/D sampling of clock B; Step S6: closed loop locking and conversion.

Step S1: it is the clock A of square wave that waveform is provided, if clock A is not square wave, can adopt amplifier or diode to carry out the square wave shaping as the clock A of input clock, and it is shaped as dagital clock signal, to reduce the clock edge shake; If clock A is output as square-wave signal, can be directly as input signal.

Step S2: it is sinusoidal wave clock B that waveform is provided, if clock B output is not sinusoidal signal, and according to the operating frequency of clock B, the design simulation band pass filter, DC component and the high order harmonic component of filtering clock B obtain sinusoidal waveform; If clock B is output as sinusoidal signal, can be directly as input signal.

Step S3: the pact Frequency Design of clock A and clock B, clock A, two kinds of frequency values of clock B are carried out common divisor calculate; For convenient design, generally can choose the greatest common divisor frequency as the pact frequency of two kinds of clock conversion.

Step S4: clock A pact reference clock frequency produces, and take the pact frequency as parameter, clock A is counted frequency division, obtains the pact reference clock frequency of clock A; Counting can be realized based on FPGA or other digital device.

Step S5: the A/D of clock B sampling, take the pact reference clock frequency of clock A as parameter, by the AD device, clock B is carried out digital sample, obtain the sample frequency of clock B.

Step S6: closed loop locking and conversion are that parameter is carried out the phase bit comparison and obtained phase difference with the sample frequency of the pact reference clock frequency of clock A and clock B, and the phase signal that detects are converted to the Voltage-output signal; Described Voltage-output signal obtains output signal frequency is implemented the control voltage of control through loop filtering, controls output signal frequency; The frequency control terminal of output signal frequency incoming clock B is namely completed the closed loop locking work of whole system, realized that described clock A is to locking and the conversion of described clock B.

The loop bandwidth of loop filtering and loop type can require and clock stability requirement design according to phase noise.Under particular case, the loop bandwidth design can also improve the stability indicator of output signal.During the General System design, can adopt second-order loop, 10Hz is with interior bandwidth.Closed loop can adopt the bandwidth varying scheme as required, and closed loop can transit to lower bandwidth parameter from higher bandwidth parameter, satisfies simultaneously frequency difference and catches and the precision tracking requirement.

Fig. 2 is hardware circuit Organization Chart of the present invention, comprise the sinusoidal wave filtration module M2 of clock A square wave Shaping Module M1, clock B, the pact reference clock frequency generation module M4 of pact Frequency Design module M3, clock A, AD sampling module M5, the phase discriminator M6 of clock B, loop filter M7, voltage controlled oscillator M8.

The operation principle of described circuit is: obtain the square wave frequency of clock A after the shaping of clock A process square wave, clock B obtains the sinusoidal frequency of clock B through sinusoidal wave filtering; The frequency values of clock A and the frequency values of clock B are obtained the pact frequency as parameter by pact Frequency Design module; With the digital counting frequency divider of the square wave frequency input module M4 of clock A, obtain the pact reference clock frequency of clock A take the pact frequency as parameter after the counting frequency division; Take the pact frequency as parameter, the sinusoidal frequency AD sampling of clock B is obtained the sample frequency of clock B; With the pact reference clock frequency of clock A and the sample frequency input phase discriminator of clock B, phase discriminator detects the phase difference of two signals, and the phase signal that detects is converted to the Voltage-output signal; Voltage-output signal input loop filter, the control voltage of formation voltage controlled oscillator is implemented to control to the output signal frequency of voltage controlled oscillator; The frequency control terminal of the frequency incoming clock B of output signal is namely completed the closed loop locking work of whole system, realized that described clock A is to locking and the change-over circuit of described clock B.

The loop bandwidth of loop filter and loop type can require and clock stability requirement design according to phase noise.Under particular case, the loop bandwidth design can also improve the stability indicator of output signal.During the General System design, can adopt second-order loop, 10Hz is with interior bandwidth.Closed loop can adopt the bandwidth varying scheme as required, and closed loop can transit to lower bandwidth parameter from higher bandwidth parameter, satisfies simultaneously frequency difference and catches and the precision tracking requirement.

Wherein digital counting frequency divider, phase discriminator, loop filter, voltage controlled oscillators etc. can be by realizations such as a digital device such as FPGA, and remainder also can be integrated on a digital processing plate, realizes that the veneer of whole system is integrated.

The above is only the preferred embodiment of the present invention, by designing and produce the pact frequency of two kinds of clocks, and utilize digital sample and processing mode, both can realize that a kind of clock was to the locking control of another kind of clock, also can strengthen as required the special parameter of output signal, for the systems such as communication or navigation provide a kind of preferred version.

Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (6)

1. A kind of clock conversion and locking method is characterized in that: providing waveform is the clock A of square wave and the clock B of sine wave; By the frequency value of described two kinds of clocks, calculate common divisor frequency as described two kinds of clocks Transformed conventional frequency; the clock A obtains the conventional reference clock frequency of the clock A by counting frequency division according to the conventional frequency; the frequency of the conventional reference clock frequency is used as a parameter to perform A/D on the clock B Sampling to obtain the sampling frequency of the clock B; design a phase-locked loop with the reference clock frequency of the convention and the sampling frequency as parameters; connect the output frequency of the phase-locked loop to the frequency control terminal of the clock B to complete The closed-loop operation of the whole system realizes the locking and switching from the clock A to the clock B. 2 . The clock conversion and locking method according to claim 1 , wherein the conventional frequency adopts the frequency of the greatest common divisor of the frequencies of the two clocks. 3 . 3. A clock conversion and locking circuit, comprising: a clock A generating module whose waveform is a square wave, a clock B generating module whose waveform is a sine wave, a conventional frequency generating module, a conventional reference clock frequency generating module, an AD sampling module, and a phase-locked The ring module is characterized in that: clock A and clock B are input into the conventional frequency generation module to generate the conventional frequency transformed by the two clocks; the conventional frequency and the clock A are then input into the conventional reference clock frequency generation module to obtain The convention reference clock frequency of described clock A; By the frequency value of described convention reference clock frequency and the frequency value of described clock B as parameter input A/D sampling module, obtain the sampling frequency of described clock B; By described convention The reference clock frequency and the sampling frequency are input into the phase-locked loop module as parameters to obtain the required output clock frequency synchronized with the clock A; the output clock frequency is connected to the frequency control terminal of the clock B to complete the entire system The closed-loop operation realizes the locking and switching from the clock A to the clock B. 4. The clock conversion and locking circuit according to claim 3, characterized in that, two frequency values of the clock A and the clock B are input into the conventional frequency generation module as parameters to obtain the conventional frequency, and the conventional frequency is obtained by rolling Program implementation of division method. 5. The clock conversion and locking circuit according to claim 3, wherein the conventional reference clock frequency generation module is obtained by the clock A with the conventional frequency as a parameter through counting and frequency division, and the counting is realized based on FPGA. 6. clock conversion and locking circuit according to claim 4, is characterized in that, described phase-locked loop module comprises a phase detector, a loop filter and a voltage-controlled oscillator; By described convention reference clock frequency The sampling frequency is input into the phase detector as a parameter to obtain a voltage output signal; the voltage output signal is input into a loop filter to generate the control voltage of the voltage-controlled oscillator, and the output of the voltage-controlled oscillator is The signal frequency is controlled; the output signal frequency is connected to the frequency control terminal of the clock B to complete the closed-loop work of the entire system, and realize the locking and conversion from the clock A to the clock B. the

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