CN102426852A - Method and system for reading storage array unit information - Google Patents

Abstract

The invention provides a method and a system for reading information of a memory array unit, which simultaneously gate a plurality of continuous bit lines including the bit line of a read unit, apply a first reading voltage to one bit line of the read memory unit, apply a second reading voltage higher than the first reading voltage to the other bit line, apply a voltage equal to the second reading voltage to the continuous bit lines adjacent to the bit line to which the second reading voltage is applied to the read memory unit, and have no potential difference at two ends of a plurality of memory units adjacent to the bit line with higher voltage of the read memory unit, thereby avoiding the problem of current leakage caused by the adjacent memory units and improving the reading precision of the stored information of the memory units.

Description

Method and system for reading storage array unit information

technical field

The invention relates to the field of information storage, in particular to a storage array unit information reading method and system.

Background technique

The core of the entire memory is an array of memory cells. The method of reading the information of the memory cells in the array is shown in Figure 1. The memory cell is an ordinary MOS tube as an example. Each memory cell (cell) has three ports, one of which is a control port. It is equivalent to the gate of an ordinary MOS transistor, and the other two ports are equivalent to the source and drain of an ordinary MOS transistor. The control ports of the memory cells are connected to the word line, and the control ports of the memory cells in the same row of the array are connected to the same word line WL1. The sources and drains of memory cells in the same row in the memory array are connected end to end in sequence, and the sources and drains of two adjacent memory cells are connected to a bit line. When the memory cell is on, it is equivalent to a resistor; when the information stored in the memory cell is "0" or "1", its resistance value is different. Therefore, in order to read the information stored in the memory cell, it is necessary to apply a potential difference between the two ends of the memory cell to be read, and the stored information in the memory cell can be read by reading the current flowing through the memory cell.

When reading the information in the memory cell, the low-level generating circuit or the current reading circuit is connected to the bit line of the memory array through the bit line gating device, which is equivalent to an electrical switch and is controlled by the bit line gating device. The signal controls the bit line gating device to gate the bit lines in the memory array, so that the selected bit lines are connected to the low level generating circuit or the current reading circuit. Take the reading of the memory cell cell2 in Figure 1 as an example. After the word line WL1 level is high, the memory cell cell2 is turned on. The conventional memory array information reading method is to select the two bits connected to the source and drain of the memory cell cell2. Lines BLa and BLa+1, so that the bit lines BLa and BLa+1 are respectively connected to the low-level generating circuit and the current reading circuit, and the reading low voltage and the reading high voltage are respectively applied to the bit lines BLa and BLa+1, and the memory cell The potential difference between the two ends of cell2 causes a current Ibit flowing through the memory cell, and the value of the current flowing through the memory cell cell2 is denoted as Ibit. The read current I is read by the current read circuit, and the read current value read by the read circuit is denoted as I. When I=Ibit, the read current value reflects the information stored in the storage unit.

However, when reading the information in the memory cell cell2, the read low voltage and the read high voltage are applied to the bit lines BLa and BLa+1 respectively, and the bit line BLa+2 adjacent to the bit line BLa+1, There is no voltage applied on the BLa+3 equipotential line. At the moment when the low-level generating circuit and the current reading circuit work, a potential difference is generated at both ends of the source and drain of the memory cells cell3, cell4, etc., which will be generated in the memory cells cell3, cell4, etc. A leakage current Ileak is generated on cell4 and the like, and the leakage current value is denoted as Ileak. The value of the current I read by the current reading circuit is I=Ibit+Ileak, wherein only Ibit is a reflection of the information stored in the storage unit cell2, so the leakage current makes the reading current I unable to accurately reflect the storage information of the cell2 , which may lead to information reading errors, making the reading accuracy of the memory not high.

Contents of the invention

The invention solves the problem that the accuracy of the existing storage array unit information reading method is not high.

In order to solve the above problems, the present invention provides a method for reading storage array unit information, including:

gating the word line of the memory cell to be read; gating a plurality of consecutive bit lines of the memory array, wherein

Applying a first read voltage and a second read voltage to the two bit lines of the read memory cell respectively, the second read voltage is higher than the first read voltage; and applying the second read voltage Applying a voltage equal to the second read voltage to a plurality of consecutive bit lines adjacent to the bit line of the voltage;

comparing the current generated on the read memory unit with the preset current value to determine the storage information of the read memory unit.

Correspondingly, the present invention also provides a memory array unit information reading system, including a memory cell array, a low level generating circuit, a current reading circuit, a bit line gating device and a word line gating device, and also includes a plurality of voltage follow the circuit,

The voltage following circuit and the current reading circuit provide the same voltage, which is higher than the voltage generated by the low level generating circuit; the low level generating circuit, the current reading circuit and the voltage following circuit work synchronously;

The word line gating device gating the word line of the memory cell to be read; the bit line gating device simultaneously gating multiple consecutive bit lines of the memory array according to the bit line gating control signal;

The low level generation circuit is connected to one bit line of the memory array unit to be read through the bit line gating device; the current reading circuit is connected to another bit line of the memory array unit to be read through the bit line gating device Bit line connection; the input terminals of multiple voltage follower circuits are connected to the voltage output terminals of the current reading circuit, and the output terminals of each voltage follower circuit are respectively connected to the current reading circuit of the memory unit to be read through the bit line gating device A plurality of consecutive bit lines adjacent to the bit line are connected.

Compared with the prior art, the present invention has the following advantages:

The present invention provides a method for reading information of a memory array unit. The technical solution adopted is to simultaneously gate multiple consecutive bit lines including the bit line of the unit to be read, wherein, in the memory unit to be read One bit line applies a first read voltage, and the other bit line applies a second read voltage higher than the first read voltage; adjacent to the bit line to which the read memory cell applies the second read voltage Applying a voltage equal to the second read voltage to a plurality of consecutive bit lines; comparing the read current generated on the read memory cell with a preset current value to determine the storage information of the read memory cell. Compared with the conventional reading scheme, the same second read voltage is applied to a plurality of consecutive bit lines adjacent to the bit line to which the second read voltage is applied to the read memory cell, and the same second read voltage is applied to the read memory cell. There is no potential difference between the two ends of the adjacent memory cells, which avoids the problem of leakage current generated by the adjacent memory cells, and improves the reading accuracy of the stored information of the memory cells.

Description of drawings

The above and other objects, features and advantages of the present invention will be more clearly illustrated by the accompanying drawings. Like reference numerals designate like parts throughout the drawings. The drawings are not intentionally scaled according to the actual size, and the emphasis is on illustrating the gist of the present invention.

FIG. 1 is a schematic diagram of reading a storage unit by an existing storage array unit information reading method;

2 is a schematic diagram of reading a storage unit by the storage array unit information reading method of the present invention;

3 is a schematic diagram of a low-level generating circuit of a storage array unit information reading method of the present invention;

4 is a schematic diagram of a current reading circuit of a method for reading information of a storage array unit according to the present invention;

5 is a schematic diagram of the voltage clamping unit of the current reading circuit of the storage array unit information reading method of the present invention;

FIG. 6 is a schematic diagram of a voltage follower circuit of a method for reading memory array unit information according to the present invention;

FIG. 7 is a schematic diagram of the connection of the bit line gating device of the method for reading the information of the memory array unit according to the present invention;

8 is a schematic diagram of the application of the storage array unit information reading method of the present invention to the entire storage array;

FIG. 9 is a schematic diagram of a storage array unit information reading system according to the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, many specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways than those described here, so the present invention is not limited by the specific embodiments disclosed below.

Secondly, the present invention is described in detail with reference to the schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention.

As described in the background, the conventional method for reading information in a memory array is to apply a low voltage for reading on one bit line of the memory cell to be read, and apply a high voltage for reading on the other bit line, and apply the high voltage to the other bit line. No signal is applied to other bit lines adjacent to the bit line. At the moment when a high voltage is applied to the bit line of the memory cell to be read, the multiple bit lines adjacent to the bit line connected to the high voltage signal do not apply any signal. There is a potential difference between the two ends of the connected memory cells, and the word lines of the memory cells in the same row as the read cell are gated, and the memory cells whose word lines are gated are equivalent to a resistor, which will generate a leakage current on these memory cells , so that the current read by the current reading circuit is the sum of the current flowing through the memory cell to be read and the leakage current of other adjacent memory cells. However, only the current flowing through the memory cell to be read is a reflection of the information stored in the memory cell to be read, and the leakage current generated on other memory cells adjacent to the memory cell to be read may lead to The memory information of the unit was read incorrectly. Therefore, the existing storage array information reading method makes the reading accuracy of storage array units not high.

In order to improve the reading accuracy of the storage array unit information reading method, the present invention proposes a new storage array unit information reading method. For the bit line, apply equal voltages to consecutive multiple bit lines adjacent to the bit line that is applied with a higher voltage to the memory cell to be read, to eliminate the generation of leakage current on the memory cell adjacent to the memory cell to be read, and to improve the The reading precision of the storage array unit information reading method. The reading process of the present invention will be described in detail below through specific embodiments.

Referring to Fig. 2, this embodiment proposes a method for reading information of memory array cells, using two voltage follower circuits to provide a voltage equal to the bit line to which a higher voltage is applied to the memory cell to be read. In this embodiment, the word line gate The control signal strobes the word line WL of the read memory cell Celln+1 through the word line strobe device, and the bit line strobe control signal strobes four consecutive bit lines BLn, BLn+ of the memory array simultaneously through the bit line strobe device 1. BLn+2 and BLn+3, make the bit line BLn apply a low first read voltage, the first read voltage is generated by a low level generating circuit, the bit line BLn+1 applies a second read voltage, the second The read voltage is higher than the first read voltage, which is generated by the current read circuit, and the bit lines BLn+2 and BLn+3 are applied with a voltage following the voltage generated by the circuit. The information stored in the storage unit Celln+1 can be obtained by reading the current on the storage unit Celln+1 and comparing it with a preset reference current value. The function of the voltage follower circuit is to follow the voltage of the end to which the second read voltage is applied to the memory cell to be read, and make the voltage of the bit line connected to it reach the same voltage value as the second read voltage. When reading the memory cell Celln+1, the voltages at both ends of the memory cells Celln+2 and Celln+3 are equal, so no leakage current will be generated and the read current generated on the memory cell Celln+1 will not be affected. Therefore, the method for reading memory array unit information in this embodiment can ensure the reading accuracy of the storage unit Celln+1.

In the method of this embodiment, only 4 consecutive bit lines of the memory array are selected, and more consecutive bit lines can be selected, wherein the first bit line generated by the low level generation circuit is applied to a bit line of the read memory cell. One read voltage, the other bit line applies the second read voltage generated by the current reading circuit; a plurality of consecutive bit lines adjacent to the bit line to which the second read voltage is applied to the read memory cell simultaneously apply voltages to follow The voltage provided by the circuit is equal to the second read voltage.

The first read voltage in this embodiment is generated by a low-level generating circuit. The basic structure of the low-level generating circuit can be a MOS transistor. See Figure 3 for the circuit connection mode. The source 1 of the MOS transistor is grounded, and the drain 2 passes through the bit The line gating device is connected to the bit line, and the gate 3 is connected to the control terminal. When the control terminal is turned on, the MOS transistor is turned on, and the bit line connected to the drain 2 through the bit line gating device is set to a low level; when the control terminal is turned off, the MOS transistor is turned off, and the drain 2 is passed through the bit line gating device The connected bit line is floating.

The second reading voltage of the present embodiment is produced by the current reading circuit, and the current reading circuit can be a sense amplifier or a pseudo sense amplifier, referring to Fig. 4, its basic structure includes two PMOS current mirrors 4 connected to the analog power supply VDDA , a current judgment unit and a voltage clamping unit, wherein a mirror branch of the current mirror 4 composed of PMOS transistors is connected to the voltage clamping unit and applies a high voltage to a bit line of the read memory unit 5 through the bit line gating device At the same time, the bit line potential of the read memory cell 5 is fixed at the set voltage value Vdp by the voltage clamp unit, and another bit line of the read memory cell 5 applies a level generating circuit ( Not shown in the figure) produces a low voltage, the other mirror branch of the current mirror 4 is connected to one end of the current source A through the sensing point C, the other end of the current source is grounded, and the decision unit is connected to the sensing point C superior.

The decision unit of the current reading circuit in this embodiment can use an inverter, the input end of the inverter is connected to the sensing point C of the current reading circuit, and the output end of the inverter outputs the reading current I The mirror image reads the comparison result between the current Im and the preset reference current value provided by the current source A, and the comparison result reflects the information stored in the storage unit Celln+1.

The voltage clamping unit of the current reading circuit of this embodiment may include an inverter and an NMOS transistor, see FIG. 5, wherein the source 12 of the NMOS transistor is the input terminal of the voltage clamping unit, and the drain 13 is the voltage The output terminal of the clamp unit is also the voltage output terminal of the current reading circuit, the drain 13 is connected to the input terminal of the inverter 10, and the output terminal of the inverter 10 is connected to the gate 11 of the NMOS transistor.

The basic structure of the voltage follower circuit can include an operational amplifier, as shown in Figure 6, the output terminal 22 of the operational amplifier is connected to the inverting input terminal 21, so that the voltage of the output terminal 22 of the amplifier is consistent with the voltage of the non-inverting input terminal 20 . The input terminal 20 of the operational amplifier is the input terminal of the voltage follower circuit, which is connected to the voltage output terminal of the current reading circuit, and the voltage output by the output terminal 22 of the operational amplifier is applied to the bit line through the bit line gating device. As shown in Figure 2, during the read operation, the voltage follower circuit can charge the connected bit lines BLn+2 and BLn+3 synchronously with the bit line BLn+1, so that the voltage of the bit lines BLn+2 and BLn+3 The voltage is equal to the bit line BLn+1.

In addition, the voltage follower circuit in this embodiment may also include a control terminal. Referring to FIG. 6, the voltage follower circuit operates when the control terminal 23 is at a high level, and the output terminal 22 outputs a voltage equal to the non-inverting input terminal 20; the control terminal 23 is at a low level. level, the voltage follower circuit is closed and does not work, and the output voltage of the output terminal 22 is zero.

In the method for reading memory array unit information in this embodiment, the multiple continuous bit lines of the memory array are selected by the bit line gating device according to the gating control signal. The bit line gating device is the storage array unit information of this embodiment. An important part of the reading method, the bit line gating device is a circuit device that controls the connection relationship between the bit line and other readout circuits (such as current reading circuits). The control signal is controlled, which is equivalent to an electrical switch. The most basic unit of the bit line gating device is a MOS transistor. The source and drain of the MOS transistor are respectively connected to the bit line and the readout circuit, and the gate is connected to the bit line gating control signal.

In an actual memory array unit information reading system, the bit line gating device has various structures, and the bit line gating device in this embodiment may adopt a gating structure in which one gating control signal is used to gate one bit line. Referring to the schematic diagram of the connection of the gating device when the storage array unit information is read in FIG. The bit line BLn of the array is connected to the low level generating circuit through the MOS transistor M1; the bit line gating control signal S2 selects the MOS transistor M2, and the bit line BLn+1 of the memory array is connected to the current reading circuit through the MOS transistor M2; The line strobe control signal S3 strobes the MOS transistor M3, and the bit line BLn+2 of the memory array is connected to the voltage follower circuit through the MOS transistor M3; the bit line strobe control signal S4 strobes the MOS transistor M4, and the bit line BLn+2 of the memory array 3 is connected with the voltage follower circuit through the MOS transistor M4.

The method of this embodiment is applied to the entire memory array as shown in FIG. 8. For a memory array composed of a plurality of memory cells, the word line WLn controls the on and off of the memory cells in the nth row, and the word line WLm controls the memory cells in the mth row. On and off, the strobe control signal generated by the pre-decoding circuit strobes the continuous four MOS transistors made by the bit line strobe, so that the four consecutive bit lines in the memory array are turned on with the other end of the strobe device. Four consecutive bit lines can be located anywhere in the memory array, such as bit lines BLn, BLn+1, BLn+2, and BLn+3 are gated, or bit lines BLm, BLm+1, BLm+2, and BLm+3 The gating device makes the four consecutive bit lines apply the voltages generated by the low level generating circuit, the current reading circuit and the two voltage follower circuits respectively.

The present invention also provides a memory array information reading system, as shown in FIG. 9, which includes a memory cell array, a low-level generating circuit, a current reading circuit, a bit line gating device, a word line gating device, and a plurality of voltage follower circuit, where

The low-level generating circuit, the current reading circuit and a plurality of dummy voltage supply circuits are connected to a plurality of continuous bit lines of the memory array through the bit line gating device;

The bit line gating device is connected to the bit line of the storage array; the word line gating device is connected to the word line of the storage array;

The voltage provided by the voltage following circuit and the current reading circuit are the same, higher than the voltage provided by the low level generating circuit; the low level generating circuit, the current reading circuit and the voltage following circuit work synchronously;

The low level generating circuit is connected to a bit line of the memory array unit to be read through the bit line gating device; the current reading circuit is connected to another bit line of the memory array unit to be read through the bit line gating device; The input terminals of multiple voltage follower circuits are connected to the voltage output terminals of the current reading circuit, and the output terminals of each voltage follower circuit are respectively adjacent to the bit lines connected to the current reading circuit of the memory cell to be read through the bit line gating device consecutive multiple bit line connections.

The structure of the bit line gating device may include a plurality of MOS transistors, the gate of a MOS transistor is only connected to one bit line gating control signal, the source is only connected to one bit line, and the drain is connected to a low level generating circuit, Voltage follower circuit or current read circuit.

The current reading circuit can be a sense amplifier or a pseudo sense amplifier, and its basic structure includes a PMOS current mirror connected to the analog power supply VDDA, a current judgment unit and a voltage clamp unit, wherein a mirror image branch of the current mirror composed of a PMOS transistor After connecting the voltage clamping unit, connect the bit line of the memory cell to be read through the bit line gating device, and at the same time, the potential of a bit line of the memory cell to be read is fixed at the set voltage value Vdp by the voltage clamping unit; the current mirror The other mirror branch is connected to one end of the current source through the sensing point, the other end of the current source is grounded, and the decision unit is connected to the sensing point. Wherein, the decision unit can use an inverter, the input terminal of the inverter is connected to the sensing point of the current reading circuit, and the output terminal of the inverter outputs the mirror image reading current and the preset value provided by the current source A. The comparison result of the reference current value; the voltage clamping unit may include an inverter and an NMOS transistor, the source of the NMOS transistor is the input terminal of the voltage clamping unit, the drain is the output terminal of the voltage clamping unit, and the drain terminal and the inverting The input terminal of the inverter is connected, and the output terminal of the inverter is connected with the gate of the NMOS transistor.

The basic structure of the voltage follower circuit can include an operational amplifier, the output of the operational amplifier is connected to the inverting input terminal, the input terminal of the operational amplifier is connected to the voltage output terminal of the current reading circuit, and the output terminal of the operational amplifier is gated through the bit line devices are connected on bit lines. The voltage follower circuit may also include a control terminal. When the control terminal is at a high level, the voltage follower circuit works, and when the control terminal is at a low level, the voltage follower circuit is turned off and does not work.

When performing a memory array unit information read operation, the word line gating control signal is gated through the word line gating device to gating the word line of the memory cell to be read, and the bit line gating control signal is gating through the bit line gating device to be read A plurality of consecutive bit lines of the memory cell, wherein the low level generation circuit is connected to one bit line of the memory array unit to be read through the bit line gating device; the current reading circuit is connected to the read bit line through the bit line gating device The other bit line of the memory array unit is connected; multiple voltage follower circuits are respectively connected to a plurality of continuous bit lines adjacent to the bit line connected to the current reading circuit of the read memory unit through the bit line gating device. The low level generating circuit, the current reading circuit and the voltage follower circuit charge the respectively connected bit line synchronously, and the current reading circuit reads the current of the read memory unit to determine the information stored in the read memory unit.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (11)

1. a cells of memory arrays information-reading method is characterized in that, comprising:

Gating is read the word line of storage unit; Many continuous bit lines of gating storage array, wherein

Apply first respectively at said two bit lines that are read storage unit and read voltage and second reading power taking pressure, said second reading power taking pressure is higher than first and reads voltage; Apply the voltage that equates with said second reading power taking pressure simultaneously with the adjacent continuous many bit lines of bit line that apply said second reading power taking pressure;

Relatively be read the electric current and the predetermined current value that produce on the storage unit and confirm the said canned data that is read storage unit.

2. cells of memory arrays information-reading method according to claim 1 is characterized in that, said applying simultaneously with said second reading power taking with the adjacent continuous many bit lines of bit line that apply said second reading power taking pressure presses the voltage that equates to be:

The in-phase input end of operational amplifier is imported said second reading power taking and is pressed; Through being that the bit line that is connected the output terminal of operational amplifier applies the voltage that equates with said second reading power taking pressure after the operational amplifier computing, the inverting input of said operational amplifier is connected output terminal.

3. cells of memory arrays information-reading method according to claim 1 and 2 is characterized in that, many continuous bit lines of said gating storage array are:

A plurality of gating control signals are controlled a plurality of MOS transistor conductings; Wherein, The source electrode and drain electrode conducting of a MOS transistor of a gating control signal control make the bit line of the source electrode that is connected a MOS transistor apply said low-voltage, high voltage or the pseudo-voltage that is connected drain electrode.

4. cells of memory arrays information-reading method according to claim 1 and 2 is characterized in that, saidly applies first at a said bit line that is read storage unit and reads voltage and be:

The source electrode of the MOS transistor of control source ground is that said bit line applies first and reads voltage with the drain electrode conducting.

5. cells of memory arrays information-reading method according to claim 1 and 2 is characterized in that, saidly applies the second reading power taking at a said bit line that is read storage unit and presses and to be:

Supply voltage is that said second reading power taking is pressed through comprising behind of 2 transistorized current mirrors of PMOS by the voltage clamp circuit clamper, and said second reading power taking pressed is applied to a said bit line that is read storage unit.

6. cells of memory arrays information-reading method according to claim 5 is characterized in that, the said electric current and the predetermined current value that produce on the storage unit of relatively being read confirms that the said canned data that is read storage unit is:

Read in and be read the electric current that reads that storage unit applies bit line that the second reading power taking presses, comprising:

Be read the electric current that produces on the storage unit another generation image current at said current mirror;

Said image current and said predetermined current value compare, and obtain the said canned data that is read storage unit through the decision circuit judgement that comprises phase inverter.

7. cells of memory arrays information-reading method according to claim 1 and 2 is characterized in that, applies adjacent continuous two bit lines of bit line that the second reading power taking presses and applies with said second reading power taking and press the voltage that equates with the said storage unit that is read.

8. a cells of memory arrays information reading system comprises that memory cell array, low level produce circuit, electric current reads circuit, bit line strobe unit and word line strobe unit, it is characterized in that, also comprises a plurality of voltage follower circuits,

Said voltage follower circuit reads circuit with said electric current identical voltage is provided, and is higher than said low level and produces the voltage that circuit produces; Said low level generation circuit, electric current read circuit synchronouss working with voltage follower circuit;

Said word line strobe unit gating is read the word line of storage unit; Said bit line strobe unit is according to many continuous bit lines of the said storage array of bit line gating control signal while gating;

Said low level produces circuit and is connected with a bit line that is read cells of memory arrays through the bit line strobe unit; Said electric current reads circuit and is connected with another root bit line that is read cells of memory arrays through the bit line strobe unit; The input termination electric current of a plurality of voltage follower circuits reads the voltage output end of circuit, and the output terminal of each voltage follower circuit reads the adjacent continuous many bit lines of the bit line of circuit and connects with the electric current that is connected that is read storage unit respectively through the bit line strobe unit.

9. cells of memory arrays information reading system according to claim 8 is characterized in that said voltage follower circuit comprises an operational amplifier,

The in-phase input end of said operational amplifier connects the voltage output end that electric current reads circuit, and the output terminal of operational amplifier is connected on the bit line through the bit line strobe unit; The output terminal of said operational amplifier is connected with inverting input.

10. cells of memory arrays information reading system according to claim 9 is characterized in that said operational amplifier comprises control end,

When said control end was high level, the output end voltage of said operational amplifier equated with in-phase input end voltage;

When control end was low level, the output terminal of said operational amplifier was floating empty.

11. described according to Claim 8-10 cells of memory arrays information reading system; It is characterized in that; Said bit line strobe unit comprises a plurality of MOS transistors; A said bit line gating control signal connects the grid of a said MOS transistor, and a said bit line connects the source electrode of a said MOS transistor, and low level produces circuit, voltage follower circuit or electric current and reads the drain electrode that circuit connects said MOS transistor.

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