CN102422537A - Gate driver for enhancement mode and depletion mode wide bandgap semiconductor JFETs - Google Patents

Abstract

A DC-coupled bipolar gate driver circuit for driving a Junction Field Effect Transistor (JFET) is provided. The JFET may be a wide band gap Junction Field Effect Transistor (JFET), such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit, and a pull-down circuit. The driver is configured to receive an input Pulse Width Modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.

Description

Gate Drivers for Enhancement-Mode and Depletion-Mode Wide Bandgap Semiconductor JFETs

This application claims priority to US Provisional Patent Application No. 61/177,014, filed May 11, 2009, which is hereby incorporated by reference in its entirety.

technical field

The present invention relates generally to gate drivers and integrated circuits including gate drivers, and more particularly to n-channel JFET-based gate drivers for enhancement-mode and depletion-mode wide bandgap semiconductor junction field effect transistors (JFETs).

Background technique

One application of wide bandgap junction field effect transistors (JFETs) is in high voltage, high frequency power electronics. The special device characteristics of wide bandgap JFETs enable these devices to replace high-voltage insulated-gate bipolar transistors (IGBTs) in many applications. Switching energy loss is one of the main characteristics of power semiconductor switches to compare when selecting devices for new designs. The transition speed is ultimately limited by the device. However, the performance of the gate driver can significantly affect this speed.

The main function of the gate driver is to transfer/remove the necessary gate charge needed by the device's internal gate-source and Miller capacitances to transition the device between states. The faster the gate driver can perform this task, the faster the device transitions from off-state to on-state and from on-state to off-state. Therefore, it is important to use a properly designed gate driver in order to obtain the maximum performance of the device in practical system applications.

The gate structure of a JFET presents two distinct requirements to drive the device into a conducting state. These requirements are similar to the combination of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Bipolar Junction Transistors (BJTs). First, similar to MOSFETs, high peak instantaneous currents are recommended for fast charging of the gate capacitance. Second, similar to BJTs, a small DC gate current is required to maintain conduction.

For wide bandgap JFETs, an AC-coupled, BJT-like RC driver can be used in most applications. A driver of this type is depicted in FIG. 1 . This driver scheme has been shown to provide exceptional switching performance, but suffers from duty cycle and switching frequency limitations. An RC driver consists of a parallel resistor and bypass capacitor connected between the gate/base of a semiconductor switch and the output of a pulse width modulation (PWM) IC or other pulse generating circuit.

RC drivers are capable of level shifting, setting the DC current limit, and providing the high peak currents required by most power semiconductors for fast turn-on. In order to continuously maintain the maximum switching speed, the bypass capacitors of the RC driver must be fully discharged before the next switching event. The time to discharge depends on the RC time constant of the RC driver. Therefore, the maximum switching frequency and duty cycle of the application is limited by the RC time constant of the RC driver.

Therefore, there remains a need for improved gate drivers for wide bandgap JFETs, and particularly for active, DC-coupled drivers that can overcome the limitations of RC drivers.

Contents of the invention

A dual-stage gate driver circuit for driving a junction field effect transistor (JFET) having a gate, a source, and a drain is provided, the dual-stage gate driver circuit comprising:

an input terminal, the input terminal is used to provide a control pulse signal V _in ;

three resistors _R1 , _R2 and _R3 each having a first terminal and a second terminal electrically coupled to the gate of the JFET through the second terminal;

a first conduction circuit electrically coupled between the input terminal and the first terminal of resistor _R2 ;

a second conduction circuit electrically coupled between the input terminal and the first terminal of resistor _R1 ; and

A pull-down circuit electrically coupled between the input and the first terminal of resistor _R3 .

Also provided is a dual-stage gate driver circuit for driving a junction field effect transistor (JFET) having a gate, a source, and a drain, the dual-stage gate driver circuit comprising:

an input terminal, the input terminal is used to provide a control pulse signal V _in ;

a first conduction circuit;

a second conduction circuit; and

pull-down circuit,

Wherein, the first conduction circuit, the second conduction circuit and the pull-down circuit are electrically coupled in parallel between the input terminal and the gate of the JFET.

These and other features of the present teachings are set forth herein.

Description of drawings

The drawings illustrate one or more embodiments of the invention and together with the description serve to explain principles of the invention. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like elements of the embodiments.

Figure 1 is a circuit diagram of an AC-coupled RC gate driver.

Figure 2 is a schematic diagram of a VJFET modeled as a capacitor in parallel with a pn diode.

Figure 3 is a circuit diagram of a DC-coupled dual-stage gate driver for a wide bandgap JFET.

4 is a circuit diagram of a DC-coupled dual-stage gate driver for a wide bandgap JFET with feedback to a pulse generator circuit.

5 is a circuit diagram of a DC-coupled dual-stage gate driver for a wide bandgap JFET according to another embodiment.

6 is a circuit diagram of a DC-coupled dual-stage gate driver for a wide bandgap JFET with feedback to a pulse generator circuit according to another embodiment.

FIG. 7 is a circuit diagram showing a part of the gate driver in operation during a period t1.

FIG. 8 is a circuit diagram showing a part of the gate driver in operation during a period t2.

FIG. 9 is a circuit diagram showing a part of the gate driver in operation during a period t3.

10A to 10F show operating waveforms for a dual-stage JFET gate driver.

Figure 11A is a circuit diagram of a dual driver IC for driving enhancement mode (EM) SiC JFETs.

FIG. 11B are waveforms for the device of FIG. 11A.

FIG. 12A is a circuit diagram of a switching energy test circuit for a single device test.

12B is a circuit diagram of a switching energy test circuit for bridge configuration testing.

FIG. 13 shows operating waveforms for AC coupled drive in the single switch test circuit of FIG. 12A.

14A and 14B show switching energy measurements for a SiC JFET (SJEP120R125) tested in full phase pins using the test circuit of FIG. 12B.

15A and 15B are graphs showing switching energy versus load current for two SiC JFETs (SJEP120R125 and SJEP120R063) at junction temperatures of 25°C and 150°C.

16A is a schematic diagram of an embodiment using a dual driver circuit for driving enhancement mode (EM) SiC JFETs.

Figures 16B-16E illustrate experimental results for the embodiment depicted in Figure 16A.

17A is a schematic diagram of an embodiment using an IC driver and a transistor driver for driving an enhancement mode (EM) SiC JFET.

Figures 17B to 17E show experimental results for the embodiment depicted in Figure 17A.

18A is a schematic diagram of an alternative embodiment using IC drivers and transistor drivers for driving enhancement mode (EM) SiC JFETs.

Figures 18B-18C show experimental results for the embodiment depicted in Figure 18A.

Detailed ways

Various embodiments of the invention are now described in detail. Referring to the drawings, like numerals indicate like components throughout the views. As used in the specification herein and throughout the claims that follow, the singular forms "a" and "the" include plural referents unless the context clearly dictates otherwise. Additionally, as used in this specification and throughout the claims that follow, the meaning of "in" includes "in" and "on", unless the context clearly dictates otherwise.

Embodiments of the present invention are described in conjunction with the accompanying drawings.

The transition speed of a JFET is ultimately limited by the device. However, the performance of the gate driver can significantly affect this speed. As stated above, the gate driver must meet two main requirements: the transfer/removal of dynamic gate charge; and the sustainability of the DC gate voltage and the resulting gate-source current during conduction. The ability of the gate driver to quickly transfer/remove the necessary gate charge required by the device's internal gate-source and Miller capacitances is a major factor affecting the time it takes for the device to transition between states. The gate driver should also be designed to efficiently maintain the steady-state DC gate voltage and gate current required for minimum R _DS(ON) during conduction.

Using a simple RC network, an AC (capacitor) coupled gate driver circuit connects the gate of the JFET to the output of a standard COTS MOSFET/IGBT gate driver IC to allow insertion of a MOSFET or IGBT with a normally-off SiC JFET in the application replace. Although AC-coupled drivers have proven to be an effective way to drive enhancement-mode (EM) SiC JFETs, they suffer from duty cycle and switching frequency limitations.

Figure 1 provides a schematic diagram of an AC coupled drive. This particular gate driver _uses a current limiting resistor, R _CL , to set the " The DC operating point in the “on” state. Bypass capacitors are used to quickly transfer/remove dynamic gate charge for fast turn-on and turn-off. In a sense, the capacitor behaves as overdriving the gate of the JFET, which is seen by the overshoot of the gate-source voltage tested at the terminals. Overdriving the gate for a duration of <200ns with a maximum driver IC voltage of +15V connected to the gate through a low resistance resistor is acceptable and recommended for fast turn-on. As the device transitions between blocking and conducting states, the high peak current from the gate drive is handing over the charge required by the input capacitance and not flowing through the gate-source diode. When the input capacitor is fully charged, the steady-state condition is regulated by the current-limiting resistor. An additional low resistance resistor (typically 1-5 ohms) may be included in series with the bypass capacitor to suppress any observed gate ringing.

Drivers of this type can be used with unipolar or bipolar drive voltages. If used with a unipolar drive voltage, the bypass capacitor will provide some negative gate bias at turnoff to help reduce turnoff time and provide some degree of noise immunity for a limited duration. Since MOSFETs and IGBTs are usually connected to the driver IC through a gate resistor, a simple change of resistor value and addition of bypass capacitors are all that is required to convert standard MOSFET/IGBT drive to SiC JFET drive in most power switch configurations.

Select the appropriate value of C _BP based on the Q _g of the SiC JFET and its independent PWM/driver IC supply rail voltage. Parasitic circuit effects can affect the choice of C _BP , so a specific value of C _BP may not be suitable for all applications. Instead, _the user is suggested as a starting point an empirically estimated range of C _BP values bounded by the following expression:

$\frac{\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}}}<span\; class="notranslate">\; \&le;</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; BP</span>}}<span\; class="notranslate">\; \&le;</span>\frac{\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; *</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; DD</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GS</span>}}}$

The RCL is used to limit the continuous current flowing from the PWM/driver IC through the gate-source diode of the SiC JFET, thus setting the gate-source voltage. To avoid overdriving the gate of the JFET during steady-state conduction, a positive gate-source bias of no more than +3.0V is recommended. The selection of the R _CL requires the following information:

a. V _O = positive output voltage of PWM/driver IC

b. V _GS = desired JFET gate-source voltage

c. I _GFWD = gate-source diode current at desired gate-source voltage. I _GFWD can be estimated from graph X of the data sheet.

Then use the following expression to calculate R _CL :

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; CL</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; GFWD</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; Vgs</span>}<span\; class="notranslate">\; )</span>}}$

To consistently achieve the fastest possible switching performance, the bypass capacitors of the RC network must be fully discharged before the next switching event. The size of this capacitor depends on the application and the specification of the driver IC. Any particular value may require more time to discharge than is available for the particular combination of switching frequency and duty cycle. Although not fully discharging the capacitor does not cause any operational problems, it will result in a slower turn-on transition due to the smaller voltage difference between the output of the driver IC and the capacitor voltage at the next turn-on event. Therefore, an additional DC-coupled gate driver design that can operate over a wider range of switching frequencies and duty cycles is necessary.

The gate-source and gate-drain structure of this JFET device can be modeled as a capacitor in parallel with a pn diode as shown in Figure 2. The equivalent model of this device is unique and represents some characteristics of MOSFET and some characteristics of BJT. Power JFETs place two main requirements on the gate driver: fast transfer/removal of dynamic charge to charge/discharge the total gate capacitance; internal sustainability.

High frequency applications require drivers that do not depend on the RC time constant for optimum performance. Dual-stage, DC-coupled driver designs have been developed specifically for JFETs. Figure 3 shows a two-stage, DC-coupled driver according to one embodiment. 4, 5 and 6 depict other embodiments of dual-stage gate drivers. The driver can apply high peak current pulses to provide the required dynamic charge as fast as possible for fast turn-on, and also maintain a steady state DC gate voltage/current to maintain conduction. This driver can be used to overdrive the gate during the turn-on instant. The developed dual-stage driver allows precise control of overdrive conditions as well as steady-state conditions.

The circuit shown in Figure 3 receives a single PWM control signal and generates a second pulse width modulated (PWM) signal that is synchronized with the original control signal. The generated pulses drive the first pass stage, which provides a high peak current source to rapidly charge the gate and Miller (or gate-drain) capacitance of the device. The pulse width of the second control pulse lasts until the Miller capacitance of the device is fully charged and the drain-source voltage has completely collapsed. The second control pulse can be generated by open loop and closed loop circuits.

The second PWM signal, which is synchronized with the original control signal, has a much shorter pulse width. The generated pulses drive a first pass stage, which controls the transfer of dynamic gate charge. Switch _S1 of the first stage is connected to a high peak current source to rapidly charge the gate and Miller capacitance of the device when turned on. The original control pulse is applied to the second conduction stage where switch _S2 supplies the necessary steady state DC gate current required to maintain conduction. The current limiting resistor _R1 is sized appropriately to set the forward gate current I _GFWD and step down the voltage from the positive rail voltage to the voltage required by the gate of the JFET. _R is sized in the same manner as is used for current limiting resistors in AC-coupled RC drive circuits. The complement of the user-supplied PWM pulse controls the cut-off stage, which pulls the JFET gate low through the low-resistance pull-down resistor _R3 . This driver approach can be implemented in a variety of ways, such as using discrete transistors, multiple driver ICs, or a single dual driver IC. The method chosen will depend on the required driver voltage, transition time and desired peak current supply.

The original control pulse is applied to the second conduction stage, which provides the necessary steady state DC gate current required to maintain conduction. The current limiting resistor is sized appropriately to set the forward gate current and step down the voltage from the positive rail voltage to that required by the gate of the JFET. When the user-input PWM signal transitions to a logic state indicative of the JFET's desired _toff duration, the pull-down circuit pulls the gate to the switch-common or negative voltage through a small pull-down resistor.

Depending on the transistor technology used (ie, FET or bipolar), an inverting circuit may not be necessary to drive the pull-down circuit. Figure 4 shows a DC coupled dual stage gate driver for a wide bandgap JFET with feedback to a pulse generator circuit. 5 is a circuit diagram of a DC-coupled dual-stage gate driver for a wide bandgap JFET according to another embodiment. 6 is a circuit diagram of a DC-coupled dual-stage gate driver for a wide bandgap JFET with feedback to a pulse generator circuit according to another embodiment. As shown in Figure 4 to Figure 6, the dual-stage gate driver is divided into 3 parts.

Figures 10A-10F provide corresponding waveforms describing complete gate driver operation. During period _t1 , the first conduction circuit is active. The user input _Vin shown in Figure 10A is received and the pulse generator circuit derives the second control pulse _Vc2 shown in Figure 10B. _Vc2 drives a switch that connects the gate of the JFET to a high peak current source through a small damping resistor _R2 . The waveform for the gate current (I _G ) shown in FIG. 1F illustrates that the gate current is high during t ₁ and is < 1A. After the drain-source voltage V _DS collapses shown in FIG. 10E , the first pass circuit is turned off.

In the case of the preferred embodiment, the duration of time _tl can be adjusted _manually , or automatically based on feedback from the JFET. At the beginning of _t1 , the second conduction circuit is also turned on. However, the small current contribution of this stage of the driver is minimal compared to the contribution of the first conduction stage. After the first conduction circuit is deactivated, the second conduction circuit regulates the DC gate current (≦1A) for the remainder of the conduction period. From Fig. 10F, it can be seen that at the beginning of _t2 , _IG decreases to a much smaller value. The end of the _t2 period is determined by the user input voltage. At the end of period _t2 the gate pull-down circuit is activated and period _t3 begins. During this period, the JFET transitions to a blocking state and remains blocked until the next input pulse is received. During _t3 , the pull-down circuit holds the gate of the device at a voltage common to the switches or negative for the duration of the blocking state.

FIG. 7 is a circuit diagram showing a part of the gate driver in operation during period _t1 . FIG. 8 is a circuit diagram showing a part of the gate driver in operation during period _t2 . FIG. 9 is a circuit diagram showing a part of the gate driver in operation during period _t3 .

Exemplary implementation

A circuit is provided, the circuit comprising:

Wide Bandgap Junction Field Effect Transistors (JFETs); and

DC-coupled, dual-stage driver, where the driver consists of:

a first conduction circuit;

a second conduction circuit; and

pull-down circuit,

Wherein, the driver is configured to receive an input pulse width modulation (PWM) control signal and generate an output driver signal for driving the gate of the wide bandgap JFET.

The period of the user input control pulse may be equal to the sum of the pulse duration t _on indicating the time the JFET is conducting and the pulse duration t _off indicating the time the JFET is to be blocking.

The first pass circuit may include a pulse generator circuit and a high peak current source. The pulse generator circuit can receive a PWM control signal input by a user and generate a second control pulse. The output can be synchronized with the user-input pulse, but have < 15% of the pulse width of the user-input pulse. The first pass circuit may be connected to the positive rail voltage +V ₁ . Pulse width can be adjustable. For example, the pulse width can be adjusted manually or automatically based on feedback from the JFET.

The first pass circuit may connect the gate of the wide bandgap JFET to a high peak current source through a low value (eg, <10 ohms) damping resistor.

The first on circuit may be active during < 15% of the t _on duration of the user input control pulse, as determined using the pulse generator circuit.

A second pass circuit may connect the gate of the transistor to the positive voltage rail + _V2 through a current limiting resistor (eg, <2000 ohms). The second on circuit may be active for the entire duration of to _on of the user input control pulse.

A pull-down circuit may connect the gate of the transistor to a circuit common or negative voltage _-V3 through a low damping resistor (eg, <100 ohms). The pull-down circuit may include an inverter circuit. The pull-down circuit may be active for a duration of t _off of the voltage input by the user.

The positive rail voltages + _V1 and + _V2 can be separate positive voltages, or connected to the same positive voltage rail.

experiment

Enhancement mode (EM) SiC JFETs are driven using dual driver ICs. This approach is depicted in Figure 11A. In this circuit, Driver A controls the dynamic charge condition and Driver B controls the steady state gate condition. The pulse width of the input to driver A can be limited to ≤200ns. Since the purpose of Driver A is to hand over high peak currents to charge the device input capacitance, its pulse width should not exceed the device on-time by more than 100ns. In addition, the high peak current supplied at the turn-on instant is internally distributed so that it transfers the charge to the input capacitor, not just through the gate-source diode. This results in an overshoot of the gate voltage greater than +3V at precisely limited times. However, when the input capacitor is fully charged and the drain voltage has collapsed completely, the gate voltage will continue to rise, allowing high current to flow to the gate-source diode until Driver A turns off. It is recommended that the time difference between the end of the transition period and the time to turn off driver A be minimized as much as possible. For any duration that driver A remains active during the conduction period, excessive power dissipation will be dissipated by the gate, which can result in damage to the gate if the duration is longer than 100ns.

FIG. 11B presents some experimental results for driving SiC JFETs using the dual drive circuit depicted in FIG. 11A . The SiC JFET used was SJEP120R125 manufactured by SemiSouth Laboratories, Inc. Gate drive voltages of +15V and -10V were provided, and resistors of corresponding size were set (ie, R ₁ =R ₃ =5 ohms, R ₂ =135 ohms). Driver A pulse width is set to 100ns.

FIG. 11B shows that during the turn-on transition, at V _GS =+6V, I _GS(PK) = 2A. Steady state conditions were measured at _VGS = +3V and _IGS = 100mA with Driver A off and Driver B in control.

Switching power consumption is one of the main performance factors used in comparing different semiconductor transistors for new designs. Minimizing this figure is a priority for high switching frequency applications, since this type of loss can become a significant portion of the total device power dissipation. Normally-off SiC JFETs are measured according to the same standards as MOSFETs/IGBTs. Use a standard, double-pulse clamped inductive load test circuit to observe energy loss during both turn-on and turn-off. Measurements were also performed based on different drive voltage recommendations (ie, unipolar or bipolar drive) and switching configurations (ie, single device or bridge configuration). Measurements were also performed at elevated temperatures, showing that there is little change in the switching energy as the junction temperature increases.

For single-device applications, such as buck-boost converters, a unipolar drive voltage is usually sufficient to drive EM SiC JFETs. In these types of circuits, current is passed between the main power transistor and a free-wheeling diode. Although each application/design may present a different set of conditions, experimental results to date have demonstrated that the use of a negative rail is generally unnecessary in single switch applications. The use of an AC-coupled, RC driver also proves sufficient for most single-switch applications with a bypass capacitor that provides some negative bias when off (duration of negative bias based on RC time constant) pressure to aid in fast cutoff and to provide some degree of noise immunity for a limited amount of time. The switching losses of a SiC JFET (i.e., SJEP120R125) were observed under various conditions. The +15V unipolar driver IC and +15V/-10V bipolar driver combined with this AC-coupled, RC driver interface were evaluated using the test circuit shown in Figure 12A. The duty cycle was adjusted to observe the difference in switching losses when the bypass capacitor was allowed to fully or partially discharge. Table 1 lists the resulting conduction losses for each case. As desired, the turn-on energy loss can be greater by up to 2x more when the bypass capacitor is not allowed to fully discharge before the next switching event. These results may or may not be sufficient based on the needs of a particular application and may require the use of a dual stage driver with a modest negative rail to achieve higher switching frequencies or higher duty cycles.

Using the bridge configuration as shown in Figure 12B, the test circuit for condition-based monitoring of switching energy was modified to reflect the conditions experienced in the application. For these applications, shoot-through can be a real problem, so noise immunity must be evaluated. A negative drive voltage is recommended for cutoff to help improve noise immunity and prevent shoot through caused by the "Miller effect". Similar to MOSFETs and IGBTs, there are three general ways to prevent positive spikes on the gate voltage from reaching the threshold voltage of the device:

a. Negative drive voltage on the gate during turn-off;

b. Closely connected capacitive clamps at the gate-source terminals;

c. dV/dt during limit switching.

If the lowest possible switching loss is required, as a first approach, it is recommended to increase the voltage difference between the cut-off voltage and the threshold voltage by adding or increasing the amount of negative voltage. This is the easy solution and the only one that does not affect the switching performance of the high or low side devices. However, as with all field-controlled power devices, there is a limit to the amount of negative voltage that can be applied to the gate of a SiC JFET. If the positive gate spike is still evident after applying the maximum negative voltage, another way must be used. Tightly connected capacitive clamps at the gate-source terminals of each device will provide a secondary source to pull the necessary displacement current. This will reduce the positive spike at the gate; however, this approach will require the gate driver to hand over more gate charge during each turn-on switching event. A modest increase in gate drive power and possibly slower turn-on speed will be observed. A final option is to adjust the dV/dt down by adjusting the series gate resistance of the gate drive. This will reduce the peak current through the Miller capacitance of both switches and reduce the probability of shoot through by blocking the switches. This third option will result in significantly slower switching compared to the possible maximum; therefore, the designer must make a trade-off for each specific application.

14A and 14B show switching energy measurements for a SiC JFET (SJEP120R125) tested in all phase legs using the test circuit of FIG. 12B.

Table 1 includes the switching losses observed using the test setup described in FIG. 12B using DC coupled gate drivers.

Table 1: Switching energy loss of SJEP120R125 (Condition: V _DS =600V, I _D =12A)

Figures 15A and 15B show the measured switching energy loss as a function of load current and junction temperature for two SiC JFETs (ie, SJEP120R125 and SJEP120R063, both manufactured by SemiSouth Laboratories, Inc). As shown, there is about a 10% increase in total switching energy between 25°C and 150°C junction temperatures.

Even though enhancement-mode SiC JFETs are a new device technology, many of the same design and layout techniques that work for other types of high-frequency power transistors apply to SiC JFET designs. Care must always be taken when creating a PCB layout for a power converter so as not to introduce additional coupling capacitors, not to mount devices close to switching ICs and magnetics, to use a symmetrical layout when paralleling devices, and to obtain sufficient cooling/dissipation.

Gate ringing can be caused by high frequency noise fed back through the device's Miller capacitance or by ground bounce caused by improper separation of signal and power grounds. The layout should be designed to properly separate power ground and signal ground by making a common connection between the two at a single point. Also, proper use of a ground plane can help shield the gate from the drain and other high-frequency circuit connections. It is also possible to use a ferrite bead connected as closely as possible to the gate terminal of the SiC JFET to reduce voltage spikes at the gate. Small, low-resistance external gate resistors may also suffice, as used in the design examples presented in this document. The use of a series R-C snubber connected directly on the main DC voltage bus has been shown to reduce the amount of high frequency noise feedback through Miller capacitance. Finally, the gate driver and gate stop components should always be connected as close as possible to the gate terminal of the device to reduce all of the above contributors to gate noise.

The specifications of the application can be evaluated to determine the best gate driver approach. The use of dual driver ICs is the easiest way. However, two separate driver ICs can be used to achieve the desired peak current level. The derivation of the overdrive pulse should be precise and closely match the transistor turn-on speed to minimize unnecessary gate power dissipation.

As with any low-threshold device, noise immunity is an important aspect. When using EM SiC JFETs in bridge or series configurations, a negative cut-off voltage is recommended. As with MOSFETs/IGBTs, JFETs can also experience false triggering due to the "Miller effect". However, this adverse effect can be minimized by increasing the voltage difference between the cut-off voltage and the gate threshold voltage. If positive gate voltage spikes are still a problem, a small capacitive clamp added on the gate-source terminal is recommended to limit the effect of high dV/dt on the gate of the opposing JFET.

Additional implementation

Also provided is a circuit comprising: a wide bandgap junction field effect transistor (JFET) and a DC coupled dual stage driver. The driver includes: an upper conduction driver (U9) circuit; a lower conduction driver (U11) circuit; and a logic gate U12 for receiving a signal from its input and generating a signal for the upper conduction driver (U9) a brief "on" pulse. The upper driver and the lower driver are configured to receive an input pulse width modulation (PWM) control signal and generate an output driver signal VG for driving the gate of the wide bandgap JFET.

According to this embodiment, the upper turn-on driver comprises a turn-on driver U9, a first resistor (5) and a first diode D1, wherein the output of the turn-on driver U9 is coupled to the first terminal of the first resistor, the first The second terminal of the resistor is coupled to the anode terminal of the first diode D1, and the cathode of the first diode D1 forms the output of the upper driver circuit. The lower conduction driver includes a conduction driver U11, a second resistor (100) having a first terminal and a second terminal, a second diode D2 having an anode and a cathode, and a third resistor having a first terminal and a second terminal. Resistor. The output of conduction driver U11 is coupled to the first terminal of the second resistor and the cathode of the second diode D2. The anode of the second diode D2 is coupled to the first terminal of the third resistor. The second terminal of the third resistor is coupled to the second terminal of the third resistor to form the output of the lower driver circuit. The output of the upper driver circuit and the output of the lower driver circuit are connected together to form an input to a wide bandgap junction field effect transistor JFET.

A dual driver circuit is used to drive enhancement mode (EM) SiC JFETs. Figure 16A depicts this approach. In this circuit, the output of logic gate U12 is connected to the input of upper conduction driver U9 and the input of lower conduction driver U11.

FIG. 16B shows the dead time of the input VA of the logic gate U12 and the output VB of the logic gate U12. The waveform of the output of the upper conduction driver U9 is shown as V1 in FIG. 16C , and the waveform of the output of the lower conduction driver U11 is shown as V2 in FIG. 16C .

Figure 16C shows that the upper conduction driver U9 causes an additional time delay compared to the output of the lower conduction driver U11. This delay is well after the "maintain on" pulse from down driver U11. An effective way to reduce the time delay consists of adding an RC delay circuit of 1.5K resistor and 120pF capacitor at the input of the down driver U11 to align V1 and V2, as shown in Figure 16D. The resistance and capacitance values of the RC delay circuit can be chosen such that the output of the upper conduction driver U9 and the output of the lower conduction driver U11 will go high simultaneously.

In FIG. 16D, the output of the upper conduction driver U9 and the output of the lower conduction driver U11 are shown going high at the same time. Slow turn-off was observed when the third resistor (6.8 ohms shown) and second diode D2 were not used as shown in Figure 16D. For faster turn off, a third resistor (shown as 6.8 ohms) and second diode D2 are used to produce a faster turn off. Figure 16E shows the effect of adding a speed-up circuit.

Also provided is a circuit comprising: a wide bandgap junction field effect transistor (JFET) and a DC coupled dual stage driver. According to this embodiment, the driver includes: a logic circuit for receiving a pulse width modulation (PWM) control signal and generating an enable signal and an inverted PWM signal; an IC driver (509) circuit, the IC driver (509) The circuit has a PWM input signal and an enable signal input from a logic circuit (LOGIC); and a transistor driver circuit having an input of an inverted PWM signal. The IC driver (509) circuit and the transistor driver circuit are configured to receive an input pulse width modulation (PWM) control signal and generate an output driver signal VG for driving the gate of the wide bandgap JFET.

The logic circuit (LOGIC) according to this embodiment comprises: a first NOR gate, a second NOR gate, a first capacitor with a first terminal and a second terminal, a second diode (1N914) with an anode and a cathode , a fourth resistor 500 having a first terminal and a second terminal, a third NOR gate and a fourth NOR gate. Each of the first, second, third and fourth NOR gates has a first input, a second input and an output. The detailed circuit layout is depicted in Figure 17A.

The IC driver (509) circuit includes 509 a driver IC and a first resistor 1. The 509 driver IC has a positive power supply, a negative power supply, an input terminal for receiving a PWM control signal, an input terminal for receiving an enable signal, and an output terminal. The input terminal for receiving the enable signal receives the enable signal from the output of the logic circuit (LOGIC). The input terminal receives a PWM control signal. 509 The output of the driver IC is coupled to the first terminal of the first resistor, and the second terminal of the first resistor is coupled to the gate terminal of the JFET.

The transistor driver circuit comprises: a zener diode D1 having an anode and a cathode, a second resistor 100 having a first terminal and a second terminal, a transistor (2N3906) having a base terminal, an emitter terminal and a collector terminal and a second resistor having a first terminal A third resistor 15 with one terminal and a second terminal. The anode of Zener diode D1 forms the input to the transistor driver circuit. The cathode of the Zener diode D1 is connected to the first terminal of the second resistor 100 . The second terminal of the second resistor 100 is connected to the base terminal of the transistor. The emitter terminal of the transistor is connected to the positive power supply of the transistor driver. The collector terminal of the transistor is connected to the first terminal of the third resistor. The second terminal of the third resistor is connected to the output of the IC driver (509) circuit and the gate terminal of the JFET.

The output of the IC driver (509) circuit and the output of the transistor driver circuit are connected together to form an input to a wide bandgap junction field effect transistor (JFET).

The driver structure as explained above is used to drive enhancement mode (EM) SiC JFETs. Figure 17A depicts this method. In this circuit, the output of the logic circuit (LOGIC) is connected to the enable signal input of the IC driver circuit, and the inverted signal of the PWM signal output of the logic circuit (LOGIC) is connected to the input terminal of the transistor driver circuit. Figure 17B shows the double pulse waveform of the voltage between the gate terminal and the source terminal of the JFET, and the current flowing into the gate of the JFET. Figure 17C shows the turn-on voltage between the gate terminal and the source terminal of the JFET and the turn-on pulse current flowing into the gate of the JFET, showing the peak value of the current at 5.5A. Therefore, at least one high current driver such as an IC driver should be included for both switching on and off. Ripple effects at the turn-on and turn-off edges are shown when viewed on an enlarged time scale. Figure 17D shows the double pulse current flowing into the gate of the JFET. It shows that the turn-on and turn-off edges are quick and clean. The "stay" current can be provided using lower current transistors powered from a lower power supply. Such a structure serves to economize on components and reduce losses in the associated gate resistors. FIG. 17E shows the turn-on voltage between the gate terminal and the source terminal of the JFET, and the turn-on pulse current flowing into the gate of the JFET. Ripple effects at the turn-on and turn-off edges are shown when viewed on an enlarged time scale.

Figure 18A shows another similar dual stage driver circuit. Only the components around the JFET are further added and modified. FIG. 18B shows the on-voltage between the gate terminal and the source terminal of the JFET, and the off-current flowing into the gate terminal of the JFET. FIG. 18C shows the off voltage between the gate terminal and the source terminal of the JFET and the off current flowing into the gate terminal of the JFET. The cut-off waveform shows obvious ripples. While not wishing to be bound by theory, it is believed that the cause of such ripple may be related to high dV/dT false triggering of logic circuits due to "sky-wiring" of the logic circuits.

The foregoing description of exemplary embodiments of the present invention has been presented for purposes of illustration and description only, and is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.

The embodiments were chosen and described in order to explain the principles of the invention and its practical application, to enable others skilled in the art to utilize the invention with various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which this invention pertains without departing from its spirit and scope. Accordingly, the scope of the present invention is defined by the appended claims rather than by the foregoing description and the exemplary embodiments described herein.

references

[1] D.Bortis, P.Steiner, J.Biela, and J.W.Kolar, "Double-Stage Gate Driver Circuit for Parallel Connected IGBT Modules," Proc. of the 2008 IEEE International PowerModulator Conference (2008).

[2] G.Schmitt, R.Kennel, and J.Holtz, "Voltage Gradient Limitation of IGBTs by Optimized Gate-Current Profiles," Power Electronics Specialists Conference, 2008.PESC2008, pp.3592-3596 (Jun.15-19, 2008).

[3] M.Abu-Khaizaran, P.Palmer, and Y.Wang, "Parameters Influencing the Performance of an IGBT Gate Driver," Power Electronics Specialists Conference, 2008, pp.3457-3462 (Jun.15-19, 2008) .

Claims (30)

1. A dual-stage gate driver circuit for driving a junction field-effect transistor (JFET) having gate, source and drain, said dual-stage gate driver circuit comprising: an input terminal, the input terminal is used to provide a control pulse signal V _in ; three resistors _R1 , _R2 and _R3 each having a first terminal and a second terminal electrically coupled to the gate of the JFET through the second terminal; a first conduction circuit electrically coupled between said input and said first terminal of said resistor _R2 ; a second conduction circuit electrically coupled between said input and said first terminal of said resistor _R1 ; and a pull-down circuit electrically coupled between the input and the first terminal of the resistor _R3 . 2. The dual-stage gate driver circuit according to claim 1, wherein the control pulse signal V _in is configured to have a pulse duration t _on and a pulse off duration t _off , so that during the pulse duration t _on , the JFET is in a conduction state, and the JFET is in a blocking state during the off-pulse duration t _off . 3. The dual-stage gate driver circuit according to claim 2, wherein the first conduction circuit comprises: a switch S1 having a gate, a source electrically coupled to said first terminal of said resistor R2, and a drain electrically coupled to a first current source for providing a positive voltage + _V1 ; and a pulse generator electrically coupled between the input terminal and the gate of the switch S1. 4. The dual-stage gate driver circuit of claim 3 , wherein the second pass circuit comprises a switch S2 having a gate electrically coupled to the input terminal, a gate electrically coupled to the resistor R1 The source of said first terminal is electrically coupled to the drain of a second current source for supplying a positive voltage + _V2 . 5. The dual-stage gate driver circuit of claim 4, wherein the first current source and the second current source correspond to a single current source or two different current sources. 6. The dual-stage gate driver circuit according to claim 4, wherein the pull-down circuit comprises a switch S3 having a gate electrically coupled to the input terminal, electrically coupled to a gate for providing a negative voltage _-V3 The source of the third current source and the drain electrically coupled to the first terminal of the resistor R3. 7. The dual-stage gate driver circuit according to claim 6, wherein the pull-down circuit further comprises an inverter electrically coupled between the input terminal and the gate of the switch S3. 8. The dual-stage gate driver circuit according to claim 7, wherein when the control pulse signal _Vin is provided: said pulse generator responsively generates a corresponding control pulse signal V _c2 having a pulse duration t ₁ , said control pulse signal V _c2 turning on said switch S1 for a pulse duration t ₁ ; Said control pulse signal _Vin respectively makes said switch S2 conduct in said pulse duration t _on and makes said switch S2 turn off in said pulse duration t _off ; and The control pulse signal _Vin respectively turns off the switch S3 during the pulse duration t _on and turns on the switch S3 during the pulse duration t _on . 9. The dual-stage gate driver circuit according to claim 8, wherein the generated control pulse signal _Vc2 is synchronized with the control pulse signal, and wherein the pulse duration _t1 of the generated control pulse signal _Vc2 is equal to Or less than 15% of the pulse duration t _on of the control pulse signal _Vin . 10. The dual-stage gate driver circuit according to claim 9, wherein the pulse duration _ti of the generated control pulse signal V _c2 can be adjusted manually. 11. The dual-stage gate driver circuit according to claim 9, wherein the pulse duration _t1 of the generated control pulse signal V _c2 can be automatically adjusted according to the feedback signal V _FB from the JFET. 12. A dual stage gate driver circuit for driving a junction field effect transistor (JFET) having a gate, a source and a drain, the dual stage gate driver circuit comprising: an input terminal, the input terminal is used to provide a control pulse signal V _in ; a first conduction circuit; a second conduction circuit; and pull-down circuit, Wherein, the first conduction circuit, the second conduction circuit and the pull-down circuit are electrically coupled in parallel between the input terminal and the gate of the JFET. 13. The dual-stage gate driver circuit according to claim 12, wherein the control pulse signal V _in is configured to have a pulse duration t _on and a pulse off duration t _off , so that at the pulse duration t _on The JFET is in the conduction state in , and the JFET is in the blocking state during the off-pulse duration t _off . 14. The dual-stage gate driver circuit according to claim 13, wherein the first turn-on circuit comprises: a switch S1 having a gate, a source electrically coupled to the gate of the JFET through a resistor R2, and a drain electrically coupled to _{a first} current source for providing a positive voltage +V; and a pulse generator electrically coupled between the input terminal and the gate of the switch S1. 15. The dual-stage gate driver circuit according to claim 14, wherein said pulse generator is configured such that when said control pulse signal V _in is provided, said pulse generator responsively generates The control pulse signal V _in is synchronized with the corresponding control pulse signal V _c2 . 16. The dual-stage gate driver circuit according to claim 15, wherein the generated _control pulse signal V _c2 has a pulse duration t ₁ which is equal to or less than the pulse of the control pulse signal V _in 15% of duration t _on . 17. The dual-stage gate driver circuit according to claim 16, wherein the pulse duration _ti of the generated control pulse signal V _c2 can be adjusted manually. 18. The dual-stage gate driver circuit according to claim 16, wherein the pulse duration _t1 of the generated control pulse signal _Vc2 can be automatically adjusted according to the feedback signal _VFB from the JFET. 19. The dual-stage gate driver circuit of claim 14 , wherein the second pass circuit comprises a switch S2 having a gate electrically coupled to the input terminal, a gate electrically coupled to the input terminal through a resistor R1 The source of the gate of the JFET and the drain are electrically coupled to a second current source for supplying a positive voltage + _V2 . 20. The dual-stage gate driver circuit of claim 19, wherein the pull-down circuit comprises: a switch S3 having a gate, a source electrically coupled to a third current source for providing a negative voltage _-V3 , and a drain electrically coupled to the gate of said JFET through a resistor R3; and an inverter electrically coupled between the input terminal and the gate of the switch S3. 21. The dual-stage gate driver circuit of claim 13 , wherein the first pass circuit is electrically coupled between a first current source and the gate of the JFET through the resistor R2, wherein the The first current source is set to provide a positive voltage +V ₁ . 22. The dual-stage gate driver circuit according to claim 21, wherein, in operation, when the control pulse signal Vin _is at the pulse duration t _on , the first turn-on circuit is equal to or less than The control pulse signal V _in is turned on during the duration _t1 of 15% of the pulse duration t _on , and when the control pulse signal V _in is at the pulse off duration t _off , the first conduction The on-circuit is switched off during the pulse-off duration t _off . 23. The dual-stage gate driver circuit of claim 22, wherein the second turn-on circuit is electrically coupled between a second current source and the gate of the JFET through a resistor R1, wherein R1>R1, And wherein said second current source is set to provide a positive voltage +V ₂ . 24. The dual-stage gate driver circuit of claim 23, wherein the first current source and the second current source correspond to a single current source or two different current sources. 25. The dual-stage gate driver circuit according to claim 23, wherein, in operation, when the control pulse signal Vin _is at the pulse duration t _on , the second conduction circuit is at the pulse The second conduction circuit is turned on during the duration t _on , and when the control pulse signal _Vin is at the pulse off duration t _off , the second conduction circuit is turned off during the pulse off duration t _off . 26. The dual-stage gate driver circuit of claim 23 , wherein the pull-down circuit is electrically coupled between a third current source and the gate of the JFET through a resistor R3, wherein the third current source is Set to provide negative voltage -V ₃ . 27. The dual-stage gate driver circuit of claim 26, wherein the pull-down circuit includes an inverter electrically coupled between the input terminal and the resistor R3. 28. The dual-stage gate driver circuit according to claim 27, wherein when the control pulse signal _Vin is at the pulse duration t _on , the pull-down circuit is turned off during the pulse duration t _on , And wherein when the control pulse signal Vin is _in the pulse-off duration t _off , the pull-down circuit is turned on during the pulse-off duration t _off . 29. The dual stage gate driver circuit of claim 1, wherein the JFET is a wide bandgap JFET or a SiC JFET. 30. The dual stage gate driver circuit of claim 12, wherein the JFET is a wide bandgap JFET or a SiC JFET.

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