CN102420135A - Channel Stress Adjustment Method - Google Patents

Abstract

The invention provides a channel stress adjusting method, which comprises the following steps: providing a substrate; forming a metal oxide semiconductor transistor on the substrate, wherein the metal oxide semiconductor transistor comprises a source drain region, a channel, a grid insulating layer and a grid side wall structure; forming a dielectric layer on the substrate and covering the metal oxide semiconductor transistor; carrying out a planarization process on the dielectric layer; removing the flattened residual dielectric layer to expose the source/drain region; and forming a non-uniform coating high-stress dielectric layer on the substrate with the exposed source/drain region.

Description

Channel Stress Adjustment Method

technical field

The present invention relates to a channel stress adjustment method, and in particular to a channel stress adjustment method applied in the fabrication of metal oxide semiconductor transistors.

Background technique

In integrated circuit manufacturing technology, high dielectric constant insulating layer/metal gate (High-K/MetalGate, hereinafter referred to as HK/MG) technology has been widely used. This technology allows manufacturers to reduce the leakage current of components and make integrated The performance of the circuit continues to improve. However, there are currently two different HK/MG integration schemes in parallel, namely the gate-first process (hereinafter referred to as Gate-first) and the gate-last process (hereinafter referred to as gate-last). In the Gate-first process, HK/MG is placed before the gate is formed; as for the Gate-last process, the metal gate is filled after the polysilicon dummy gate is removed.

Please refer to FIG. 1a and FIG. 1b, which are partial schematic diagrams of metal-oxide-semiconductor transistors in the conventional process. In FIG. The polysilicon gate 11 covered by the mold 16 is formed on the gate insulating layer 12 above the channel 100. If it is a Gate-last process, the polysilicon gate 11 is a dummy poly gate (dummypoly), and is covered by the sidewall of the gate. Structure (spacer) 13 surrounds. The gate insulating layer 12 can be a multi-layer structure as shown in the figure, consisting of a silicon oxide layer 120 and a high dielectric constant insulating layer (HK) 121, and the gate sidewall structure (spacer) 13 can also be as follows The multi-layer structure shown in the figure-the first gate sidewall layer 131 and the second gate sidewall layer 132 . Next, a contact etch stop layer (Contact Etch Stop Layer, CESL for short) 14 covers it, and then an interlayer dielectric layer (Interlayer dielectric, ILD for short) 15 is formed. Due to the need for planarization, as shown in FIG. 1b, top-cut chemical mechanical polishing (top-cut Chemical Mechanical Polishing) will be performed next to smooth some structures on the surface of the substrate 10, such as part of the interlayer dielectric layer in the figure. 15. A part of the contact hole etch stop layer 14 and the hard mask 16 are formed to form a structure as shown in the figure for subsequent processes, such as removal of dummy polysilicon gates and insertion of metal gates.

With gate length scaling stalled and new materials yet to be proven, the mobility-tuning process has become one of the most important contributors to improved IC performance. The lattice strain (strain) of the channel 100 has been commonly used to enhance the mobility during the production of devices, and the hole mobility and electron mobility provided by the strained silicon lattice can reach 4 times that of unstrained silicon. with 1.8 times.

Therefore, designers can apply tensile stress to the channel of N-channel MOS transistors or compressive channels of P-channel MOS transistors by modifying the structure of the transistors. Compression stress. Because stretching the channel can improve the mobility of electrons, and compressing the channel can improve the mobility of holes. Usually, a layer of silicon nitride (SiN) film is covered after the metal oxide semiconductor transistor element is manufactured, and the high stress characteristic of the silicon nitride film itself is used to control the stress in the electronic channel. Using different deposition conditions, the silicon nitride film can provide tensile stress to enhance the electron mobility of the N channel, and can also provide compressive stress to enhance the hole mobility of the P channel. In addition, the electron/hole mobility can be improved to different degrees by controlling the silicon nitride films with different thicknesses.

Therefore, in addition to the role of the contact hole etching stop layer 14 in the contact hole etching process, it can additionally play an important role in generating stress on the channel, thereby increasing the carrier mobility. That is, the contact hole etching stop layer 14 mostly made of silicon nitride is covered on the top of the metal oxide half field effect transistor, and the tensile or compressive stress of itself is used to adjust the metal oxide half field effect transistor channel. The lattice strain of the channel can be improved to achieve the purpose of increasing the carrier mobility.

However, when the contact hole etch stop layer 14 is damaged by the above-mentioned chemical mechanical polishing, the stress originally provided to the channel will change drastically, thereby adversely affecting the carrier mobility of the channel. How to improve these deficiencies is the main purpose of developing this application.

Contents of the invention

The purpose of the present invention is to provide a channel stress adjustment method, which includes the following steps: providing a substrate; forming a metal oxide semiconductor transistor on the substrate, the metal oxide semiconductor transistor includes an active drain region, a channel, a gate , gate insulating layer and gate sidewall structure; forming a dielectric layer above the substrate and covering the metal oxide semiconductor transistor; performing a planarization process on the dielectric layer; removing the planarized residual dielectric layer to expose the source and drain region; and re-forming a non-uniform covering high-stress dielectric layer on the substrate exposing the source and drain regions.

Another object of the present invention is to provide a channel stress adjustment method, which includes the following steps: providing a substrate; forming a metal oxide semiconductor transistor on the substrate, the metal oxide semiconductor transistor includes an active drain region, a channel, Dummy gate, gate insulating layer and gate sidewall structure; forming a dielectric layer above the substrate and covering the metal oxide semiconductor transistor; performing a planarization process on the dielectric layer to expose the dummy gate of the metal oxide semiconductor transistor ; Remove the dummy gate and fill it with a metal gate; Remove the planarized residual dielectric layer to expose the source and drain regions; metal oxide semiconductor transistors.

In a preferred embodiment of the present invention, the aforementioned substrate may be a silicon substrate, the aforementioned gate and dummy gate may be polysilicon gates, and the aforementioned gate insulating layer may include a silicon oxide layer and a high dielectric constant insulating layer. The aforementioned gate sidewall structure may include a first gate sidewall layer and a second gate sidewall layer.

In a preferred embodiment of the present invention, the above-mentioned dielectric layer includes a contact hole etch stop layer and an interlayer dielectric layer, and the method for covering the dielectric layer may include the following steps: forming a contact hole etch stop layer covering the substrate a metal oxide semiconductor transistor; and forming an interlayer dielectric layer on the etching stop layer of the contact hole.

In a preferred embodiment of the present invention, the above-mentioned contact hole etching stop layer can be a stress film in stress memory technology, and the above-mentioned planarization process can be a chemical mechanical polishing process, and is used to expose the gate or gate of the metal oxide semiconductor transistor. false gate.

In a preferred embodiment of the present invention, the above-mentioned non-uniform coating high-stress dielectric layer may include a high-stress dielectric layer to which tensile stress is applied and a high-stress dielectric layer to which compressive stress is applied, wherein the high-stress dielectric layer to which tensile stress is applied The dielectric layer covers the source-drain region of the N-channel MOS transistor, and the high-stress dielectric layer applying compressive stress covers the source-drain region of the P-channel MOS transistor.

In a preferred embodiment of the present invention, the above source and drain regions may have a recess, and the high stress dielectric layer may be filled into the recess. The material of the interlayer dielectric layer can be silicon oxide or polymer.

The present invention removes the residual dielectric layer after planarization and re-forms a non-uniform covering high-stress dielectric layer, which is used to provide tensile or compressive stress to the channel of the metal oxide half field effect transistor again, so as to increase the load The purpose of the carrier mobility, and then effectively achieve the main purpose of developing this application.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are described below in detail together with accompanying drawings.

Description of drawings

FIG. 1a and FIG. 1b are partial process schematic diagrams of metal-oxide-semiconductor transistors in a conventional process.

2a, 2b, 2c, 2d and 2e are schematic diagrams of a first preferred embodiment of a part of the process of metal-oxide-semiconductor transistors developed by the present application to improve common means.

FIG. 3 is a schematic diagram of the structure of a metal-oxide-semiconductor transistor developed by the present application to improve common means.

4a, 4b, 4c and 4d are schematic diagrams of a second preferred embodiment of a part of the process of metal-oxide-semiconductor transistors developed by the present application to improve common means.

FIG. 5 is a schematic diagram of the structure of a metal-oxide-semiconductor transistor developed by the present application to improve common means.

Explanation of reference signs

10, 20, 40: substrate

11, 21, 41: polysilicon gate

12, 22, 42: gate insulating layer

13, 23, 43: Gate sidewall structure

14, 24, 44: contact hole etch stop layer

15, 25, 45: interlayer dielectric layer

16, 26, 46: hard mask

121, 221, 421: high dielectric constant insulating layer

120, 220, 420: silicon oxide layer

27, 47: High stress dielectric layer

100, 200, 400: channel

101, 201, 401: source and drain regions

131, 231, 431: first gate sidewall layer

132, 232, 432: second gate sidewall layer

411: Work Function Metal Structures

412: Low-impedance metal structure

2010, 4010: Depression

Detailed ways

Please refer to FIGS. 2a, 2b, 2c, 2d and 2e, which are schematic diagrams of a first preferred embodiment of a part of the process of metal-oxide-semiconductor transistors developed by the present application to improve common means, wherein FIG. 2a shows the substrate 20. The source-drain region 201 and the channel 200 have been defined, and the gate 21 covered by the hard mask 26 is formed on the gate insulating layer 22 above the channel 200, and the gate 21 can be completed by a material containing silicon , such as doped silicon, undoped silicon, polysilicon, amorphous silicon, etc. If it is a Gate-last process, the gate 21 is a dummy polysilicon gate (dummy poly), and there is still a resistance formed by titanium nitride (TiN) or tantalum nitride (TaN) between the gate insulating layer 22. Barrier/etching stop layer (not shown), surrounded by gate sidewall structure (spacer) 23, if Gate-first process, still have one or more layers between gate 21 and gate insulating layer 22 work function metal layer (not shown). The gate insulating layer 22 can be a multi-layer structure as shown in the figure, consisting of a silicon oxide layer 220 and a high dielectric constant insulating layer (HK) 221, and the gate sidewall structure (spacer) 23 can also be as follows The multi-layer structure shown in the figure-the first gate sidewall layer 231 and the second gate sidewall layer 232 . The first gate sidewall layer 231 can be completed by a silicon oxide/silicon nitride composite layer or pure silicon oxide, while the second gate sidewall layer 232 can be made of a silicon oxide/silicon nitride composite layer or silicon nitride / silicon oxide / silicon nitride composite layer to complete. Next, a contact etch stop layer (Contact Etch Stop Layer, CESL for short) 24 is formed covering the channel 200, the source and drain regions 201, the gate 21, the gate insulating layer 22 and the gate sidewall structure 23, and then An interlayer dielectric (ILD) 25 is formed on the etch stop layer 24 of the contact hole.

Similarly, due to planarization requirements, as shown in FIG. 2b, the method of the present application will then perform a planarization process, such as a top-cut chemical mechanical polishing (top-cut Chemical Mechanical Polishing) process, for grinding the surface of the substrate 20. Part of the structure, such as part of the interlayer dielectric layer 25 , part of the contact hole etch stop layer 24 and the hard mask 26 in the figure, will be removed. In this way, part of the metal oxide semiconductor transistor such as the gate 21 and the gate sidewall structure 23 will be exposed from the planarized interlayer dielectric layer 25 and the contact hole etch stop layer 24 . It should be noted that in the planarization process, the top of the gate sidewall structure 23 may also be removed.

Because the contact hole etch stop layer 24 will be destroyed at this time, it has lost the function of providing stress to the trench 200, and the distance between the original contact hole etch stop layer 24 and the trench 200 is too far, so in order to ensure that the trench can be directly If the channel 200 provides stress, the method of this application directly removes the remaining interlayer dielectric layer 25 and the contact hole etch stop layer 24 by dry etching or wet etching, and in order to make the effect of applying stress on the channel better Notably, part or even all of the second gate sidewall layer 232 may also be removed by dry etching or wet etching to form as shown in FIG. 2 c .

Next, re-cover the substrate surface with a high-stress dielectric layer to form a non-conformal high-stress dielectric layer 27 as shown in FIG. Then cover the highly stressed dielectric layer applying tensile stress, and if it is a P-channel MOS transistor, cover the highly stressed dielectric layer applying compressive stress instead. The material of the high-stress dielectric layer can be silicon nitride or spin-on silicon oxide (Spin-On Glass, SOG for short).

Then another chemical-mechanical polishing is performed on the non-uniformly coated high-stress dielectric layer 27, and then forms as shown in FIG. 2e. As for the follow-up process, such as removing the polysilicon gate 21 and other steps, it can be the same as the usual method, so it will not be repeated.

In addition, the contact hole etch stop layer 24 can also be used as a stress film in a stress memory technique (Stress Memorization Technique, referred to as SMT). Stress memory technology mainly performs amorphization implantation on the exposed source and drain regions 201 to convert polysilicon into amorphous silicon, and then covers the contact hole etching stop layer 24, which acts as a stress film, on the amorphous silicon material. The source-drain region 201 is then subjected to anneal heat treatment, so that the source-drain region 201 can memorize the stress effect of the stress film covering it. Then, the interlayer dielectric layer 25 is formed on the contact hole etching stop layer 24 and then the above-mentioned planarization process and subsequent non-uniform coating of the high-stress dielectric layer 27 are performed.

In addition, in order to allow the non-uniform coating of the high-stress dielectric layer 27 to provide a better stress effect on the channel 200, the present application can also form a recess 2010 as shown in FIG. 3 on the source-drain region 201. The depression 2010 is formed by, for example, firstly etching to produce a cavity, and then filling the epitaxial layer of silicon and other materials, but the height of the epitaxial layer does not exceed the surface of the substrate. In this way, the high-stress dielectric layer 27 is non-uniformly coated. Stress can be applied to the channel 200 deeper into the substrate 20 to achieve a better lattice strain effect.

As for the material of the interlayer dielectric layer 25, in addition to silicon oxide, it can also be completed by other materials, such as a polymer (polymer), mainly based on the selectivity of chemical mechanical polishing and whether it will cause pollution in the process. Make material selection considerations.

Please refer to FIGS. 4a, 4b, 4c and 4d again, which are schematic diagrams of a second preferred embodiment of a part of the process of metal-oxide-semiconductor transistors developed by the present application in order to improve common means, wherein FIG. 4a shows the source on the substrate 40 The drain region 401 and the channel 400 have been defined, and a dummy gate covered by a hard mask 46, such as a dummy poly gate (dummy poly) 41, is formed on the gate insulating layer 42 above the channel 400 , and is surrounded by a gate sidewall structure (spacer) 43 . The polysilicon gate 41 can be made of other materials containing silicon, such as doped silicon, undoped silicon, amorphous silicon, and the like. A barrier/etch stop layer can be selectively provided between the dummy polysilicon gate 41 and the gate insulating layer 42. This barrier/etch stop layer usually contains metal elements, which can prevent the dummy polysilicon gate 41 from being isolated from the high dielectric constant. If there is a mismatch between layers (HK) 421, it can also be used as an etch stop layer when removing the dummy polysilicon gate 41; the material of this barrier etch stop layer is, for example, titanium nitride (TiN) or nitride Tantalum (TaN). The gate insulating layer 42 can be a multi-layer structure as shown in the figure, consisting of a silicon oxide layer 420 and a high dielectric constant insulating layer (HK) 421, and the gate sidewall structure (spacer) 43 can also be as follows The multi-layer structure shown in the figure-the first gate sidewall layer 431 and the second gate sidewall layer 432 . Next, a Contact Etch Stop Layer (CESL for short) 44 is formed covering the channel 400, the source-drain region 401, the polysilicon gate 41, the gate insulating layer 42 and the gate sidewall structure 43, and then An interlayer dielectric layer (Interlayer Dielectric, ILD for short) 45 is formed on the etch stop layer 44 of the contact hole.

Similarly, due to planarization requirements, as shown in FIG. 4b, the method of the present application will then perform a planarization process, such as a top-cut chemical mechanical polishing (top-cut Chemical Mechanical Polishing) process, for grinding the surface of the substrate 40. Part of the structure, such as part of the interlayer dielectric layer 45, part of the contact hole etch stop layer 44 and the hard mask 46 in the figure will be removed to expose part of the metal oxide semiconductor transistor such as dummy polysilicon gate (dummy poly) 41 and gate The pole sidewall structure 43 is exposed from the planarized interlayer dielectric layer 45 and contact hole etch stop layer 44 . Next, the dummy polysilicon gate 41 is removed to stop on the metal-containing barrier/etch stop layer, and then the work function metal structure 411 and the low resistance metal structure 412 are filled. It should be noted that in the planarization process, the top of the gate sidewall structure 43 may also be removed.

Then the remaining interlayer dielectric layer 45 and the damaged contact hole etch stop layer 44 are completely removed by dry etching or wet etching, and in order to make the effect of applying stress on the channel more significant, you can also use It is considered to remove part or even all of the second gate sidewall layer 432 by dry etching or wet etching, as shown in FIG. 4 c .

Next, the surface of the substrate is re-covered with a non-uniform high-stress dielectric layer 47, and then formed as shown in FIG. electrical layer, and in the case of P-channel metal-oxide-semiconductor transistors, it is replaced by a high-stress dielectric layer that applies compressive stress. Since the metal gate structure has been replaced, the non-uniform covering high-stress dielectric layer 47 in this embodiment does not need to undergo top-cut chemical mechanical polishing to expose the gate, so there is no risk of damage.

Of course, the contact hole etch stop layer 44 can also play the role of a stress film in a stress memory technique (Stress Memorization Technique, referred to as SMT). The recess 4010 shown in FIG. 5 can also be formed on the source-drain region 401 . As for the material of the interlayer dielectric layer 45, in addition to silicon oxide, it can also be completed by other materials, such as a polymer (polymer), mainly based on the selection ratio of chemical mechanical polishing and whether it will cause pollution in the process. Make material selection considerations.

In summary, the technical means of this application solves the adverse effects on the carrier mobility of the channel due to the damage of the contact hole etching stop layer by chemical mechanical polishing in common methods, and then achieves the main purpose of developing this application . Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (20)

1. A channel stress adjustment method, the method comprising the following steps: Provide the substrate; forming a metal oxide semiconductor transistor on the substrate, the metal oxide semiconductor transistor including an active drain region, a channel, a gate, a gate insulating layer and a gate sidewall structure; forming a dielectric layer over the substrate and covering the metal oxide semiconductor transistor; performing a planarization process on the dielectric layer; removing the planarized residual of the dielectric layer to expose the source and drain regions; and A non-uniform covering high-stress dielectric layer is re-formed on the substrate exposing the source-drain region. 2. The channel stress adjustment method according to claim 1, wherein the substrate is a silicon substrate, and the gate is a gate containing silicon. 3. The channel stress adjustment method according to claim 1, wherein the gate insulating layer comprises a silicon oxide layer and a high dielectric constant insulating layer. 4. The channel stress adjustment method according to claim 1, wherein the gate sidewall structure at least comprises a first gate sidewall layer and a second gate sidewall layer. 5. The channel stress adjustment method according to claim 1, wherein the dielectric layer comprises a contact hole etch stop layer and an interlayer dielectric layer, and the method for covering the dielectric layer comprises the following steps: forming a contact hole etch stop layer over the substrate covering the metal oxide semiconductor transistor; and An interlayer dielectric layer is formed on the etch stop layer of the contact hole. 6. The channel stress adjustment method as claimed in claim 5, wherein the etch stop layer of the contact hole is a stress film in stress memory technology. 7. The channel stress adjustment method as claimed in claim 1, wherein the planarization process is a chemical mechanical polishing process, and the planarization process is used to expose the gate of the metal oxide semiconductor transistor. 8. The channel stress adjustment method according to claim 1, wherein the non-uniform coating high-stress dielectric layer comprises a high-stress dielectric layer applied with tensile stress and a high-stress dielectric layer applied with compressive stress, wherein the A highly stressed dielectric layer applying tensile stress covers the source and drain regions of the N-channel MOS transistor, and a highly stressed dielectric layer applying compressive stress covers the source and drain regions of the P-channel MOS transistor polar region. 9. The channel stress adjustment method as claimed in claim 1, wherein the source-drain region has a recess, and the high-stress dielectric layer fills the recess. 10. The channel stress adjustment method as claimed in claim 1, wherein the material of the interlayer dielectric layer is silicon oxide or polymer. 11. A channel stress adjustment method, the method comprising the following steps: Provide the substrate; forming a metal oxide semiconductor transistor on the substrate, the metal oxide semiconductor transistor comprising an active drain region, a channel, a dummy gate, a gate insulating layer and a gate sidewall structure; forming a dielectric layer over the substrate and covering the metal oxide semiconductor transistor; performing a planarization process on the dielectric layer to expose the dummy gate of the metal oxide semiconductor transistor; Fill in the metal after removing the dummy gate; removing the planarized residual of the dielectric layer to expose the source and drain regions; and On the substrate exposing the source and drain regions, a non-uniform covering high-stress dielectric layer is re-formed to cover the metal oxide semiconductor transistor. 12. The channel stress adjustment method according to claim 11, wherein the substrate is a silicon substrate, and the dummy gate is a gate containing silicon. 13. The channel stress adjustment method as claimed in claim 11, wherein the gate insulating layer comprises a silicon oxide layer and a high dielectric constant insulating layer. 14. The channel stress adjustment method according to claim 11, wherein the gate sidewall structure at least comprises a first gate sidewall layer and a second gate sidewall layer. 15. The channel stress adjustment method according to claim 11, wherein the dielectric layer comprises a contact hole etch stop layer and an interlayer dielectric layer, and the method for covering the dielectric layer comprises the following steps: forming a contact hole etch stop layer over the substrate covering the metal oxide semiconductor transistor; and An interlayer dielectric layer is formed on the etch stop layer of the contact hole. 16. The channel stress adjustment method as claimed in claim 15, wherein the contact hole etch stop layer is a stress film in stress memory technology. 17. The channel stress adjustment method as claimed in claim 11, wherein the planarization process is a chemical mechanical polishing process. 18. The channel stress adjustment method as claimed in claim 11, wherein the high-stress dielectric layer comprises a high-stress dielectric layer to which tensile stress is applied and a high-stress dielectric layer to which compressive stress is applied, wherein the tensile stress is applied The high-stress dielectric layer covers the source-drain region of the N-channel MOS transistor, and the high-stress dielectric layer applying compressive stress covers the source-drain region of the P-channel MOS transistor. 19. The channel stress adjustment method as claimed in claim 11, wherein the source-drain region has a recess, and the high-stress dielectric layer fills the recess. 20. The channel stress adjustment method as claimed in claim 11, wherein the material of the interlayer dielectric layer is silicon oxide or polymer.

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