CN102420131B - Silicon wafer back silicon nitride growth method integrated in FEOL (front end of line) - Google Patents
Silicon wafer back silicon nitride growth method integrated in FEOL (front end of line) Download PDFInfo
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- CN102420131B CN102420131B CN201110183456.2A CN201110183456A CN102420131B CN 102420131 B CN102420131 B CN 102420131B CN 201110183456 A CN201110183456 A CN 201110183456A CN 102420131 B CN102420131 B CN 102420131B
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- silicon nitride
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- 238000000034 method Methods 0.000 title claims abstract description 71
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 63
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 63
- 239000010703 silicon Substances 0.000 title claims abstract description 63
- 229910052581 Si3N4 Inorganic materials 0.000 title claims abstract description 61
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 31
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 10
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 230000000694 effects Effects 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 230000007306 turnover Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 abstract description 52
- 230000008021 deposition Effects 0.000 abstract description 4
- 239000008187 granular material Substances 0.000 abstract description 3
- 239000011241 protective layer Substances 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000010287 polarization Effects 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a silicon wafer back silicon nitride growth method integrated in an FEOL (front end of line). According to the method, existing process equipment is utilized to carry out low temperature silicon nitride deposition on the back of a silicon wafer. In brief, the method is characterized in that silicon nitride is added to serve as a protective layer after a metal front insulating layer is subjected to polarization mode dispersion (PMD) deposition, and back scuffing and small granules are effectively reduced; the silicon wafer is turned back so as to enter to a common plasma enhanced chemical vapor deposition (PECVD) cavity so as to deposit low-temperature silicon nitride (less than 450 DEG C); and dry etching is carried out to remove a superficial silicon nitride film after film formation is finished, chemical mechanical polishing (CMP) is reutilized to remove an oxidation film with a certain thickness, and finally an oxidation film with a certain thickness is added according to requirements.
Description
Technical field
The present invention relates to a kind of special integrated approach, particularly relate to a kind of silicon chip back side silicon nitride growing method be integrated in front road technique.
Background technology
Current semiconductor technology presents development in pluralism, while having introduced a large amount of new material, inevitably brings cross pollution to actual production, wherein to semiconductor device the most responsive be the pollution of metallic element.In order at utmost reduce risks, most semiconductor production factory can adopt dust free room subregion, device class, and strengthens the intensity of silicon chip back side cleaning.Wherein the cost of Wafer Backside Cleaning and effect are very significant, and 12 cun of therefore substantially all semiconductor production factories all can be added in it in production procedure.
Because metal ion can be diffused in silicon single crystal; wet-cleaned can peel off certain thickness silicon usually; but the side effect that repeatedly wet treatment brings is that silicon chip back side is uneven, roughness increases, and can affect the aligning of follow-up high accuracy photoetching process and weaken back side vacuum suction effect.Therefore before wet treatment, increase one deck silicon nitride at silicon chip back side and just seem particularly important.
Limit by current equipment, not the cavity of growth back side silicon nitride silicon separately.Stove technique then can be deposited on silicon chip positive and negative simultaneously and temperature is high.
Summary of the invention
The invention discloses a kind of silicon chip back side silicon nitride growing method be integrated in front road technique, in order to solve in prior art not the cavity of growth back side silicon nitride silicon separately, adopt stove technique then can be deposited on silicon chip positive and negative simultaneously, and the problem that technological temperature is high.
Above-mentioned purpose of the present invention is achieved through the following technical solutions:
Be integrated in the silicon chip back side silicon nitride growing method in front road technique, wherein,
Step a: at the upper surface depositing metal insulating barrier of silicon chip;
Step b: grow front protecting layer on metal dielectric layer;
Step c: turn over after silicon chip, deposit low temperature silicon nitride layer on the lower surface of silicon chip, to play the effect of physical protection layer;
Steps d: dry etching removes front protecting layer, carries out cmp afterwards and removes certain thickness metal dielectric layer.
Be integrated in the silicon chip back side silicon nitride growing method in front road technique as above, wherein, be also included on metal dielectric layer after steps d and grow layer oxide film.
Be integrated in the silicon chip back side silicon nitride growing method in front road technique as above, wherein, the front protecting layer in step b is silicon nitride layer.
Be integrated in the silicon chip back side silicon nitride growing method in front road technique as above, wherein, the thickness of the metal dielectric layer in step a is 6000A ~ 10000A.
Be integrated in the silicon chip back side silicon nitride grown method in front road technique as above, wherein, the thickness of the front protecting layer in step b is 1000A ~ 2000A.
Be integrated in the silicon chip back side silicon nitride grown method in front road technique as above, wherein, the thickness of the low temperature silicon nitride layer in step c is 500A ~ 5000A.
Be integrated in the silicon chip back side silicon nitride growing method in front road technique as above, wherein, described metal dielectric layer is oxidation film layer.
Be integrated in the silicon chip back side silicon nitride growing method in front road technique as above, wherein, in step c, silicon chip be placed in deposit low temperature silicon nitride layer in plasma enhanced chemical vapor deposition die cavity.
In sum, owing to have employed technique scheme, the present invention's silicon chip back side silicon nitride growing method be integrated in front road technique solves in prior art does not grow up separately at the cavity of silicon chip back side silicon nitride, adopt stove technique then can be deposited on silicon chip positive and negative simultaneously, and the problem that technological temperature is high, utilize existing process equipment, at silicon chip back side low temperature depositing silicon nitride.Be exactly in simple terms after metal front insulation layer (PMD) deposition; chase after long silicon nitride film again and do protective layer; this effectively can reduce the back side and scratch and granule; turn over after silicon chip; enter common plasma enhanced chemical vapor deposition (PECVD) cavity deposit low temperature silicon nitride (<450C); first remove the silicon nitride film on surface with dry etching after film forming; and then utilize cmp (CMP) to remove certain thickness oxide-film, finally chase after long certain thickness oxide-film by demand.
Accompanying drawing explanation
Fig. 1 is the structural representation after the present invention is integrated in the upper surface depositing metal insulating barrier of the silicon chip of the silicon chip back side silicon nitride growing method in front road technique;
Fig. 2 be the present invention be integrated in the silicon chip back side silicon nitride growing method in front road technique metal dielectric layer on grow the structural representation after front protecting layer;
Fig. 3 be the present invention be integrated in the silicon chip of the silicon chip back side silicon nitride growing method in front road technique lower surface on structural representation after deposit low temperature silicon nitride layer;
Fig. 4 is the structural representation after the present invention is integrated in the removal front protecting layer of the silicon chip back side silicon nitride growing method in front road technique and metal dielectric layer;
Fig. 5 is the structural representation grown on metal dielectric layer after oxide-film that the present invention is integrated in silicon chip back side silicon nitride growing method in front road technique.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
Be integrated in the silicon chip back side silicon nitride growing method in front road technique, wherein,
Fig. 1 is the structural representation after the present invention is integrated in the upper surface depositing metal insulating barrier of the silicon chip of the silicon chip back side silicon nitride growing method in front road technique, refer to Fig. 1, step a: at the upper surface depositing metal insulating barrier 102 of silicon chip 101, unlike the prior art, the thickness of the metal dielectric layer 102 of this method deposit will exceed the thickness 1000 ~ 2000A of prior art;
The thickness of the metal dielectric layer 102 in step a of the present invention is 6000A ~ 10000A.
Described metal dielectric layer 102 in the present invention is oxidation film layer.
Fig. 2 be the present invention be integrated in the silicon chip back side silicon nitride growing method in front road technique metal dielectric layer on grow the structural representation after front protecting layer, refer to Fig. 2, step b: grow front protecting layer 103 on metal dielectric layer 102, makes front protecting layer 103 be covered completely by metal dielectric layer 102 upper surface;
Front protecting layer 103 in step b of the present invention is silicon nitride layer.
The thickness of the front protecting layer 103 in step b of the present invention is 1000A ~ 2000A.
Fig. 3 be the present invention be integrated in the silicon chip of the silicon chip back side silicon nitride growing method in front road technique lower surface on structural representation after deposit low temperature silicon nitride layer, refer to Fig. 3, step c: turn over after silicon chip 101, deposit low temperature silicon nitride layer 201 on the lower surface of silicon chip 101, to play the effect of physical protection layer, the damage for silicon chip 101 back side in subsequent technique effectively can be reduced;
In step c of the present invention, silicon chip 101 is placed in deposit low temperature silicon nitride layer 201(<450C in plasma enhanced chemical vapor deposition die cavity), plasma enhanced chemical vapor deposition die cavity is die cavity comparatively common in prior art.
The thickness of the low temperature silicon nitride layer 201 in step c of the present invention is 500A ~ 5000A, and the thickness of low temperature silicon nitride layer 201 determines according to the number of times of wet etching, and a general back side wet method can peel off the low temperature silicon nitride layer 201 of about 200A.
Fig. 4 is the structural representation after the present invention is integrated in the removal front protecting layer of the silicon chip back side silicon nitride growing method in front road technique and metal dielectric layer; refer to Fig. 4; rapid d: dry etching removes front protecting layer 103, carries out cmp afterwards and removes certain thickness metal dielectric layer 102.
Fig. 5 is the structural representation grown on metal dielectric layer after oxide-film that the present invention is integrated in silicon chip back side silicon nitride growing method in front road technique, refers to Fig. 5, is also included on metal dielectric layer 102 and grows layer oxide film 104 after steps d.
Further, after steps d, also can not grow oxide-film 104, whether grow and decide according to the requirement of subsequent technique.
In sum, the silicon chip back side silicon nitride growing method that the present invention is integrated in front road technique utilizes existing process equipment, at silicon chip back side low temperature depositing silicon nitride.Be exactly in simple terms after metal front insulation layer (PMD) deposition; chase after long silicon nitride film again and do protective layer; this effectively can reduce the back side and scratch and granule; turn over after silicon chip; enter common plasma enhanced chemical vapor deposition (PECVD) cavity deposit low temperature silicon nitride (<450C); first remove the silicon nitride film on surface with dry etching after film forming; and then utilize cmp (CMP) to remove certain thickness oxide-film, finally chase after long certain thickness oxide-film by demand.
Be described in detail specific embodiments of the invention above, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, equalization conversion done without departing from the spirit and scope of the invention and amendment, all should contain within the scope of the invention.
Claims (3)
1. be integrated in the silicon chip back side silicon nitride growing method in front road technique, it is characterized in that,
Step a: at the upper surface depositing metal insulating barrier of silicon chip, described metal dielectric layer is oxidation film layer, and the thickness of described metal dielectric layer is
Step b: grow front protecting layer on metal dielectric layer, the thickness of described front protecting layer is
described front protecting layer is silicon nitride layer;
Step c: turn over after silicon chip, deposit low temperature silicon nitride layer on the lower surface of silicon chip, the thickness of low temperature silicon nitride layer is
to play the effect of physical protection layer;
Steps d: dry etching removes front protecting layer, carries out cmp afterwards and removes certain thickness metal dielectric layer.
2. the silicon chip back side silicon nitride growing method be integrated in front road technique according to claim 1, is characterized in that, be also included on metal dielectric layer and grow layer oxide film after steps d.
3. the silicon chip back side silicon nitride growing method be integrated in front road technique according to claim 1, is characterized in that, in step c, silicon chip is placed in deposit low temperature silicon nitride layer in plasma enhanced chemical vapor deposition die cavity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110183456.2A CN102420131B (en) | 2011-07-01 | 2011-07-01 | Silicon wafer back silicon nitride growth method integrated in FEOL (front end of line) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110183456.2A CN102420131B (en) | 2011-07-01 | 2011-07-01 | Silicon wafer back silicon nitride growth method integrated in FEOL (front end of line) |
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| Publication Number | Publication Date |
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| CN102420131A CN102420131A (en) | 2012-04-18 |
| CN102420131B true CN102420131B (en) | 2015-06-17 |
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| CN201110183456.2A Active CN102420131B (en) | 2011-07-01 | 2011-07-01 | Silicon wafer back silicon nitride growth method integrated in FEOL (front end of line) |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103523738B (en) * | 2012-07-06 | 2016-07-06 | 无锡华润上华半导体有限公司 | Micro electro mechanical system sheet and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1181617A (en) * | 1996-10-24 | 1998-05-13 | 佳能株式会社 | Production of electronic device |
| CN1747136A (en) * | 2004-09-10 | 2006-03-15 | 中芯国际集成电路制造(上海)有限公司 | Corrosion of silicon nitride layer with single-chip substrate as back for IC integrated circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5444473A (en) * | 1977-09-16 | 1979-04-07 | Toshiba Corp | Nanufacture for semiconductor device |
| US6127070A (en) * | 1998-12-01 | 2000-10-03 | Advanced Micro Devices, Inc. | Thin resist with nitride hard mask for via etch application |
| JP2004128037A (en) * | 2002-09-30 | 2004-04-22 | Trecenti Technologies Inc | Method for manufacturing semiconductor device |
| US7083495B2 (en) * | 2003-11-26 | 2006-08-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Advanced process control approach for Cu interconnect wiring sheet resistance control |
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- 2011-07-01 CN CN201110183456.2A patent/CN102420131B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1181617A (en) * | 1996-10-24 | 1998-05-13 | 佳能株式会社 | Production of electronic device |
| CN1747136A (en) * | 2004-09-10 | 2006-03-15 | 中芯国际集成电路制造(上海)有限公司 | Corrosion of silicon nitride layer with single-chip substrate as back for IC integrated circuit |
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| CN102420131A (en) | 2012-04-18 |
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