CN102413269B - Video processing method and circuit applying method - Google Patents
Video processing method and circuit applying method Download PDFInfo
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Abstract
The invention discloses a video processing method and a circuit applying the method, and the method and circuit disclosed by the invention are used for amplifying and strengthening the acuity for input video data. The video processing method comprises the following steps: firstly, respectively storing N pixel row data in the input video data temporarily into N linear buffer devices, wherein N is a natural number; then referring to the N pixel row data stored temporarily in the N linear buffer devices and the N+1 input pixel row data input in real time, generating I amplified pixel row data through interpolation, wherein I is a natural number greater than N; then referring to the N pixel row data stored temporarily in the N linear buffer devices and the N+1 input pixel row data, and generating I amplified smooth pixel row data; and finally acquiring I sharpening pixel row data according to the mixing of the I amplified pixel row data and the I amplified smooth pixel row data.
Description
Technical field
The present invention relates to a kind of video processing circuits, and be particularly related to a kind of video processing circuits of carrying out video amplifier operation and video smoothing operation with reference to temporary pixel data in identical linear buffer (Line Buffer) that comprises.
Background technology
In the prior art, video sharpness (Sharpness) intensifier circuit exists, and has been widely used in many video processing applications occasions.In general, video sharpness intensifier circuit extracts the radio-frequency component in original video according to original video, and the high frequency video components extracting is superposeed back in original video, to reach the technique effect of the video sharpness that strengthens original video.Yet existing video sharpness enhancing technology need be used a large amount of linear buffer device (Line Buffer) to keep in original video, just can complete the operation of calculating high frequency video components.Accordingly, how to design and can in the situation that linear buffer usage quantity is less, carry out the video processing circuits that video sharpness strengthens operation, one of direction of constantly endeavouring for industry.
Summary of the invention
The present invention relates to a kind of video processing circuits, the video amplifier circuit that its application be arranged in parallel and video smoothing (Smooth) circuit, according to temporary original video data in identical linear buffer, complete respectively the operation of video amplifier and the operation of video amplifier and smoothing.The video processing circuits the present invention relates to is application mix circuit also, according to video data and the video data after amplification and smoothing after amplifying, finds out radio-frequency component data and sharp keenization number of lines of pixels certificate.Accordingly, than conventional video acutance intensifier circuit, the video processing circuits the present invention relates to has linear buffer device quantity and the lower-cost advantage of the use of needing.
According to an aspect of the present invention, a kind of video processing circuits is proposed, in order to inputting video data is amplified and acutance enhancing operation.Video processing circuits comprises N linear buffer device, video amplifier circuit, video smoothing circuit and mixing (Blending) circuit, and N is natural number.N linear buffer device is respectively in order to N pixel column (Row) data in temporary inputting video data.Video amplifier circuit, with reference to N number of lines of pixels certificate temporary in N linear buffer device and N+1 the number of lines of pixels certificate of inputting in real time, produces I via interpolation (Interpolation) and amplifies number of lines of pixels certificate, and I is the natural number that is greater than N.Video smoothing circuit amplifies smoothing number of lines of pixels certificate with reference to N number of lines of pixels certificate and N+1 input number of lines of pixels temporary in N linear buffer device according to producing I.Hybrid circuit is found out I high-frequency pixels row data according to I amplification number of lines of pixels certificate and I amplification smoothing number of lines of pixels certificate, and is mixed to get the individual sharp keenization number of lines of pixels certificate of I according to I amplification number of lines of pixels certificate and I high-frequency pixels row data.
According to a further aspect in the invention, a kind of method for processing video frequency is proposed, in order to inputting video data is amplified and acutance enhancing operation.Method for processing video frequency comprises following step.First respectively N number of lines of pixels in temporary inputting video data is according in N linear buffer device, and N is natural number.Then with reference to N number of lines of pixels certificate temporary in N linear buffer device and N+1 of inputting in real time, input number of lines of pixels certificate, via interpolation, produce I amplification number of lines of pixels certificate, I is the natural number that is greater than N.Then with reference to N number of lines of pixels certificate and N+1 input number of lines of pixels temporary in N linear buffer device, according to producing I, amplify smoothing number of lines of pixels certificate.According to I amplification number of lines of pixels certificate and I amplification smoothing number of lines of pixels certificate, be mixed to get I sharp keenization number of lines of pixels certificate afterwards.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and by reference to the accompanying drawings, be described in detail below:
Accompanying drawing explanation
Fig. 1 shows the calcspar according to the video processing circuits of the embodiment of the present invention.
Fig. 2 shows the detailed block diagram of the video amplifier circuit 12 of Fig. 1.
Fig. 3 shows according to the vertical smoothing unit in the video smoothing circuit 14 of the embodiment of the present invention and the detailed block diagram of vertical interpolation unit.
Fig. 4 shows the detailed block diagram according to register, horizontal smoothing unit and horizontal interpolation unit in the video smoothing circuit 14 of the embodiment of the present invention.
Fig. 5 shows the detailed block diagram of the hybrid circuit 16 of Fig. 1.
Fig. 6 shows the flow chart according to the method for processing video frequency of the embodiment of the present invention.
Fig. 7 shows the detail flowchart of the step (c) in Fig. 6.
Fig. 8 shows the detail flowchart of the step (b) in Fig. 6.
Fig. 9 shows the detail flowchart of the step (d) in Fig. 7.
Main element symbol description
1: video processing circuits 12: video amplifier circuit
14: video smoothing circuit 16: hybrid circuit
12a, 14c: vertical interpolation unit 12b, 14d: horizontal interpolation unit
Mua_1~Mua_N+1, Mub_1~Mub_M, Muc1~Muc3, Mua ' _ 1~Mua ' _ N+1, Mud1~Mud3, Mub ' _ 1~Mub ' _ M: multiplier
Ada, Adb, Adc, Ada ', Add, Adb ': adder
14a_1~14a_N+1: vertical smoothing unit
14b_1~14b_M: horizontal smoothing unit
16a: arithmetic element 16b: mixed cell
16c: visual classification unit 16d: look-up table unit
Embodiment
The video processing circuits application of the embodiment of the present invention can share video amplifier circuit and the smoothing circuit of linear buffer and find out high frequency video data.
Please refer to Fig. 1, it illustrates the calcspar according to the video processing circuits of the embodiment of the present invention.Video processing circuits 1 is in order to amplify inputting video data and acutance enhancing operation.For instance, inputting video data comprises a plurality of number of lines of pixels certificates, and each number of lines of pixels is according to comprising a plurality of pixel datas of input successively.Video processing circuits 1 comprise N linear buffer device LB1, LB2 ..., LBN, video amplifier circuit 12, video smoothing circuit 14 and hybrid circuit 16, wherein N is natural number.
Continuous N pixel column (Pixel Row) data PR_1, PR_2 in the temporary inputting video data of linear buffer device LB1~LBN ..., PR_N, for video amplifier circuit 12, video smoothing circuit 14 and hybrid circuit 16, carry out corresponding operation, wherein each N number of lines of pixels comprises M pixel data according to PR_1~PR_N, and M is greater than 1 natural number.For instance, on an operating time point, video processing circuits 1 receives a number of lines of pixels of inputting in real time, and according to PR_N+1, linear buffer device is temporarily stored in previous N number of lines of pixels in order according to after PR_N, PR_N_1, PR_N_2..., PR_1.In an operational instances, N equals 5, and the number of lines of pixels of input corresponds to the 6th number of lines of pixels certificate in inputting video data according to PR_N+1 in real time, accordingly, the number of lines of pixels storing in linear buffer device LB1~LBN (N=5) according to be respectively correspond to the 1st in inputting video data, the 2nd ..., the 5th number of lines of pixels certificate.
Please refer to Fig. 2, it shows the detailed block diagram of the video amplifier circuit 12 of Fig. 1.Video amplifier circuit 12 with reference to number of lines of pixels temporary in linear buffer LB1~LBN according to PR_1~PR_N and N+1 number of lines of pixels according to PR_N+1 obtain I amplification number of lines of pixels according to PLR_1, PLR_2 ..., PLR_I, wherein I is the natural number that is greater than N+1.For instance, video amplifier circuit 12 comprises vertical interpolation unit 12a and horizontal interpolation unit 12b.
Video smoothing circuit 14 with reference to N number of lines of pixels temporary in linear buffer LB1~LBN according to PR_1~PR_N and N+1 number of lines of pixels according to PR_N+1, produce I amplification smoothing number of lines of pixels according to PLSR_1, PLSR_2 ..., PLSR_I.For instance, video smoothing circuit 14 comprises N+1 vertical smoothing unit, a M horizontal smoothing unit, vertical interpolation unit, horizontal interpolation unit and a plurality of register.Next will give an example, the operation of each unit in video smoothing circuit 14 will be described further.
Please refer to Fig. 3, it illustrates according to the vertical smoothing unit in the video smoothing circuit 14 of the embodiment of the present invention and the detailed block diagram of vertical interpolation unit.Each N vertical smoothing unit 14a_1,14a_2 ..., 14a_N+1 with reference to N+1 number of lines of pixels X the number of lines of pixels certificate according to correspondence in PR_1~PR_N+1, with produce vertical smoothing number of lines of pixels according to PVSR_1, PVSR_2 ..., PVSR_N+1, X is greater than 1 natural number.For instance, the vertical smoothing unit 14a_1~14a_N+1 of each N+1 comprise X multiplier Muc1, Muc2 ..., MucX and adder Adc, in order to X the weighting parameters with reference to corresponding, each number of lines of pixels of correspondence, according to being weighted addition, is operated to realize aforementioned vertical smoothing.For instance, numerical value X equals 3, and vertical smoothing unit 14a_1~14a_N+1 respectively with reference to three corresponding number of lines of pixels according to PR_1~PR_3, PR_2~PR_4, PR_3~PR_5 ..., PR_N~1 is to PR_N+1, produces corresponding vertical smoothing number of lines of pixels according to PVSR_1 to PVSR_N+1.
Vertical interpolation unit 14c has similar operation to the vertical interpolation unit 12a in video amplifier circuit 12, in order to carry out vertical direction interpolative operation according to vertical smoothing number of lines of pixels according to PVSR_1~PVSR_N+1, with produce I vertical amplify smoothing number of lines of pixels according to PLVSR_1, PLVSR_2 ..., PLVSR_N.For instance, vertical interpolation unit 14c comprise multiplier Mua ' _ 1, Mua ' _ 2 ..., Mua ' _ N+1 and adder Ada ', in order to reference to weighting parameters a ' _ 1, a ' _ 2 ..., a ' _ N+1 is weighted addition to each vertical smoothing number of lines of pixels of amplifying of correspondence according to PLVSR_1~PLVSR_N+1, to realize aforementioned vertical interpolation operation.
Please refer to Fig. 4, it illustrates the detailed block diagram according to register, horizontal smoothing unit and horizontal interpolation unit in the video smoothing circuit 14 of the embodiment of the present invention.For instance, video smoothing circuit 14 comprise M-1 register R ' _ 1, R ' _ 2 ..., R ' _ M-1, it stores respectively each N+1 vertical amplification smoothing number of lines of pixels according to the pixel data of the M-1 in PLVSR_1~PLVSR_N+1, and each N+1 the vertical smoothing number of lines of pixels of amplifying is the pixel data of inputting in real time according to M pixel data in PLVSR_1~PLVSR_N+1.M pixel data of the pixel data that horizontal smoothing unit and horizontal interpolation unit are deposited in reference register R ' 1 to R ' _ M-1 and input in real time carries out corresponding smoothing and interpolation operates.Due to register R ' _ 1~R ' _ M-1, horizontal smoothing unit and horizontal interpolation unit for each N+1 vertical amplify smoothing number of lines of pixels according to PLVSR_1~PLVSR_N+1 performed be operating as identical in fact, next, only with aforementioned circuit for s vertical amplify smoothing number of lines of pixels according to PLVSR_s performed be operating as example, operation to aforementioned circuit is further described, and s is the natural number that is less than or equal to N+1.
When inputing to the signal of register R ' 1 to R ' _ M-1, be while vertically amplifying smoothing number of lines of pixels according to PLVSR_s, its deposit respectively vertical amplification smoothing number of lines of pixels according to the 1st in PLVSR_s, the 2nd ..., M-1 pixel data Px_1, Px_2 ..., Px_M-1, vertically amplify smoothing number of lines of pixels and will in the next operating time, be stored in register R ' _ M-1 according to M pixel data Px_M in PLVSR_s.
Each M horizontal smoothing unit 14b_1,14b_2 ..., 14b_M is with reference to Y the pixel data of depositing, produce correspondence horizontal smoothing pixel data PHS_1, a PHS_2 ..., PHS_M, Y is greater than 1 natural number.For instance, Y equals 3, and with M horizontal smoothing unit 14b_M, the pixel data Px_M-1 and the Px_M-Y+1 (being Px_M-2) that in its M pixel data Px_M, register R ' _ M-1 with reference to input in real time and R ' _ M-Y+1 (being R ' _ M-2), deposit carry out smoothing operation, and produce according to this horizontal smoothing pixel data PHS_M.All the other M-1 horizontal smoothing unit 14b_M-1 to 14b_1 carry out the operation similar to horizontal smoothing unit 14b_M, in this, also no longer it are repeated.For instance, each horizontal smoothing unit 14b_1~14b_M comprise Y multiplier Mud1, Mud2 ..., MudY (being Mud3) and adder Add, its in order to reference to corresponding Y weighting parameters d1, d2 ..., dy (being d3), each pixel data to correspondence is weighted addition, to realize out aforementioned levels smoothing operation.
Though only the operation of aforementioned circuit is explained according to the performed example that is operating as of PLVSR_s for s the vertical smoothing number of lines of pixels of amplifying with register R ' 1~R ' M, horizontal smoothing unit 14b1~14b_M in video smoothing circuit 14 and horizontal interpolation unit 14d in aforementioned paragraphs, yet, register R ' 1~R ' M, horizontal smoothing unit 14b_1~14b_M and horizontal interpolation unit 14d can analogize and obtain according to the narration of aforementioned paragraphs according to performed operation for other vertical smoothing number of lines of pixels of amplifying, in this, and no longer it is repeated.Accordingly, video smoothing circuit 14 can obtain I amplification smoothing number of lines of pixels according to PLSR_1~PLSR_I.
Please refer to Fig. 5, it shows the detailed block diagram of the hybrid circuit 16 of Fig. 1.For instance, hybrid circuit 16 comprises arithmetic element 16a and mixed cell 16b.Arithmetic element 16a amplifies number of lines of pixels according to I and according to PLSR_1~PLSR_I, subtracts each other and obtain I high-frequency pixels row data PHP_1~PHP_I with I corresponding amplification smoothing number of lines of pixels according to PLR_1~PLR_I.Mixed cell 16b with reference to I acutance weight (Weight) W1, W2 ..., WI, according to I high-frequency pixels row data PHP_1 and corresponding I, amplify number of lines of pixels and be mixed to get the individual sharp keenization number of lines of pixels of I according to PSR_1~PSR_I according to PLR_1~PLR_I.For instance, mixed cell 16b comprises multiplier, in order to according to corresponding acutance weights W 1~WI, determine high-frequency pixels row data PHP_1~PHP_I with respect to corresponding amplification number of lines of pixels the weight according to PLR_1~PLR_I; And comprise adder, in order to the high-frequency pixels row data PHP_1~PHP_I after weight adjustment is superimposed to corresponding amplification number of lines of pixels according on PLR_1~PLR_I.
In an example, hybrid circuit 16 also comprises visual classification unit 16c and look-up table (Lookup Table, LUT) unit 16d.Visual classification unit 16c judges whether each N+1 number of lines of pixels meets video features condition according to PR_1~PR_N+1, and produce according to this I look-up table control signal LU1, LU2 ..., LUN.For instance, visual classification unit 16c is in order to determine search window (Search Window), with circle, select N number of lines of pixels according to the number of lines of pixels certificate of part in PR_1~PR_N+1, and whether this video features condition is for being corresponded to the condition at the natural edge of object by the number of lines of pixels of circle choosing certificate.Accordingly, visual classification unit 16c can at least be divided into the classification that corresponds to nature edge and the classification that corresponds to non-natural edge according to PR_1~PR_N+1 by number of lines of pixels, and provides control signal LU1~LUN to indicate respectively each number of lines of pixels according to the classification of PR_1~PR_N.
Look-up table unit 16d finds out corresponding acutance weights W 1~WI in response to control signal LU1~LUN according to look-up table.For instance, correspond to the control signal of nature edge classification in response to number of lines of pixels certificate corresponding to indication, this look-up table provides the acutance weight that numerical value is higher accordingly, so that the image content at this natural edge is carried out to high frequency strengthening; The control signal that corresponds to non-natural edge classification in response to number of lines of pixels certificate corresponding to indication, this look-up table provides the acutance weight that numerical value is lower accordingly, to avoid that the content at non-edge in picture is carried out to excessive high frequency strengthening, and affects the quality of picture.
In an operational instances, visual classification unit 16c can according to N+1 number of lines of pixels being selected by circle according in correspond to the pixel data of high gray value (Gray Level) and minimum gray scale value difference make a decision criterion, judge whether these number of lines of pixels certificates of being enclosed choosing correspond to nature edge.When this difference is more than or equal to a critical value, visual classification unit 16c judges that these number of lines of pixels of being enclosed choosing are according to corresponding to nature edge classification; When this difference is less than this critical value, visual classification unit 16c judges that these number of lines of pixels of being enclosed choosing are according to corresponding to non-natural edge classification.In other example, visual classification unit 16c also can, according to by other numerical characteristics of the number of lines of pixels certificate of circle choosing, classify to its corresponding classification.
Please refer to Fig. 6, it illustrates the flow chart according to the method for processing video frequency of the embodiment of the present invention.The method for processing video frequency of the embodiment of the present invention is in order to amplify inputting video data and acutance enhancing operation, and this method for processing video frequency comprises following step.First as step (a), respectively N number of lines of pixels in temporary inputting video data according to PR_1~PR_N in N linear buffer device LB1~LBN.Then as step (b), video amplifier circuit 12 with reference to N number of lines of pixels temporary in N linear buffer device LB1~LBN according to N+1 number of lines of pixels of PR_1~PR_N and in real time input according to PR_N+1, via interpolation, produce I amplification number of lines of pixels according to PLR_1~PLR_I.
Then as step (c), video smoothing circuit 14 with reference to N number of lines of pixels temporary in N linear buffer device according to N+1 number of lines of pixels of PR_1~PR_N and in real time input according to PR_N+1, produce I amplification smoothing number of lines of pixels according to PLSR_1~PLSR_I.As step (d), hybrid circuit 16 amplifies number of lines of pixels according to I and according to PLSR_1~PLSR_I, is mixed to get I sharp keenization number of lines of pixels according to PSR_1~PSR_I according to PLR_1~PLR_I and I amplification smoothing number of lines of pixels afterwards.
Please refer to Fig. 7, it shows the detail flowchart of the step (c) in Fig. 6.For instance, in abovementioned steps (c), also comprise step (c1)~(c4).First as step (c1), N+1 vertically smoothing unit 14a_1~14a_N+1 is with reference to N+1 number of lines of pixels according to the X in RP_1~PR_N+1 number of lines of pixels certificate, and N+1 vertical smoothing number of lines of pixels of generation is according to PVSR_1~PVSR_N+1.Then as step (c2), vertical interpolation unit 14c carries out the operation of vertical direction interpolation according to N+1 vertical smoothing number of lines of pixels according to PVSR_1~PVSR_N+1, to find out I the vertical smoothing number of lines of pixels of amplifying according to PLVSR_1~PLVSR_I.
Then as step (c3), M horizontal smoothing unit 14b_1~14b_M vertically amplifies smoothing number of lines of pixels according to the pixel data of the Y in PLVSR_1~PLVSR_I with reference to each I, produces M horizontal smoothing number of lines of pixels according to PHS_1~PHS_M.Afterwards as step (c4), horizontal interpolation unit 14d carries out the operation of horizontal direction interpolation according to M horizontal smoothing number of lines of pixels according to PHS_1~PHS_M, to find out each I, amplify smoothing number of lines of pixels according to the J in PLVSR_1~PLVSR_M amplification smoothing pixel data, to find out accordingly I, amplify smoothing number of lines of pixels according to PLSR_1~PLSR_I.
Please refer to Fig. 8, it shows the detail flowchart of the step (b) in Fig. 6.For instance, in abovementioned steps (b), also comprise step (b1) and (b2).First as step (b1), vertical interpolation unit 12a carries out the operation of vertical direction interpolation according to N+1 number of lines of pixels according to PR_1~PR_N+1, to find out I the vertical number of lines of pixels certificate of amplifying.Then as step (b2), horizontal interpolation unit 12b according to carrying out the operation of horizontal direction interpolation, amplifies number of lines of pixels according to J in PLR_1~PLR_I amplification pixel data to find out each I according to the individual vertical number of lines of pixels of amplifying of each I.
Please refer to Fig. 9, it shows the detail flowchart of the step (d) in Fig. 7.For instance, in abovementioned steps (d), also comprise step (d1) and (d2).First as step (d1), arithmetic element 16a amplifies number of lines of pixels according to I and according to PLSR_1~PLSR_I, subtracts each other and obtain I high-frequency pixels row data PHP_1~PHP_I with I corresponding amplification smoothing number of lines of pixels according to PLR_1~PLR_I, and it is respectively in order to indicate I to amplify number of lines of pixels according to the radio-frequency component of PLR_1~PLR_I.Then as step (d2), mixed cell 16b, with reference to I acutance weights W 1~WI, is mixed to get I sharp keenization number of lines of pixels according to PSR_1~PSR_I with I corresponding amplification number of lines of pixels according to PLR_1~PLR_I according to I high-frequency pixels row data PHP_1~PHP_I.
In an example, in step (d1) and (d2), also comprise step (d3) and (d4).As step (d3), visual classification unit 16c judges whether each N+1 number of lines of pixels meets video features condition according to PR_1~PR_N+1, and produces according to this I look-up table control signal LU1~LUN.Then as step (d4), look-up table unit 16d determines I acutance weights W 1~WI according to I look-up table control signal LU1~LUN, to amplify number of lines of pixels to I, according to PLR_1~PLR_I, carries out optionally acutance enhancing operation.
Video amplifier circuit and video smoothing circuit that the video processing circuits application of the embodiment of the present invention be arranged in parallel, with according to temporary original video data in identical linear buffer, complete respectively video amplifier operation and video amplifier and smoothing operation.The video processing circuits of the embodiment of the present invention is application mix circuit also, according to video data and the video data after amplification and smoothing after amplifying, finds out radio-frequency component data and sharp keenization number of lines of pixels certificate.Accordingly, with respect to conventional video acutance intensifier circuit, the video processing circuits the present invention relates to has linear buffer device quantity and the lower-cost advantage of the use of needing.
In sum, although the present invention with preferred embodiment exposure as above, yet it is not in order to limit the present invention.Persons of ordinary skill in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various variations and modification.Therefore, protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (6)
1. a video processing circuits, in order to inputting video data is amplified and acutance strengthens operation, described video processing circuits comprises:
N linear buffer device, in order to N number of lines of pixels certificate in temporary described inputting video data, N is natural number respectively;
Video amplifier circuit, with reference to described N number of lines of pixels certificate temporary in described N linear buffer device and N+1 the number of lines of pixels certificate of inputting in real time, produces I via interpolation and amplifies number of lines of pixels certificate, and I is the natural number that is greater than N;
Video smoothing circuit, described N number of lines of pixels certificate and described N+1 input number of lines of pixels certificate with reference to temporary in described N linear buffer device, produce I and amplify smoothing number of lines of pixels certificate; And
Hybrid circuit, in order to find out I high-frequency pixels row data according to described I amplification number of lines of pixels certificate and described I amplification smoothing number of lines of pixels certificate, and be mixed to get I sharp keenization number of lines of pixels certificate according to described I amplification number of lines of pixels certificate and described I high-frequency pixels row data, and
Wherein, described video smoothing circuit comprises:
The vertical smoothing of N+1 unit, described in each described in N+1 vertical smoothing elements reference N number of lines of pixels according to and described N+1 X the number of lines of pixels certificate of inputting in number of lines of pixels certificate, produce vertical smoothing number of lines of pixels certificate, X is greater than 1 natural number; And
Vertical interpolation unit, in order to carry out the operation of vertical direction interpolation according to the individual described vertical smoothing number of lines of pixels certificate of N+1, vertically amplifies smoothing number of lines of pixels certificate to find out I, and wherein described in each, the individual smoothing number of lines of pixels certificate of vertically amplifying of I comprises M pixel data;
M horizontal smoothing unit, with reference to I described in each vertical Y the pixel data amplifying in smoothing number of lines of pixels certificate, produces horizontal smoothing number of lines of pixels certificate, and Y is greater than 1 natural number; And
Horizontal interpolation unit, carries out the operation of horizontal direction interpolation according to M described horizontal smoothing data, with find out described in each I amplify smoothing number of lines of pixels according in J amplification smoothing pixel data;
Wherein, described hybrid circuit comprises:
Arithmetic element, in order to amplify number of lines of pixels according to amplifying smoothing number of lines of pixels certificate with corresponding described I according to described I, subtracts each other and obtains I high-frequency pixels row data, respectively in order to indicate the radio-frequency component of described I amplification number of lines of pixels certificate; And
Mixed cell, with reference to I acutance weight, according to described I high-frequency pixels row data and described I corresponding amplification number of lines of pixels certificate, is mixed to get described I sharp keenization number of lines of pixels certificate.
2. video processing circuits according to claim 1, wherein, described video amplifier circuit comprises:
Vertical interpolation unit, in order to carry out the operation of vertical direction interpolation according to described N number of lines of pixels certificate and described N+1 input number of lines of pixels certificate, to find out I vertical amplification number of lines of pixels certificate; And
Horizontal interpolation unit, in order to according to the vertical number of lines of pixels of amplifying of I described in each according to carrying out the operation of horizontal direction interpolation, with find out described in each I amplify number of lines of pixels according in J amplification pixel data.
3. video processing circuits according to claim 1, wherein, described hybrid circuit also comprises:
Visual classification unit, in order to judge described in each N number of lines of pixels according to and described N+1 input number of lines of pixels certificate whether meet video features condition, and produce according to this I look-up table control signal; And
Look-up table unit, determines described I acutance weight according to described I look-up table control signal respectively, to amplify number of lines of pixels to described I, according to carrying out optionally acutance, strengthens operation.
4. a method for processing video frequency, in order to inputting video data is amplified and acutance strengthens operation, described method for processing video frequency comprises:
N number of lines of pixels in temporary described inputting video data is according in N linear buffer device respectively, and N is natural number;
N+1 the input number of lines of pixels certificate with reference to described N number of lines of pixels certificate temporary in described N linear buffer device and real-time input, produces I amplification number of lines of pixels certificate via interpolation, and I is the natural number that is greater than N;
Described N number of lines of pixels certificate and described N+1 input number of lines of pixels certificate with reference to temporary in described N linear buffer device, produce I and amplify smoothing number of lines of pixels certificate; And
According to described I amplification number of lines of pixels certificate and described I amplification smoothing number of lines of pixels certificate, be mixed to get I sharp keenization number of lines of pixels certificate; And
Wherein, produce in described I step of amplifying smoothing number of lines of pixels certificate and also comprise:
X the number of lines of pixels certificate with reference in described N number of lines of pixels certificate and described N+1 input number of lines of pixels certificate, produces N+1 vertically smoothing number of lines of pixels certificate, and X is greater than 1 natural number; And
According to described N+1 vertical smoothing number of lines of pixels, according to carrying out the operation of vertical direction interpolation, to find out I, vertically amplify smoothing number of lines of pixels certificate;
With reference to I described in each vertical Y the pixel data amplifying in smoothing number of lines of pixels certificate, produce M horizontal smoothing number of lines of pixels certificate, Y is greater than 1 natural number; And
According to described M horizontal smoothing data, carry out the operation of horizontal direction interpolation, with find out described in each I amplify smoothing number of lines of pixels according in J amplification smoothing pixel data,
Wherein, the step that is mixed to get described I sharp keenization number of lines of pixels certificate also comprises:
According to described I amplification number of lines of pixels, according to described I the amplification smoothing number of lines of pixels certificate with corresponding, subtract each other and obtain I high-frequency pixels row data, respectively the radio-frequency component in order to indicate described I to amplify number of lines of pixels certificate; And
With reference to I acutance weight, according to described I high-frequency pixels row data and described I corresponding amplification number of lines of pixels certificate, be mixed to get described I sharp keenization number of lines of pixels certificate.
5. method for processing video frequency according to claim 4, wherein, produces described I step of amplifying number of lines of pixels certificate and also comprises:
According to described N number of lines of pixels certificate and described N+1 input number of lines of pixels certificate, carry out the operation of vertical direction interpolation, to find out I vertical amplification number of lines of pixels certificate; And
According to the vertical number of lines of pixels of amplifying of I described in each according to carrying out the operation of horizontal direction interpolation, with find out described in each I amplify number of lines of pixels according in J amplification pixel data.
6. method for processing video frequency according to claim 4, wherein, the step that is mixed to get described I sharp keenization number of lines of pixels certificate also comprises:
Judge described in each N number of lines of pixels according to and described N+1 input number of lines of pixels certificate whether meet video features condition, and produce according to this I look-up table control signal;
According to described I look-up table control signal, determine described I acutance weight, to amplify number of lines of pixels to described I, according to carrying out optionally acutance, strengthen operation.
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