CN102412298A - Semiconductor Element And Manufacturing Method Thereof - Google Patents

Abstract

The present invention provides a semiconductor element and a method for manufacturing the semiconductor element. The semiconductor element includes: a second semiconductor layer including first columns of the first conductivity type and second pillars alternately arranged along the main surface of the first semiconductor layer. The second pillar of the second conductivity type; the first control electrode is buried in the inside of the groove provided from the surface of the second semiconductor layer to the direction of the first semiconductor layer; and the second control electrode is arranged on the second semiconductor layer , and connected to the first control electrode. On the surface of the second semiconductor layer except for the part covered by the second control electrode, a first semiconductor region of the second conductivity type is arranged, and on the surface of the first semiconductor region, selectively arranged and controlled by the second control electrode The surface of the covered second semiconductor layer is separated by a second semiconductor region of the first conductivity type. In addition, a third semiconductor region of the second conductivity type adjacent to the second semiconductor region is selectively provided on the surface of the first semiconductor region.

Description

Semiconductor element and method for manufacturing same

This application is based on and claims priority from prior Japanese Patent Application No. 2010-210476 filed on September 21, 2010, the entire contents of which are hereby incorporated by reference.

technical field

Embodiments of the present invention relate to a semiconductor element and a method for manufacturing the semiconductor element.

Background technique

Power semiconductor components such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor, Insulated Gate Bipolar Transistor) have high-speed switching (switching) characteristics, tens to hundreds of volts ( V) reverse blocking voltage (blocking voltage) (withstand voltage), which is widely used in power conversion and control of household appliances, communication equipment, vehicle motors, etc. Furthermore, in order to improve the efficiency of these devices and reduce power consumption, semiconductor elements are required to have characteristics of high withstand voltage and low on-resistance. For example, in a semiconductor device having a superjunction structure in which p-type and n-type semiconductor layers are alternately arranged, high withstand voltage and low on-resistance can be simultaneously realized.

However, there is a problem that when a bias voltage is applied to the superjunction structure, the capacitance of the pn junction decreases sharply, and the output capacitance of the semiconductor element greatly changes. That is, the semiconductor element having a super junction structure has high switching noise depending on the output capacitance. Therefore, there is a need for a semiconductor element having a super-junction structure capable of increasing output capacitance and reducing switching noise.

Contents of the invention

Embodiments of the present invention provide a semiconductor element having a super junction structure capable of increasing output capacitance and reducing switching noise, and a method of manufacturing the semiconductor element.

The semiconductor element according to the embodiment of the present invention includes: a second semiconductor layer including first columns of the first conductivity type and second columns of the second conductivity type alternately arranged in a direction along the main surface of the first semiconductor layer; a first control electrode buried in a trench provided from the surface of the second semiconductor layer toward the first semiconductor layer; and a second control electrode provided on the second semiconductor layer, and connected to the first control electrode. On the surface of the second semiconductor layer except the portion covered by the second control electrode, a first semiconductor region of the second conductivity type is provided, and on the surface of the first semiconductor region, selectively A second semiconductor region of the first conductivity type spaced apart from the surface of the second semiconductor layer covered by the second control electrode. In addition, a third semiconductor region of the second conductivity type adjacent to the second semiconductor region is selectively provided on the surface of the first semiconductor region.

According to the embodiments of the present invention, it is possible to provide a semiconductor element having a super junction structure capable of increasing output capacitance and reducing switching noise, and a method of manufacturing the semiconductor element.

Description of drawings

FIG. 1 is a schematic diagram showing a semiconductor element according to a first embodiment. FIG. 1( a ) is a perspective view showing the structure of the Ia-Ia cross section, and FIG. 1( b ) is a plan view showing the arrangement of the gate electrodes.

FIG. 2 is a graph showing voltage-capacitance characteristics of the semiconductor element of the first embodiment.

3(a) to 8(b) are cross-sectional views schematically showing the manufacturing process of the semiconductor element of the first embodiment. In Fig. 3 (a) ~ Fig. 8 (b), (a) of each figure represents the structure of the Ia-Ia cross section of Fig. 1 (b), and (b) of each figure represents the IVb-IVb cross section of Fig. 1 (b) Structure.

9 is a perspective view schematically showing the structure of a semiconductor element according to a modified example of the first embodiment.

10 is a perspective view schematically showing the structure of a semiconductor element according to another modified example of the first embodiment.

11 is a plan view showing the arrangement of gate electrodes in a modified example of the first embodiment.

FIG. 12 is a schematic diagram showing a semiconductor element having the gate electrode shown in FIG. 11( a ). FIG. 12( a ) is a perspective view schematically showing the structure of a semiconductor element, and FIG. 12( b ) is a schematic view showing the structure of the XIIb-XIIb cross section.

FIG. 13 is a schematic diagram showing the structure of a semiconductor element according to the second embodiment. FIG. 13( a ) is a plan view showing part of the chip surface of the semiconductor element except for the source electrode and the interlayer insulating film. Fig. 13(b) is a perspective view schematically showing the structure of a semiconductor element.

FIG. 14 is a perspective view schematically showing a semiconductor element of a comparative example.

Detailed ways

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in the following embodiments, the same reference numerals are assigned to the same parts in the drawings, and detailed descriptions of these parts are appropriately omitted, and different parts are appropriately described. The first conductivity type is n-type and the second conductivity type is p-type for description, but the first conductivity type may be p-type and the second conductivity type may be n-type.

(first embodiment)

FIG. 1 is a schematic diagram showing a semiconductor element 100 according to this embodiment. FIG. 1( a ) is a perspective view showing a cross-sectional structure, and FIG. 1( b ) is a plan view showing the arrangement of gate electrodes 12 and 15 . FIG. 1(a) shows the state in which the interlayer insulating film 23 and the source electrode 19 are removed in order to show the arrangement relationship between the gate electrodes 12 and 15, the n-type source region 7 and the p ⁺ contact region 8. (Refer to Figure 8).

As shown in Figure 1 (a), the semiconductor element 100 includes: the n-type drain layer 2 as the first semiconductor layer; the drift layer 3 as the second semiconductor layer; the gate electrode 12 as the first control electrode, buried Inside the trench 13 provided from the surface of the drift layer 3 toward the n-type drain layer; and the gate electrode 15 as the second control electrode is provided on the drift layer 3 .

Drift layer 3 includes n-type pillars 4 as first pillars and p-type pillars 5 as second pillars, which are alternately arranged along the main surface 2 a of n-type drain layer 2 .

Gate electrode 12 is buried in trench 13 via gate insulating film 11 as a first insulating film provided on the inner surface of trench 13 .

The gate electrode 15 is provided on the drift layer 3 via a gate insulating film 14 serving as a second insulating film provided on the surface of the drift layer 3 .

A p-type base region 6 serving as a first semiconductor region is provided on a portion of the surface of the drift layer 3 other than the portion covered by the gate electrode 15 . However, as shown in FIG. 1 , the outer edge 6 a of the p-type base region 6 along the gate electrode 15 may extend below the gate electrode 15 .

Furthermore, an n-type source region 7 serving as a second semiconductor region is provided on the surface of the p-type base region 6 . N-type source region 7 is provided at a distance from the surface of drift layer 3 covered by gate electrode 15 .

Furthermore, a p ⁺ contact region 8 serving as a third semiconductor region is adjacent to the n-type source region 7 and is selectively provided on the surface of the p-type base region 6 . N-type source region 7 and p ⁺ contact region 8 are electrically connected to unshown source electrode 19 .

In the semiconductor element 100 of the present embodiment, when a gate voltage is applied to the gate electrode 12 buried in the trench 13, the inversion channel formed at the interface between the p-type base region 6 and the gate insulating film 11 , the drain current can flow between the drain electrode as the first main electrode electrically connected to the n-type drain layer 2 and the source electrode 19 as the second main electrode.

On the other hand, in the gate electrode 15 provided on the drift layer 3, as ^shown in FIG. ground setting. Thus, it is possible to obtain a structure in which, for example, even if an inversion channel is formed at the interface between the diffusion portion 6a of the p-type base region 6 formed below the gate electrode 15 and the gate insulating film 14, the drain current does not flow. to below the gate electrode 15. Furthermore, it is possible to prevent the drain current from concentrating on the gate electrode 15 because the threshold voltage of the inversion channel formed below the gate electrode 15 is reduced.

FIG. 1( b ) is a plan view illustrating an arrangement relationship between the gate electrodes 12 and 15 , and the n-type column 4 and the p-type column 5 in the semiconductor element 100 . The front cross-sectional structure of the perspective view shown in FIG. 1( a ) schematically shows the Ia-Ia cross-section in FIG. 1( b ).

For example, n-type columns 4 and p-type columns 5 can be provided in stripes extending in a direction along main surface 2 a of drain layer 2 . Moreover, as shown in FIG. 1(a) and (b), the gate electrode 12 can be arranged in the trench 13 formed on the surface of the n-type column 4 along the extending direction of the n-type column 4 and the p-type column 5. .

The gate electrode 15 can be provided in a ladder shape that connects adjacent gate electrodes 12 in a direction intersecting with the extending direction of the n-type column 4 and the p-type column 5 . Furthermore, drift layer 3 covered by gate electrode 15 includes a part of p-type column 5 .

As shown in FIG. 1( b ), the gate electrodes 15 are arranged so that their positions are alternately shifted in the direction perpendicular to the direction in which the p-type pillars 5 extend.

FIG. 2 is a graph conceptually showing the voltage-capacitance characteristics of the semiconductor element 100 and the semiconductor element 600 of the comparative example shown in FIG. 14 . The vertical axis represents the capacitance value C, and the horizontal axis represents the source-drain voltage V _ds .

C _ds shown in FIG. 2 is the source-drain capacitance of the semiconductor element 100 , C _gd1 is the gate-drain capacitance of the semiconductor element 100 , and C _gd2 is the gate-drain capacitance of the semiconductor element 600 of the comparative example.

For example, C _ds decreases as V _ds becomes higher, and becomes smaller sharply in the region A shown in FIG. 2 . The reduction of C _ds in this A region corresponds to the fact that at the pn junction between the n-type column 4 and the p-type column 5, the depletion layers extended in the n-type column 4 and the p-type column 5, respectively, are connected, And the drift layer 3 is depleted. Furthermore, when the depletion layer spreads over the entire drift layer 3 , C _ds approaches a minimum value, and then tends to gradually decrease with an increase in V _ds .

On the other hand, C _gd1 decreases as V _ds becomes higher and saturates when V _ds moves to the A region. After that, C _gd1 tends to increase slowly with respect to the rise of V _ds .

C _gd1 is the capacitance between the bottom of the gate electrode 12 buried in the trench 13 and the drain electrode 17 . When V _ds is applied between the source and drain, as the depletion layer expands from the p-type base region 6 and the pn junction between the p-type pillar 5 and n-type pillar 4 to the n-type pillar 4 , C _gd1 decreases.

For example, in the semiconductor device 600 shown in FIG. 14 , when V _ds is applied until the depletion layer expands in the n-type column 4 and the p-type column 5 and the drift layer 3 is substantially depleted as a whole, C _gd2 changes at a relatively large rate. reduce. After that, the expansion of the depletion layer of the drift layer 3 slows down, and C _gd2 tends to decrease slowly with the increase of V _ds .

In contrast, in the semiconductor element 100 , the gate electrode 15 is provided on the drift layer 3 , and the p-type base region 6 is not formed under the gate electrode 15 . Therefore, when the p-type column 5 under the gate electrode 15 is depleted, a part of the gate electrode 15 facing the drain layer 2 via the p-type column 5 faces the drain layer 2 via the depletion layer. Also, a part of the gate electrode 15 again contributes to C _gd1 , so that the reduced C _gd1 temporarily exhibits a tendency to increase as V _ds rises.

The output capacitance of the semiconductor element 100 is the sum of the source-drain capacitance C _ds and the gate-drain capacitance C _gd1 . For example, assuming that the semiconductor element 100 differs from the semiconductor element 600 in the presence or absence of the gate electrode 15 , it can be considered that C _ds of the semiconductor element 100 is approximately equal to the source-drain capacitance of the semiconductor element 600 . Therefore, since C _gd1 is greater than C _gd2 , the output capacitance of the semiconductor element 100 is greater than the output capacitance of the semiconductor element 600 . After the drain voltage Vds rises and Cds decreases significantly, the relative difference in output capacitance further increases.

For example, the change amount (dV/dt) of the drain voltage when the semiconductor elements 100 and 600 perform switching operations is inversely proportional to the output capacitance. Therefore, the amount of change in the drain voltage of the semiconductor element 100 is smaller than the amount of change in the drain voltage of the semiconductor element 600 . Also, since the switching noise is proportional to the rate of change of the drain voltage, the noise of the semiconductor element 100 is lower than that of the semiconductor element 600 .

That is, the semiconductor element 100 has a configuration in which the gate electrode 15 is provided on the drift layer 3 and the p-type base region 6 is not provided below the gate electrode 15 . Thereby, the gate-drain capacitance C _gd1 can be increased, and switching noise can be reduced.

In the semiconductor element 600 shown in FIG. 14, for example, by increasing the protruding amount ΔG of the lower portion of the gate electrode 12 toward the drain layer 2 from the boundary between the p-type base region 6 and the n-type column 4, the gate electrode 12 can also be made larger. The capacitance C _gd2 between the electrode and the drain increases.

However, if the bottom of the gate electrode 12 protrudes to the n-type column 4 by increasing ΔG, when the drift layer 3 is depleted and the electric field becomes high in the n-type column 4, the gate insulation at the bottom of the trench 13 Membrane 11 is exposed to a high electric field. Furthermore, hot carriers accelerated by a high electric field may be injected into the inside of the gate insulating film 11 to degrade the insulation of the gate insulating film 11 and cause a decrease in reliability.

In contrast, in the semiconductor element 100 of the present embodiment, the gate-drain capacitance can be increased by providing the gate electrode 15 . Accordingly, the amount of protrusion of the gate electrode 12 onto the n-type pillar 4 can also be reduced to improve reliability.

Below the gate electrode 15 , a depletion layer spreads to the surface of the drift layer 3 which is in contact with the gate insulating film 14 . However, the electric field directly below the gate electrode 15 is lower than that of the center of the drift layer 3 because the directly below the gate electrode 15 is sandwiched by the p-type base region 6 held at a low potential. Therefore, hot carriers are not injected into the gate insulating film 14 and the insulating properties of the gate insulating film 14 are not lowered.

Next, a manufacturing process of the semiconductor element 100 will be described with reference to FIGS. 3 to 8 .

FIG. 3( a ) is a schematic view showing a cross-section taken along line Ia-Ia in FIG. 1 , showing a state where trenches 13 are formed on the surface of drift layer 3 provided on n-type drain layer 2 .

The n-type drain layer 2 and the drift layer 3 can be provided, for example, on a silicon substrate. A silicon layer doped with n-type impurities at a high concentration can be used for the n-type drain layer 2 . The drift layer 3 includes a super junction structure composed of p-type pillars 5 and n-type pillars 4 .

For example, the super junction structure can use RIE (Reactive Ion Etching, reactive ion etching) method to form a trench on the surface of the n-type silicon layer with a concentration lower than that of the n-type drain layer 2, and then make the p-type silicon epitaxial in the trench. grow and form.

Then, on the surface of the drift layer 3 where the trench 13 is provided, a conductive layer 22 serving as the gate electrodes 12 and 15 is formed via an insulating film 24 .

As the insulating film 24, for example, a silicon dioxide film (SiO ₂ film) formed by thermally oxidizing the surface of a silicon layer can be used to form the gate insulating film 11 and the gate insulating film 14.

The conductive layer 22 can be, for example, a polysilicon layer formed by CVD (Chemical Vapor Deposition, chemical vapor deposition) method.

FIG. 4 is a schematic diagram showing a manufacturing process subsequent to FIG. 3 , and shows a state where the conductive layer 22 is patterned to form the gate electrodes 12 and 15 .

Here, FIG. 4( a ) shows the structure of the Ia-Ia cross-section in FIG. 1( b ), and FIG. 4( b ) shows the structure of the IVb-IVb cross-section. Hereinafter, it is the same up to FIG. 8 .

For example, as shown in FIG. 4( b ), the conductive layer 22 on the drift layer 3 is etched while leaving the portion buried inside the trench 13 . Thus, the gate electrode 12 is formed as a so-called trench gate.

On the other hand, the gate electrode 15 can be provided by selectively etching the conductive layer 22 on the drift layer 3 and connecting adjacent gate electrodes 12 as shown in FIG. 4( a ).

Then, boron (B) ions are implanted, for example, as a p-type impurity into the surface of the drift layer 3 where the gate electrodes 12 and 15 are provided, thereby forming the p-type base region 6 .

As shown in FIG. 5( a ) and FIG. 5( b ), boron (B) is implanted into the surface of the drift layer 3 except the portion covered by the gate electrode 15 to form the p-type base region 6 .

Next, as shown in FIGS. 6( a ) and 6 ( b ), for example, arsenic (As) as an n-type impurity is selectively ion-implanted on the surface of drift layer 3 to form n-type source region 7 . In addition, boron (b) as a p-type impurity is selectively ion-implanted, thereby forming p ⁺ contact region 8 .

As shown in FIG. 6( a ), n-type source region 7 and p ⁺ contact region 8 are provided on the surface of drift layer 3 excluding the portion covered by gate electrode 15 .

As shown in FIG. 6( b ), a MOSFET having the same trench gate structure as that of the semiconductor element 600 shown in FIG. 14 is formed in a portion where the gate electrode 15 is not provided.

Next, as shown in FIGS. 7( a ) and 7 ( b ), interlayer insulating film 23 is formed on gate electrode 12 and gate electrode 15 , n-type source region 7 , and p ⁺ contact region 8 .

For the interlayer insulating film 23, for example, a SiO ₂ film formed by a CVD method can be used.

Then, as shown in FIG. 8(a) and FIG. 8(b), the interlayer insulating film 23 remains on the gate electrodes 12 and 15, and the insulating film on the surface of the n-type source region 7 and the p ⁺ contact region 8 24 and the interlayer insulating film 23 are selectively etched.

Thereafter, source electrode 19 is formed on gate electrodes 12 and 15 covered with interlayer insulating film 23 and on the surfaces of n-type source region 7 and p ⁺ contact region 8 .

Furthermore, the drain electrode 17 electrically connected to the n-type drain layer 2 is formed, so that the structure of the semiconductor element 100 can be completed.

FIG. 9 is a perspective view schematically showing the structure of a semiconductor element 200 according to a modified example of the present embodiment.

The semiconductor element 200 differs from the semiconductor element 100 in that the extending direction of the n-type pillars 4 and the p-type pillars 5 arranged in stripes is perpendicular to the extending direction of the trench 13 in which the gate electrode 12 is buried.

In the semiconductor element 200, for example, the lower portion of the gate electrode 15 provided on the p-type column 5 is occupied by the p-type region 5b as a part of the p-type column 5, and will not contribute to the gate electrode until the p-type column 5 is exhausted. Electrode-drain capacitance C _gd . Moreover, as shown in FIG. 2 , when the p-type column 5 is depleted and the drift layer 3 becomes a depletion layer as a whole, it starts to contribute to C _gd , so that C _gd increases as the drain voltage V _ds rises.

FIG. 10 is a perspective view schematically showing the structure of a semiconductor element 300 according to another modified example of the present embodiment.

In the semiconductor element 300 , the method of forming the p-type pillar 35 is different from that of the semiconductor element 100 . The p-type column 35 can be formed by, for example, repeating the steps of selectively ion-implanting n-type impurities and p-type impurities into a high-resistance epitaxial layer, performing heat treatment to diffuse the n-type impurities and p-type impurities, Further, a high-resistance epitaxial layer is deposited, ion implantation of n-type impurities and p-type impurities is performed, and heat treatment is performed.

FIG. 11 is a plan view showing the arrangement of gate electrodes in a modified example of the present embodiment.

As shown in FIG. 11( a ), the gate electrode 15 may be provided in a stripe shape, and may be provided so as to cross the extending direction of the gate electrode 12 and the n-type column 4 and the p-type column 5 .

Alternatively, as shown in FIG. 11( b ), gate electrodes 12 may be provided on both sides of p-type pillars 5 , and gate electrodes 15 may be arranged across n-type pillars 4 to connect gate electrodes 12 . In this case, since the p-type pillar 5 is not provided under the gate electrode 15, the gate electrode 15 directly contributes to the inter-gate-drain capacitance C _gd .

In addition, gate electrode 12 may also be provided at a plurality of portions spaced apart in one direction along the surface of drift layer 3 . Furthermore, the gate electrode 15 may be provided so as to connect a plurality of parts at the interval of the gate electrode 12 . As a result, the gate electrodes 12 and the gate electrodes 15 are alternately arranged in series.

In the example shown in FIG. 11( c ), gate electrodes 12 are provided on both sides of p-type pillar 5 at intervals along the extending direction of p-type pillar 5 . The gate electrode 15 includes a portion connecting adjacent gate electrodes 12 across the n-type column 4 (first joint portion 15 b ), and a portion connecting the spacer ΔU of the gate electrodes 12 (second joint portion 15 a ). ). Furthermore, the gate electrode 12 and the gate electrode 15 are arranged in series in the extending direction of the n-type column 4 and the p-type column 5 . As shown in FIG. 11( c ), the second junction portion 15 a connects the spaced apart first junction portions 15 b on the n-type pillar 4 and electrically connects a plurality of parts of the gate electrode 12 .

FIG. 12 is a schematic diagram showing a semiconductor element 400 including the gate electrode 15 shown in FIG. 11( a ). FIG. 12( a ) is a perspective view schematically showing the structure of the semiconductor element 400 , and FIG. 12( b ) is a schematic view showing the structure of the XIIb-XIIb cross section.

In the semiconductor element 400 , the n-type columns 4 and the p-type columns 5 are provided in a stripe shape, and the gate electrode 15 is also provided in a stripe shape intersecting a plurality of n-type columns 4 and a plurality of p-type columns 5 . As shown in FIG. 12( a ) and FIG. 12( b ), the gate electrode 12 is provided on the surface of the n-type pillar 4 along the extending direction of the n-type pillar 4 . The gate electrode 15 intersects the plurality of gate electrodes 12 and is electrically connected at this intersection point. Furthermore, since the p-type base region 6 is not provided under the gate electrode 15 , the gate electrode 15 faces the surfaces of the plurality of n-type columns 4 and p-type columns 5 via the gate insulating film 11 .

Thereby, compared with the case where the p-type base region 6 is formed under the gate electrode 15, it is possible to increase the gate-drain capacitance C _gd . In addition, a reverse bias voltage (reverse bias voltage) is applied to the pn junction between the n-type column 4 and the p-type column 5, and the gate-drain capacitance when the n-type column 4 and the p-type column 5 are exhausted together C _gd also gets bigger.

A p-type base region 6 is provided on the surface of the drift layer 3 between adjacent gate electrodes 15 . Furthermore, n-type source region 7 and p ⁺ contact region 8 are selectively provided on the surface of p-type base region 6 . N-type source region 7 faces side surfaces of gate electrode 12 with gate insulating film 11 interposed therebetween. The p ⁺ contact region 8 is provided in connection with the p-type base region 6 , and maintains the p-type base region 6 and the source electrode 19 (see FIG. 8( b )) at the same potential.

As shown in FIG. 12( a ), the n-type source region 7 is spaced apart from the drift layer 3 below the gate electrode 15 . That is, as shown in FIG. 12(a), a part 8a of the p ⁺ contact region 8 is sandwiched between the n-type source region 7 and the gate electrode 15, so that the p-type base region extending below the gate electrode 15 An outer edge (diffusion portion) 6 a of 6 is separated from n-type source region 7 . Accordingly, the drain current flowing through the inversion layer formed under the gate electrode 15 is suppressed, and current concentration is avoided. That is, if the n-type source region 7 is connected to the outer edge (diffusion portion) 6a of the p-type base region 6, there may arise a problem of current flow via an inversion layer having a low threshold voltage formed under the gate electrode 15. The drain current thus creates a current concentration.

As described above, in the first embodiment, the gate electrode 15 electrically connected to the gate electrode 12 is provided on the surface of the drift layer 3 via the gate insulating film 11 . Furthermore, by not providing a p-type base region under the gate electrode 15, the gate-drain capacitance is increased and switching noise is reduced. In addition, the n-type source region 7 is formed to be spaced apart from the gate electrode 15 to suppress the current flowing through the inversion layer below the gate electrode 15 having a low threshold voltage. Accordingly, the drain current flows through the trench gate including the gate electrode 12 , thereby reducing current concentration.

(second embodiment)

FIG. 13 is a schematic diagram showing the structure of a semiconductor element 500 according to the second embodiment. FIG. 13( a ) is a plan view showing part of the chip surface of the semiconductor element 500 excluding the source electrode 19 and the interlayer insulating film 23 (see FIG. 8 ). FIG. 13( b ) is a perspective view schematically showing the structure of the semiconductor element 500 .

In the semiconductor element 500 , the gate electrode 12 is provided on the surface of the n-type pillar 4 along the direction in which the n-type pillar 4 extends. Furthermore, the gate electrode 15 is formed on substantially the entire surface of the region of the drift layer 3 where the n-type column 4 and the p-type column 5 are provided with the gate insulating film 11 interposed therebetween.

The p-type base regions 6 are provided scattered on the surface of the drift layer 3 when viewed in plan view parallel to the main surface 2 a of the n-type drain layer 2 . Furthermore, a plurality of openings 31 penetrating from the surface of the gate electrode 15 to the p-type base region 6 are provided in the gate electrode 15 .

In addition, n-type source region 7 and p ⁺ contact region 8 adjacent to n-type source region 7 are selectively provided on the surface of p-type base region 6 forming the bottom surface of opening 31 . The p-type base region 6 is provided on the p-type pillar 5 . Furthermore, p ⁺ contact region 8 is formed to be connected to p-type base region 6 .

In the semiconductor element 500, when a gate voltage is applied, an inversion layer is formed on the surface of the p-type base region 6 facing the gate electrode 15 via the gate insulating film 11, and an inversion layer is formed on the source and drain electrodes. A drain current flows between them. In addition, an inversion layer is also formed on the surface of the p-type column 5 facing the gate electrode 15 via the gate insulating film 11 . As a result, the drain current flows through the entire n-type pillar 4, thereby reducing the on-resistance.

On the other hand, gate electrode 12 is provided on the surface of n-type pillar 4 . Compared with a simple planar portal structure, the gate-drain capacitance C _gd can be increased. Thus, it is possible to increase the output capacitance and reduce switching noise.

As shown in the above-described embodiment, the gate electrodes 12 and 15 can be provided by appropriately selecting a preferred configuration in accordance with the structure of the n-type column 4 and the p-type column 5 and the desired gate-drain capacitance C _gd .

In the above-mentioned embodiment, the example in which the n-type columns 4 and the p-type columns 5 are arranged in a stripe shape has been described, but the present invention is not limited to this, and it can also be applied to a super junction structure configured in a lattice shape, a dot shape, or the like. . Furthermore, an example in which the structure of the trench gate is also provided in stripes has been described, but the structure should be consistent with the gist of the embodiment in which the trench gate structure of low capacitance and the surface gate structure of high capacitance are combined. That is, it is not limited to the examples described above.

As mentioned above, although this invention was demonstrated with reference to one embodiment of this invention, this invention is not limited to these embodiment. For example, embodiments with the same technical idea as the present invention, such as design changes or material changes that can be accomplished by those skilled in the art based on the technical level at the time of application, are also included in the technical scope of the present invention.

In the above-described embodiments, the vertical power MOSFET made of silicon is described as an example, but as long as it has a MOS (Metal Oxide Semiconductor, Metal Oxide Semiconductor) gate structure and a structure with n-type columns and p-type columns , and you can use it. For example, it can be applied to other switching devices such as horizontal devices or IGBTs. The material is not limited to silicon, and the same effect can be obtained by using materials such as SiC and GaN.

Claims (20)

1. a semiconductor element is characterized in that, comprising:

First semiconductor layer of first conductivity type;

Second semiconductor layer is arranged on said first semiconductor layer, and is included in first post of first conductivity type that alternately is provided with on the direction of the interarea of said first semiconductor layer and second post of second conductivity type;

First control electrode, across first dielectric film and landfill in the inside of the groove that is provided with to the said first semi-conductive direction from the surface of said second semiconductor layer;

Second control electrode is arranged on said second semiconductor layer across second dielectric film, and links to each other with said first control electrode;

First semiconductor regions of second conductivity type is arranged on except that the surface by said second semiconductor layer the part of said second control electrode covering;

Second semiconductor regions of first conductivity type separates with the surface of said second semiconductor layer that is covered by said second control electrode, and optionally is arranged on the surface of said first semiconductor regions;

The 3rd semiconductor regions of second conductivity type, adjacent and optionally be arranged on the surface of said first semiconductor regions with said second semiconductor regions;

First main electrode is electrically connected with said first semiconductor layer; And

Second main electrode is electrically connected with said second semiconductor regions and the 3rd semiconductor regions.

2. semiconductor element according to claim 1 is characterized in that:

Said first post and said second post are arranged in along the upwardly extending striated in side of the said interarea of said first semiconductor layer;

Said first control electrode is arranged to striated on the bearing of trend of said first post and said second post.

3. semiconductor element according to claim 2 is characterized in that:

Said second control electrode is arranged to the striated that intersects with said first post and said second post.

4. semiconductor element according to claim 3 is characterized in that:

At said second semiconductor layer a plurality of said first control electrodes are being set;

A plurality of said second control electrodes are with being linked to be the ladder shape between adjacent said first control electrode.

5. semiconductor element according to claim 3 is characterized in that:

At said second semiconductor layer a plurality of said first control electrodes are being set;

A plurality of said second control electrodes are with being linked to be the ladder shape between adjacent said first control electrode;

With the direction of the bearing of trend quadrature of said first control electrode on, said second control electrode alternately is shifted and disposes.

6. semiconductor element according to claim 2 is characterized in that:

Said first control electrode on said first post along the bearing of trend setting of this first post.

7. semiconductor element according to claim 2 is characterized in that:

Said second control electrode is arranged to the striated that intersects with a plurality of said first posts and a plurality of said second post.

8. semiconductor element according to claim 1 is characterized in that:

A part that in said second semiconductor layer that covers by said second control electrode, comprises said second post.

9. semiconductor element according to claim 1 is characterized in that:

Said first post and said second post are arranged in along the upwardly extending striated in side of the said interarea of said first semiconductor layer;

Said first control electrode is arranged to the striated that intersects with said first post and said second post;

Said second control electrode is arranged to striated on the bearing of trend of said first post and said second post.

10. semiconductor element according to claim 9 is characterized in that:

Adjacent said first control electrode that said second control electrode will be arranged in a plurality of said first control electrode of said second semiconductor layer is linked to be the ladder shape.

11. semiconductor element according to claim 10 is characterized in that:

Said second control electrode is arranged on said second post.

12. semiconductor element according to claim 1 is characterized in that:

A plurality of said first posts and a plurality of said second post are arranged in along the upwardly extending striated in side of the said interarea of said first semiconductor layer;

Said first control electrode is arranged in the striated that extends on the border of said first post and said second post;

Said second control electrode links to each other adjacent said first control electrode on said first post and is provided with.

13. semiconductor element according to claim 12 is characterized in that:

A plurality of said second control electrode that said first control electrode is linked to each other is set as the ladder shape.

14. semiconductor element according to claim 1 is characterized in that:

Said first control electrode has a plurality of parts that are provided with on a direction on the surface of said second semiconductor layer, separating, and said second control electrode links to each other said a plurality of parts and is provided with;

Be arranged on the said direction to said first control electrode and the said second control electrode tandem.

15. semiconductor element according to claim 14 is characterized in that:

A plurality of said first posts and a plurality of said second post are arranged in along the upwardly extending striated in side of the said interarea of said first semiconductor layer;

Said a plurality of part is arranged on the border of said first post and said second post;

Said second control electrode comprises: a plurality of first junction surfaces, be arranged on said first post, will with the direction of the bearing of trend quadrature of said first post on the said part of adjacent said first control electrode link to each other; And second junction surface, will on the bearing of trend of said first post, adjacent said first link to each other, and a plurality of said parts will be electrically connected.

16. a semiconductor element is characterized in that, comprising:

First semiconductor layer of first conductivity type;

Second semiconductor layer is arranged on said first semiconductor layer, and is included in first post of first conductivity type that alternately is provided with on the direction of the interarea of said first semiconductor layer and second post of second conductivity type;

First control electrode, across first dielectric film and landfill in the inside of the groove that is provided with to the said first semi-conductive direction from the surface of said second semiconductor layer;

A plurality of first semiconductor regions are arranged on first semiconductor regions of second conductivity type on said second post, and are arranged to when the surface of carrying out being dispersed in when observing with overlooking of the said main surface parallel of said first semiconductor layer said second semiconductor layer;

Second control electrode is arranged on said second semiconductor layer across second dielectric film, links to each other with said first control electrode, and has a plurality of openings that penetrate into said first semiconductor regions;

Second semiconductor regions of first conductivity type optionally is arranged on the surface of said first semiconductor regions of the bottom surface that forms said opening;

The 3rd semiconductor regions of second conductivity type, adjacent and optionally be arranged on the surface of said first semiconductor regions with said second semiconductor regions;

First main electrode is electrically connected with said first semiconductor layer; And

Second main electrode is electrically connected with said second semiconductor regions and the 3rd semiconductor regions.

17. semiconductor element according to claim 16 is characterized in that:

Said second control electrode covers whole of the zone that said first post and said second post are being set in said second semiconductor layer.

18. semiconductor element according to claim 16 is characterized in that:

Said first post and said second post are arranged in along the upwardly extending striated in side of the said interarea of said first semiconductor layer;

Said first control electrode is arranged to along the striated of the bearing of trend of this first post on said first post.

19. the manufacturing approach of a semiconductor element, this semiconductor element comprises:

First semiconductor layer of first conductivity type;

Second semiconductor layer is arranged on said first semiconductor layer, and is included in first post of first conductivity type that alternately is provided with on the direction of the interarea of said first semiconductor layer and second post of second conductivity type;

First control electrode, across first dielectric film and landfill in the inside of the groove on the surface that is arranged on said second semiconductor layer;

Second control electrode is arranged on said second semiconductor layer across second dielectric film, and links to each other with said first control electrode;

First semiconductor regions is arranged on except that the surface by said second semiconductor layer the part of said second control electrode covering;

Second semiconductor regions of first conductivity type optionally is arranged on the surface of said first semiconductor regions;

The 3rd semiconductor regions of second conductivity type, adjacent and optionally be arranged on the surface of said first semiconductor regions with said second semiconductor regions;

First main electrode is electrically connected with said first semiconductor layer; And

Second main electrode is electrically connected with said second semiconductor regions and the 3rd semiconductor regions;

The manufacturing approach of this semiconductor element is characterised in that:

The conductive layer that makes the conductive layer that becomes said first control electrode and become said second control electrode forms simultaneously.

20. the manufacturing approach of semiconductor element according to claim 19 is characterized in that:

Said second control electrode as mask, is carried out ion with second contained in said first semiconductor regions conductive-type impurity and injects.

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