CN102412279B - Vertical parasitic PNP transistor in silicon-germanium BICMOS (Bipolar Complementary Metal Oxide Semiconductor) technique and fabrication method - Google Patents
Vertical parasitic PNP transistor in silicon-germanium BICMOS (Bipolar Complementary Metal Oxide Semiconductor) technique and fabrication method Download PDFInfo
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- CN102412279B CN102412279B CN201110326336.3A CN201110326336A CN102412279B CN 102412279 B CN102412279 B CN 102412279B CN 201110326336 A CN201110326336 A CN 201110326336A CN 102412279 B CN102412279 B CN 102412279B
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Abstract
The invention discloses a vertical parasitic PNP transistor in the silicon-germanium BICMOS technique. A groove which is in contact with a base region is formed in a shallow trench field oxide around the base region, the depth of the groove is smaller than or equal to the depth of the base region, polycrystalline silicon is filled in the groove and doped with N-type dopant, the polycrystalline silicon doped with the N-type dopant is formed into an outer base region, which is in contact with the side of the base region, and a metal contact is formed on the outer base region, and leads out a base. The invention also discloses a fabrication method for the vertical parasitic PNP transistor in the silicon-germanium BICMOS technique. The vertical parasitic PNP transistor can be used as an output device in a high-speed, high-gain HBT (heterojunction bipolar transistor) circuit, so that one more type of device is provided as an option for the circuit, the area of the device can be effectively reduced, the parasitic effect of the device can be effectively decreased, the collector resistance of the PNP transistor can be effectively decreased, and the performance of the device can be effectively enhanced; and the method does not need additional process conditions, and can reduce the production cost.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to vertical parastic PNP triode in a kind of germanium silicon BICMOS technique, the invention still further relates to the manufacture method of vertical parastic PNP triode in a kind of germanium silicon BICMOS technique.
Background technology
In radio frequency applications, need more and more higher device feature frequency.BiCMOS (Bipolar CMOS) is that CMOS and bipolar device are integrated in the technology on same chip simultaneously, in BiCMOS technology, NPN triode, particularly germanium silicon (SiGe) heterojunction triode (HBT) or germanium silicon-carbon heterojunction triode (SiGeC HBT) are the fine selections of hyperfrequency device.And SiGe technique is substantially compatible mutually with silicon technology, and therefore SiGe HBT has become one of main flow of hyperfrequency device.Under this background, it also correspondingly improves the requirement of output device, certain for being not less than 15 current gain coefficient and cut-off frequency such as having.
In prior art, output device can adopt the parasitic PNP triode of vertical-type, and in existing BiCMOS technique, the collector electrode of vertical parastic PNP device draws that common elder generation is formed at by one buried regions that shallow-trench isolation (STI) is oxygen bottom, shallow slot field or the collector region of trap and device contacts and collector region is drawn out in another active area adjacent with collector region, draws collector electrode by form Metal Contact in this another active area.Such way is to be determined by the vertical stratification feature of its device.Its shortcoming is that device area is large, and the contact resistance of collector electrode is large.Due to collector electrode of the prior art draw will by another active area adjacent with collector region realize and this another active area and collector region between need to isolate with STI or other oxygen, so greatly limited further dwindling of device size.
Summary of the invention
Technical problem to be solved by this invention is to provide vertical parastic PNP triode in a kind of germanium silicon BICMOS technique, can be as the output device in high speed, high-gain HBT circuit, for providing many a kind of devices, circuit selects, effectively the performance of reduction of device area, the ghost effect that reduces device, the collector resistance that reduces PNP pipe, raising device; The present invention also provides the manufacture method of vertical parastic PNP triode in a kind of germanium silicon BICMOS technique, and process conditions that need not be extra, can reduce production costs.
For solving the problems of the technologies described above, the invention provides vertical parastic PNP triode in a kind of germanium silicon BICMOS technique, be formed on silicon substrate, active area is isolated by shallow slot field oxygen, and the base of PNP triode is made up of the N-type ion implanted region being formed in described active area; In the described shallow slot field oxygen of all sides of described base, form one and the groove that contacts of described base, the described shallow slot field oxygen that is arranged in described groove is all removed, the degree of depth of described groove is less than or equal to the degree of depth of described base, in described groove, be filled with polysilicon and in described polysilicon, mixed N-type impurity, form outer base area by the described polysilicon that mixes N-type impurity, described outer base area and described base contact in the side of described base, be formed with Metal Contact and draw base stage on described outer base area.
The collector region of described PNP triode is made up of the P type ion implanted region being formed in described active area, and the degree of depth of described collector region is more than or equal to the bottom degree of depth of described shallow slot field oxygen; Described base is positioned at top, described collector region and contacts with described collector region.
Described PNP triode also comprises a counterfeit buried regions, P type ion implanted region by the oxygen bottom, described shallow slot field that is formed at all sides in described collector region forms, touch at described shallow slot field oxygen bottom connection described counterfeit buried regions and described collector region, is formed with deep hole and contacts and draw collector electrode in the oxygen of the described shallow slot field at described counterfeit buried regions top.
The emitter region of described PNP triode forms by being formed at polysilicon described surfaces of active regions and that adulterate for P type; Described emitter region forms and contacts with described base, is formed with Metal Contact and draws emitter at top, described emitter region.
Further improving is that the degree of depth of described groove is that 500 dust～1500 dusts, width are 0.2 micron～0.4 micron.
For solving the problems of the technologies described above, in germanium silicon BICMOS technique provided by the invention, the manufacture method of vertical parastic PNP triode comprises the steps:
Step 1, employing etching technics are formed with source region and shallow trench on silicon substrate.
Step 2, carry out P type Implantation in described shallow trench bottom and form counterfeit buried regions.
Step 3, in described shallow trench, insert silica and form shallow slot field oxygen.
Step 4, carry out in described active area N-type Implantation form base; The degree of depth of described base is less than the bottom degree of depth of described shallow trench.
Step 5, carry out P type Implantation form collector region in described active area, the degree of depth of described collector region is more than or equal to the bottom degree of depth of described shallow slot field oxygen, and described collector region forms and contacts with described counterfeit buried regions in bottom; The top of described collector region forms and contacts with described base.
Step 6, on described active area and described shallow slot field oxygen, form medium oxide layer.
Step 7, define figure with photoresist, described photoresist forms window in the location of the follow-up groove that will form, and the region of described groove is arranged in shallow slot field oxygen and and the side adjacency of described base of all sides of described base.
Step 8, adopt dry method to add the described medium oxide layer of the beneath window that photoresist forms described in wet-etching technology etching, and carry out excessive etching the described shallow slot field oxygen in the formation region of described groove is etched away and form described groove; The side of described groove and described base contacts, and the degree of depth of described groove is less than or equal to the degree of depth of described base.
Step 9, remove described photoresist and described medium oxide layer, growth regulation second medium layer also forms emitter window; Described emitter window is to adopt described in chemical wet etching technique etching to form after second medium layer, described emitter window is positioned at top, described active area and exposes described base, and the size of described emitter window is less than the size of described active area and defines the contact area of the follow-up emitter region that will form and described base.
Step 10, be formed with the front depositing polysilicon of described silicon substrate of described emitter window and described groove, described polysilicon is thick in other region of Thickness Ratio of the position of described groove, in the bottom of polysilicon described in the position of described groove, described groove is filled completely.
Step 11, described etching polysilicon is fallen to certain thickness; After etching, just in time described groove is filled up at polysilicon described in the position of described groove, described polysilicon and described base in described groove contact in the side of described base; After etching, the described polysilicon composition emitter region of top, described active area, described emitter region contacts at described emitter window place and described base.
Step 12, employing photoresist definition figure inject p type impurity in described emitter region.
Step 13, employing photoresist definition figure, described polysilicon in described groove is carried out to N-type Implantation, by in described groove and the described polysilicon that mixes N-type impurity form described outer base area, described outer base area and described base contact in the side of described base.
Step 14, in the oxygen of the described shallow slot field at described counterfeit buried regions top, form deep hole contact and draw collector electrode; Form Metal Contact at the top of described outer base area and draw base stage; Form Metal Contact at the top of described emitter region and draw emitter.
Further improving is that the degree of depth of groove described in step 8 is that 500 dust～1500 dusts, width are 0.2 micron～0.4 micron.
Further improving is that the process conditions of the N-type Implantation of base described in step 4 are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e14cm
-2～1e16cm
-2.
Further improving is that the process conditions of the P type Implantation of counterfeit buried regions described in step 2 are: implantation dosage is 1e14cm
-2～1e16cm
-2, energy for being less than 15keV, implanted dopant is boron or boron difluoride.
Further improve is that the P type Implantation of collector region described in step 5 adopts CMOS P trap injection technology in germanium silicon BICMOS technique.
Further improve and be, in step 12, share the photoresist definition figure that the P+ of the CMOS in germanium silicon BICMOS technique injects, and the P+ of CMOS in shared germanium silicon BICMOS technique is infused in described emitter region and injects p type impurity.More preferably be selected as, the impurity that the P+ of the CMOS in described germanium silicon BICMOS technique injects is phosphorus or arsenic, and implantation dosage is 5e14cm
-2～1e16cm
-2, Implantation Energy is 5kev～100kev.
Further improve is that the N-type Implantation of outer base area described in step 13 adopts the N+ of the emitter region polysilicon of NPN in germanium silicon BICMOS technique to inject.
In germanium silicon BICMOS technique of the present invention, vertical parastic PNP triode can, as the output device in high speed, high-gain HBT circuit, be selected for circuit provides many a kind of devices.Owing to having adopted advanced deep hole contact process, it matches with the technique of the counterfeit buried regions of P type, and this structure is carried out side direction by the base of PNP and is connected, greatly save the area of PNP triode active area, improve the ghost effect of PNP triode, reduce the collector resistance of PNP triode, improved the performance of device.The technique of the NPN triode in manufacture method energy of the present invention and germanium silicon BICMOS technique is integrated, thereby can reduce production costs.
Brief description of the drawings
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structural representation of vertical parastic PNP triode in embodiment of the present invention germanium silicon BICMOS technique;
Fig. 2-Fig. 7 is the structural representation of vertical parastic PNP triode in manufacture process in embodiment of the present invention germanium silicon BICMOS technique;
Fig. 8 A is the input characteristic curve of vertical parastic PNP triode in the embodiment of the present invention germanium silicon BICMOS technique of TCAD simulation;
Fig. 8 B is the gain curve of vertical parastic PNP triode in the embodiment of the present invention germanium silicon BICMOS technique of TCAD simulation.
Embodiment
As shown in Figure 1, be the structural representation of vertical parastic PNP triode in embodiment of the present invention germanium silicon BICMOS technique.In embodiment of the present invention germanium silicon BICMOS technique, vertical parastic PNP triode, is formed on silicon substrate, and active area is isolated by shallow slot field oxygen 1.
The base 3 of PNP triode is made up of the N-type ion implanted region being formed in described active area.The process conditions of the N-type Implantation of described base are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e14cm
-2～1e16cm
-2.
In the described shallow slot field oxygen 1 of all sides of described base 3, form one and the groove that contacts of described base 3, the described shallow slot field oxygen 1 that is arranged in described groove is all removed, the degree of depth of described groove is less than or equal to the degree of depth of described base 3, be preferably, the degree of depth of described groove is that 500 dust～1500 dusts, width are 0.2 micron～0.4 micron.
In described groove, be filled with polysilicon and in described polysilicon, mixed N-type impurity, the growth technique of described polysilicon of filling described groove is identical with the emitter-polysilicon growth technique of the NPN triode in germanium silicon BICMOS technique, and both can be integrated in one and form simultaneously; The doping process of described polysilicon of filling described groove is identical with the N+ of the emitter region 8B polysilicon of NPN in described germanium silicon BICMOS technique injection, and both can be integrated in one and form simultaneously.Form outer base area 8A by the described polysilicon that mixes N-type impurity, described outer base area 8A and described base 3 contact in the side of described base 3, be formed with Metal Contact 10 and draw base stage on described outer base area 8A.
The collector region 4 of described PNP triode is made up of the P type ion implanted region being formed in described active area, and the P type Implantation of described collector region adopts CMOS P trap injection technology in germanium silicon BICMOS technique.The degree of depth of described collector region 4 is more than or equal to the bottom degree of depth of described shallow slot field oxygen 1; Described base 3 is positioned at 4 tops, described collector region and contacts with described collector region 4.
Described PNP triode also comprises a counterfeit buried regions 2, is made up of the P type ion implanted region of oxygen 1 bottom, described shallow slot field that is formed at the 4 weeks sides in described collector region, and the process conditions of the P type Implantation of described counterfeit buried regions are: implantation dosage is 1e14cm
-2～1e16cm
-2, energy for being less than 15keV, implanted dopant is boron or boron difluoride.Touch at described shallow slot field oxygen 1 bottom connection described counterfeit buried regions 2 and described collector region 4, is formed with deep hole contact 9 and draws collector electrode in the described shallow slot field at described counterfeit buried regions 2 tops oxygen 1.
The emitter region 8B of described PNP triode forms by being formed at polysilicon described surfaces of active regions and that adulterate for P type; The growth technique of the described polysilicon of described emitter region 8B is identical with the growth technique of the emitter-polysilicon of the NPN triode in germanium silicon BICMOS technique, both can be integrated in one and form simultaneously, also can be integrated in a formation simultaneously with the growth technique of the described polysilicon of filling described groove.The process conditions of the P type doping of described emitter region 8B are identical with the P+ source leakage injection technology in PMOS in germanium silicon BICMOS technique, and both can be integrated in one and form simultaneously.
Described emitter region 8B forms and contacts with described base 3, and the emitter window that the contact area of described emitter region 8B and described base 3 forms after by second medium layer 7 etching defines.Be formed with Metal Contact 10 and draw emitter at 8B top, described emitter region.Metal level 11 is drawn device realize interconnection.
As shown in Figures 2 to 7, be the structural representation of vertical parastic PNP triode in manufacture process in embodiment of the present invention germanium silicon BICMOS technique.In embodiment of the present invention germanium silicon BICMOS technique, the manufacture method of vertical parastic PNP triode comprises the steps:
Step 1, as shown in Figure 2, adopts etching technics on silicon substrate, to be formed with source region and shallow trench.
Step 2, as shown in Figure 2, carries out P type Implantation in described shallow trench bottom and forms counterfeit buried regions 2.The process conditions of the P type Implantation of described counterfeit buried regions 2 are: implantation dosage is 1e14cm
-2～1e16cm
-2, energy for being less than 15keV, implanted dopant is boron or boron difluoride.
Step 3, is as shown in Figure 2 inserted silica and is formed shallow slot field oxygen 1 in described shallow trench.
Step 4, as shown in Figure 3, carries out N-type Implantation and forms base 3 in described active area; The degree of depth of described base 3 is less than the bottom degree of depth of described shallow trench.
Step 5, is as shown in Figure 3 carried out P type Implantation and is formed collector region 4 in described active area, and the degree of depth of described collector region 4 is more than or equal to the bottom degree of depth of described shallow slot field oxygen 1, and described collector region 4 forms and contacts with described counterfeit buried regions 2 in bottom; The top of described collector region 4 forms and contacts with described base 3.The P type Implantation of described collector region 4 adopts CMOS P trap injection technology in germanium silicon BICMOS technique.
Step 6, as shown in Figure 4 forms medium oxide layer 5 on described active area and described shallow slot field oxygen 1.The thickness of described medium oxide layer 5 is 300 dust to 2000 dusts.
Step 7, as shown in Figure 5A, defines figure with photoresist, and described photoresist forms window in the location of the follow-up groove that will form, and the region of described groove is arranged in shallow slot field oxygen 1 and and the side adjacency of described base 3 of all sides of described base 3.
Step 8, as shown in Figure 5A, adopts dry method to add the described medium oxide layer 5 of the beneath window that photoresist forms described in wet-etching technology etching, and carries out excessive etching the described shallow slot field oxygen 1 in the formation region of described groove is etched away and form described groove; The side of described groove and described base 3 contacts, and the degree of depth of described groove is less than or equal to the degree of depth of described base 3, is preferably, and the degree of depth of described groove is that 500 dust～1500 dusts, width are 0.2 micron～0.4 micron.
For with germanium silicon BICMOS technique in NPN triode integrated, in the embodiment of the present invention, be also included in PNP triode region deposit germanium silicon layer 6 and remove the step of described germanium silicon layer 6, as shown in Figure 5 B, deposit germanium silicon layer 6 described in one deck; As shown in Figure 5 C, described germanium silicon layer 6 and described medium oxide layer 5 are all removed.Certainly,, if while forming separately in embodiment of the present invention germanium silicon BICMOS technique vertical parastic PNP triode, also can not comprise the step of deposit and the removal of described germanium silicon layer 6.
Step 9, as shown in Figure 6, growth regulation second medium layer 7 also forms emitter window, and described second medium layer 7 can be oxide-film, nitride film, the combination between amorphous polysilicon 8 and this three kinds of films thereof.Described emitter window is to adopt the rear formation of second medium layer 7 described in chemical wet etching technique etching, described emitter window is positioned at top, described active area and exposes described base 3, and the size of described emitter window is less than the size of described active area and defines the contact area of the follow-up emitter region 8B that will form and described base 3.
Step 10, as shown in Figure 6, be formed with the front depositing polysilicon 8 of described silicon substrate of described emitter window and described groove, described polysilicon 8 is thick in other region of Thickness Ratio of the position of described groove, in the bottom of polysilicon 8 described in the position of described groove, described groove is filled completely.The depositing technics of the emitter region polysilicon of NPN in the process using germanium silicon BICMOS technique of polysilicon 8 described in deposit, two can be integrated in one forms simultaneously.
Step 11, as shown in Figure 7, etches away certain thickness by described polysilicon 8; After etching, just in time described groove is filled up at polysilicon 8 described in the position of described groove, described polysilicon 8 and described base 3 in described groove contact in the side of described base 3; After etching, the described polysilicon 8 of top, described active area forms emitter region 8B, and described emitter region 8B contacts at described emitter window place and described base 3.
Step 12, as shown in Figure 7, shares the photoresist definition figure that the P+ of the CMOS in germanium silicon BICMOS technique injects, and the P+ of CMOS in shared germanium silicon BICMOS technique is infused in described emitter region and injects p type impurity.The impurity that the P+ of CMOS in described germanium silicon BICMOS technique injects is phosphorus or arsenic, and implantation dosage is 5e14cm
-2～1e16cm
-2, Implantation Energy is 5kev～100kev.
Step 13, as shown in Figure 7, adopt photoresist definition figure, described polysilicon 8 in described groove is carried out to N-type Implantation, by described groove and the described polysilicon 8 that mixes N-type impurity form described outer base area 8A, described outer base area 8A and described base 3 contact in the side of described base 3.The N-type Implantation of described outer base area 8A adopts the N+ of the emitter region polysilicon of NPN in germanium silicon BICMOS technique to inject, and two can be integrated in one forms simultaneously.
Step 14, as shown in Figure 1 forms deep hole contact 9 and draws collector electrode in the described shallow slot field at described counterfeit buried regions 2 tops oxygen 1; Form Metal Contact 10 at the top of described outer base area 8A and draw base stage; Form Metal Contact 10 at the top of described emitter region 8B and draw emitter.Finally forming metal level 11 draws device.
As shown in Figure 8 A and 8 B, be respectively input characteristic curve and the gain curve of vertical parastic PNP triode in the embodiment of the present invention germanium silicon BICMOS technique of TCAD simulation.Therefrom can find out, owing to having adopted advanced deep hole contact process directly to contact with the counterfeit buried regions of P type, draw the collector electrode of this device, the area of device has compared with prior art effectively reduced.And because extraction location is to the Distance Shortened of collector region, add the highly doped counterfeit buried regions of P type, the resistance of collector electrode also reduces thereupon effectively, thereby helps and the frequency characteristic that improves device.And other characteristics, such as input characteristics and current gain, but can be not influenced, current gain can remain on more than 20.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a vertical parastic PNP triode in germanium silicon BICMOS technique, is formed on silicon substrate, and active area is isolated by shallow slot field oxygen, it is characterized in that:
The base of PNP triode is made up of the N-type ion implanted region being formed in described active area; In the described shallow slot field oxygen of all sides of described base, form one and the groove that contacts of described base, the described shallow slot field oxygen that is arranged in described groove is all removed, the degree of depth of described groove is less than or equal to the degree of depth of described base, in described groove, be filled with polysilicon and in described polysilicon, mixed N-type impurity, form outer base area by the described polysilicon that mixes N-type impurity, described outer base area and described base contact in the side of described base, be formed with Metal Contact and draw base stage on described outer base area;
The collector region of described PNP triode is made up of the P type ion implanted region being formed in described active area, and the degree of depth of described collector region is more than or equal to the bottom degree of depth of described shallow slot field oxygen; Described base is positioned at top, described collector region and contacts with described collector region;
Described PNP triode also comprises a counterfeit buried regions, P type ion implanted region by the oxygen bottom, described shallow slot field that is formed at all sides in described collector region forms, touch at described shallow slot field oxygen bottom connection described counterfeit buried regions and described collector region, is formed with deep hole and contacts and draw collector electrode in the oxygen of the described shallow slot field at described counterfeit buried regions top;
The emitter region of described PNP triode forms by being formed at polysilicon described surfaces of active regions and that adulterate for P type; Described emitter region forms and contacts with described base, is formed with Metal Contact and draws emitter at top, described emitter region.
2. vertical parastic PNP triode in germanium silicon BICMOS technique as claimed in claim 1, is characterized in that: the degree of depth of described groove is that 500 dust～1500 dusts, width are 0.2 micron～0.4 micron.
3. a manufacture method for vertical parastic PNP triode in germanium silicon BICMOS technique, is characterized in that, comprises the steps:
Step 1, employing etching technics are formed with source region and shallow trench on silicon substrate;
Step 2, carry out P type Implantation in described shallow trench bottom and form counterfeit buried regions;
Step 3, in described shallow trench, insert silica and form shallow slot field oxygen;
Step 4, carry out in described active area N-type Implantation form base; The degree of depth of described base is less than the bottom degree of depth of described shallow trench;
Step 5, carry out P type Implantation form collector region in described active area, the degree of depth of described collector region is more than or equal to the bottom degree of depth of described shallow slot field oxygen, and described collector region forms and contacts with described counterfeit buried regions in bottom; The top of described collector region forms and contacts with described base;
Step 6, on described active area and described shallow slot field oxygen, form medium oxide layer;
Step 7, define figure with photoresist, described photoresist forms window in the location of the follow-up groove that will form, the region of described groove be arranged in described base all sides shallow slot field oxygen and and the side adjacency of described base;
Step 8, adopt dry method to add the described medium oxide layer of the beneath window that photoresist forms described in wet-etching technology etching, and carry out excessive etching the described shallow slot field oxygen in the formation region of described groove is etched away and form described groove; The side of described groove and described base contacts, and the degree of depth of described groove is less than or equal to the degree of depth of described base;
Step 9, remove described photoresist and described medium oxide layer, growth regulation second medium layer also forms emitter window; Described emitter window is to adopt described in chemical wet etching technique etching to form after second medium layer, described emitter window is positioned at top, described active area and exposes described base, and the size of described emitter window is less than the size of described active area and defines the contact area of the follow-up emitter region that will form and described base;
Step 10, be formed with the front depositing polysilicon of described silicon substrate of described emitter window and described groove, described polysilicon is thick in other region of Thickness Ratio of the position of described groove, in the bottom of polysilicon described in the position of described groove, described groove is filled completely;
Step 11, described etching polysilicon is fallen to certain thickness; After etching, just in time described groove is filled up at polysilicon described in the position of described groove, described polysilicon and described base in described groove contact in the side of described base; After etching, the described polysilicon composition emitter region of top, described active area, described emitter region contacts at described emitter window place and described base;
Step 12, employing photoresist definition figure inject p type impurity in described emitter region;
Step 13, adopt photoresist definition figure, the described polysilicon in described groove carried out to N-type Implantation, by described groove and the described polysilicon that mixes N-type impurity form outer base area, described outer base area and described base contact in the side of described base;
Step 14, in the oxygen of the described shallow slot field at described counterfeit buried regions top, form deep hole contact and draw collector electrode; Form Metal Contact at the top of described outer base area and draw base stage; Form Metal Contact at the top of described emitter region and draw emitter.
4. the manufacture method of vertical parastic PNP triode in germanium silicon BICMOS technique as claimed in claim 3, is characterized in that: the degree of depth of groove described in step 8 is that 500 dust～1500 dusts, width are 0.2 micron～0.4 micron.
5. the manufacture method of vertical parastic PNP triode in germanium silicon BICMOS technique as claimed in claim 3, is characterized in that: the process conditions of the N-type Implantation of base described in step 4 are: implanted dopant is that phosphorus or arsenic, energy condition are that 100Kev～300Kev, dosage are 1e14cm
-2～1e16cm
-2.
6. the manufacture method of vertical parastic PNP triode in germanium silicon BICMOS technique as claimed in claim 3, is characterized in that: the process conditions of the P type Implantation of counterfeit buried regions described in step 2 are: implantation dosage is 1e14cm
-2～1e16cm
-2, energy for being less than 15keV, implanted dopant is boron or boron difluoride.
7. the manufacture method of vertical parastic PNP triode in germanium silicon BICMOS technique as claimed in claim 3, is characterized in that: the P type Implantation of collector region described in step 5 adopts CMOS P trap injection technology in germanium silicon BICMOS technique.
8. the manufacture method of vertical parastic PNP triode in germanium silicon BICMOS technique as claimed in claim 3, it is characterized in that: in step 12, share the photoresist definition figure that the P+ of the CMOS in germanium silicon BICMOS technique injects, and the P+ of CMOS in shared germanium silicon BICMOS technique is infused in described emitter region and injects p type impurity.
9. the manufacture method of vertical parastic PNP triode in germanium silicon BICMOS technique as claimed in claim 8, is characterized in that: the implantation dosage that the P+ of the CMOS in described germanium silicon BICMOS technique injects is 5e14cm
-2～1e16cm
-2, Implantation Energy is 5kev～100kev.
10. the manufacture method of vertical parastic PNP triode in germanium silicon BICMOS technique as claimed in claim 3, is characterized in that: the N-type Implantation of outer base area described in step 13 adopts the N+ of the emitter region polysilicon of NPN in germanium silicon BICMOS technique to inject.
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| CN1174478C (en) * | 1997-03-18 | 2004-11-03 | 因芬尼昂技术股份公司 | Bipolar device and method of manufacturing the same |
| US6878976B2 (en) * | 2002-03-13 | 2005-04-12 | International Business Machines Corporation | Carbon-modulated breakdown voltage SiGe transistor for low voltage trigger ESD applications |
| US6979884B2 (en) * | 2003-12-04 | 2005-12-27 | International Business Machines Corporation | Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border |
| CN1943034B (en) * | 2004-04-22 | 2011-11-16 | 国际商业机器公司 | Tuneable semiconductor device |
| US7488662B2 (en) * | 2005-12-13 | 2009-02-10 | Chartered Semiconductor Manufacturing, Ltd. | Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process |
| CN102117827B (en) * | 2009-12-31 | 2012-11-07 | 上海华虹Nec电子有限公司 | Parasitic vertical PNP device in bipolar complementary metal oxide semiconductor (BiCMOS) process |
| CN102130152B (en) * | 2010-01-18 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | Self-aligned bipolar transistor and manufacturing method thereof |
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