CN102412263B - Semiconductor device with pre-metal dielectric filling structure and preparation method thereof - Google Patents
Semiconductor device with pre-metal dielectric filling structure and preparation method thereof Download PDFInfo
- Publication number
- CN102412263B CN102412263B CN201110274490.0A CN201110274490A CN102412263B CN 102412263 B CN102412263 B CN 102412263B CN 201110274490 A CN201110274490 A CN 201110274490A CN 102412263 B CN102412263 B CN 102412263B
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- hard mask
- mask layer
- layer
- metal dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 28
- 239000002184 metal Substances 0.000 title claims abstract description 28
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000010276 construction Methods 0.000 claims description 28
- 229920005591 polysilicon Polymers 0.000 claims description 24
- 230000003068 static effect Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052721 tungsten Inorganic materials 0.000 abstract description 10
- 239000010937 tungsten Substances 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 48
- 238000010586 diagram Methods 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 2
- 230000004224 protection Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000006263 metalation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Images
Landscapes
- Semiconductor Memories (AREA)
- Element Separation (AREA)
Abstract
The invention relates to a semiconductor device with a pre-metal dielectric filling structure and a preparation method thereof. The semiconductor device comprises a substrate, a trench isolation structure and a polycrystalline silicon grid layer, the trench isolation structure is formed in the substrate, the polycrystalline silicon grid layer is formed on the surface of the substrate, and a groove is formed on the polycrystalline silicon grid layer at the position of the trench isolation structure. The height-to-width ratio of the gap between two neighboring grids of the semiconductor device with the pre-metal dielectric filling structure can be reduced, holes cannot be easily produced when pre-metal dielectric is filled in the gap, consequently, tungsten is prevented from entering the holes to cause a problem in the conduction between the neighboring grids in the subsequent tungsten plugging process, and thereby the yield can be increased.
Description
Technical field
The present invention relates to a kind of semiconductor device with front Filled Dielectrics (Pre Metal Dieletric, the PMD) structure of metal and preparation method thereof.
Background technology
Before-metal medium layer is as the wall of device and interconnecting metal interlayer and make device avoid the protective layer that foreign particle pollutes, and the quality of its rete deposition effect directly affects performance of devices.Along with dwindling gradually of integrated circuit specific dimensions, need the bulk of the front Filled Dielectrics of metal also more and more less, challenge is more and more arranged.
See also Fig. 1, Fig. 2, Fig. 1 is a kind of domain schematic diagram of static random access memory (Static Random Access Memory, SRAM) of prior art, and Fig. 2 is that SRAM in Fig. 1 is along the cross-sectional view of A-A line.As seen from Figure 2, being filled by gap pmd layer 12 between adjacent two transistorized grids 11 in SRAM.Yet, in actual production, after pmd layer 12 is filled, be very easy to produce cavity 13 between two grids 11.Described empty 13 existence is easy to cause in follow-up tungsten plug technique, and tungsten enters the cavity 13 between neighboring gates 11, causes conducting between neighboring gates 11, thereby causes yield loss.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device with pre-metal dielectric filling structure that can avoid forming between neighboring gates the cavity.
Another object of the present invention also is to provide a kind of preparation method that can avoid forming between neighboring gates the semiconductor device with pre-metal dielectric filling structure in cavity.
A kind of semiconductor device with pre-metal dielectric filling structure, comprise substrate, be formed at the groove isolation construction in described substrate and the polysilicon gate layer that is formed at described substrate surface, described polysilicon gate layer forms groove in the position of described groove isolation construction.
A kind of preparation method with semiconductor device of pre-metal dielectric filling structure comprises the steps: to provide a substrate, and described substrate comprises groove isolation construction; Form successively polysilicon layer, the first hard mask layer and the second hard mask layer on the surface of described substrate; Surface at described the second hard mask layer forms the first photoresistance pattern, and the top of described groove isolation construction is not by described the first photoresistance pattern covers; Take described the first photoresistance pattern as mask, described the second hard mask layer of etching, the second hard mask layer above described groove isolation construction is etched, thereby exposes the first hard mask layer of described groove isolation construction top; Remove described the first photoresistance pattern; Form the second photoresistance pattern at described the second hard mask layer and the surface of described the first hard mask layer of position that will form the grid layer of described semiconductor device; Respectively take described the second photoresistance pattern, the second hard mask layer and the first hard mask layer as mask, the described polysilicon layer of etching forms the polysilicon gate layer of described semiconductor device, and described polysilicon gate layer forms groove in the position of described groove isolation construction.
Compared with prior art, due to the position at the groove isolation construction of described substrate, polysilicon gate layer with semiconductor device of pre-metal dielectric filling structure forms groove, reduced the thickness of transistorized grid in the semiconductor device, thereby reduced the depth-width ratio in the gap between adjacent two grids in the semiconductor device, when Filled Dielectrics before metal is in described gap, be not easy to produce the cavity, avoided in follow-up tungsten plug technique, tungsten enters the cavity and causes getting the problem of conducting between neighboring gates, is conducive to the raising of yield.
Description of drawings
Fig. 1 is a kind of domain schematic diagram of static random access memory of prior art.
Fig. 2 is that static random access memory shown in Figure 1 is along the cross-sectional view of A-A line.
Fig. 3 is the domain schematic diagram with semiconductor device of pre-metal dielectric filling structure of the present invention.
Fig. 4 is that semiconductor device shown in Figure 3 is along the cross-sectional view of B-B line.
Fig. 5 a is each step schematic diagram of the preparation method of the semiconductor device with pre-metal dielectric filling structure of the present invention to Figure 11 c.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
See also Fig. 3, Fig. 4, Fig. 3 is the domain schematic diagram with semiconductor device of pre-metal dielectric filling structure of the present invention, and Fig. 4 is that semiconductor device shown in Figure 3 is along the cross-sectional view of B-B line.Concrete, described semiconductor device can be static random access memory.The semiconductor device of the PMD of having interstitital texture of the present invention comprises substrate 20, is formed at the groove isolation construction 21 in described substrate 20 and the polysilicon gate layer 22 that is formed at described substrate 20 surfaces.Described polysilicon gate layer 22 forms groove 23 in the position of described groove isolation construction 21.The part of described polysilicon gate layer 22 at described groove 23 places forms the transistorized grid of described semiconductor device.
Described groove isolation construction 21 can be fleet plough groove isolation structure (STI), fills isolation oxide in described groove.The width on the top of described groove 23 is less than the width of bottom, and is concrete, and the fluting shape of described groove 23 can be rectangle or inverted trapezoidal or triangle.Consider that light shield is aimed at factor and when Implantation to enough protections in AA district, the groove width of groove 23 slightly is narrower than the characteristic size of described groove isolation construction.The variation of the resistance value of described grid can adjust accordingly by the mode of Implantation.
Due to the position at the groove isolation construction 21 of described substrate 20, polysilicon gate layer 22 with semiconductor device of pre-metal dielectric filling structure of the present invention forms groove 23, reduced the thickness of transistorized grid in the semiconductor device, thereby reduced the depth-width ratio in the gap between adjacent two grids in the semiconductor device, when Filled Dielectrics before metal is in described gap, be not easy to produce the cavity, avoided in follow-up tungsten plug technique, tungsten enters the cavity and causes getting the problem of conducting between neighboring gates, is conducive to the raising of yield.
Fig. 5 a is each step schematic diagram of the preparation method of the semiconductor device with pre-metal dielectric filling structure of the present invention to Figure 11 c, and wherein, each step is represented by three generalized sections of a, b, c of three different directions of described semiconductor device.Fig. 5 a is in each step of preparation method of the present invention to Figure 11 a, semiconductor device shown in Figure 3 is along the cross-sectional view of B-B line, Fig. 5 b is in each step of preparation method of the present invention to Figure 11 b, semiconductor device shown in Figure 3 is along the cross-sectional view of C-C line, Fig. 5 c is that in each step of preparation method of the present invention, semiconductor device shown in Figure 3 is along the cross-sectional view of D-D line to Figure 11 c.Preferably, described semiconductor device is static random access memory.Method of the present invention comprises the steps:
One substrate 30 is provided, and described substrate 30 comprises groove isolation construction 31.Described groove isolation construction 31 can be fleet plough groove isolation structure.
At the surface deposition polysilicon layer 32 of described substrate 30, as shown in Fig. 5 a, Fig. 5 b, Fig. 5 c.
Deposit successively the first hard mask layer 33 and the second hard mask layer 34 on the surface of described polysilicon layer 32, as shown in Fig. 6 a, Fig. 6 b, Fig. 6 c.Concrete, described the first hard mask layer 33 is silicon oxide layer, described the second hard mask layer 34 is silicon nitride layer (SiN).
Surface at described the second hard mask layer 34 forms the first photoresistance pattern 35, and the top of described groove isolation construction 31 is not covered by described the first photoresistance pattern 35, as shown in Fig. 7 a, Fig. 7 b, Fig. 7 c.
Take described the first photoresistance pattern 35 as mask, described the second hard mask layer 34 of etching, the second hard mask layer 34 of described groove isolation construction 31 tops is by dry etching, thereby exposes the first hard mask layer 33 of described groove isolation construction 31 tops, as shown in Fig. 8 a, Fig. 8 b, Fig. 8 c.
Remove described the first photoresistance pattern 35, as shown in Fig. 9 a, Fig. 9 b, Fig. 9 c.
Form the second photoresistance pattern 36 at described the second hard mask layer 34 and the surface of described the first hard mask layer 33 of position that will form the grid layer of described semiconductor device, as shown in Figure 10 a, Figure 10 b, Figure 10 c.
Respectively take described the second photoresistance pattern 36, the second hard mask layer 34 and the first hard mask layer 33 as mask, adopt the described polysilicon layer 32 of dry etch process etching, form the polysilicon gate layer of described semiconductor device, described polysilicon gate layer forms groove 37 in the position of described groove isolation construction 31, the part of described polysilicon gate layer 32 at described groove 37 places forms the transistorized grid 38 of described semiconductor device, as shown in Figure 11 a, Figure 11 b, Figure 11 c.Preferably, the width on the top of described groove 27 is less than the width of bottom, and is concrete, and the fluting shape of described groove 27 can be rectangle or inverted trapezoidal or triangle.Consider that light shield is aimed at factor and when Implantation to enough protections in AA district, the groove width of groove 27 slightly is narrower than the characteristic size of described groove isolation construction.The variation of the resistance value of described grid can adjust accordingly by the mode of Implantation.
The semiconductor device that adopts method of the present invention to form, due to the position at groove isolation construction 31, polysilicon gate layer 32 forms groove 37, reduced the thickness of transistorized grid 38 in the semiconductor device, thereby reduced the depth-width ratio in the gap between adjacent two grids 38 in the semiconductor device, when Filled Dielectrics before metal is in described gap, be not easy to produce the cavity, avoided in follow-up tungsten plug technique, tungsten enters the cavity and causes getting the problem of conducting between neighboring gates, is conducive to the raising of yield.Further, only limit to groove isolation construction 31 parts of substrate 30 due to the slot area of polysilicon gate layer 32, therefore, can adopt the light shield that forms groove isolation construction 31, do not need extra increase illumination, method of the present invention is simple, and cost is low.
In the situation that can also consist of without departing from the spirit and scope of the present invention many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the present invention is not limited at the specific embodiment described in specification.
Claims (5)
1. the preparation method with semiconductor device of pre-metal dielectric filling structure, is characterized in that, comprises the steps:
One substrate is provided, and described substrate comprises groove isolation construction;
Form successively polysilicon layer, the first hard mask layer and the second hard mask layer on the surface of described substrate;
Surface at described the second hard mask layer forms the first photoresistance pattern, and the top of described groove isolation construction is not by described the first photoresistance pattern covers;
Take described the first photoresistance pattern as mask, described the second hard mask layer of etching, the second hard mask layer above described groove isolation construction is etched, thereby exposes the first hard mask layer of described groove isolation construction top;
Remove described the first photoresistance pattern;
Form the second photoresistance pattern at described the second hard mask layer and the surface of described the first hard mask layer of position that will form the grid layer of described semiconductor device;
Respectively take described the second photoresistance pattern, the second hard mask layer and the first hard mask layer as mask, the described polysilicon layer of etching forms the polysilicon gate layer of described semiconductor device, and described polysilicon gate layer forms groove in the position of described groove isolation construction.
2. the preparation method with semiconductor device of pre-metal dielectric filling structure as claimed in claim 1, is characterized in that, described the second hard mask layer is silicon nitride layer.
3. the preparation method with semiconductor device of pre-metal dielectric filling structure as claimed in claim 1, is characterized in that, described the first hard mask layer is silicon oxide layer.
4. the preparation method with semiconductor device of pre-metal dielectric filling structure as claimed in claim 1, is characterized in that, adopts described first, second hard mask layer of dry etching and described polysilicon layer.
5. the preparation method with semiconductor device of pre-metal dielectric filling structure as claimed in claim 1, is characterized in that, described semiconductor device is static random access memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110274490.0A CN102412263B (en) | 2011-09-15 | 2011-09-15 | Semiconductor device with pre-metal dielectric filling structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110274490.0A CN102412263B (en) | 2011-09-15 | 2011-09-15 | Semiconductor device with pre-metal dielectric filling structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102412263A CN102412263A (en) | 2012-04-11 |
| CN102412263B true CN102412263B (en) | 2013-06-12 |
Family
ID=45914250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110274490.0A Active CN102412263B (en) | 2011-09-15 | 2011-09-15 | Semiconductor device with pre-metal dielectric filling structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102412263B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1684262A (en) * | 2003-09-05 | 2005-10-19 | 台湾积体电路制造股份有限公司 | Static random access memory unit and semiconductor element |
| CN102446740A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Integrated process for improving gap fill property of PMD (pre-metal dielectric) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100678461B1 (en) * | 2004-11-08 | 2007-02-02 | 삼성전자주식회사 | SRAMs with landing pads in contact with upper and lower cell gate patterns and methods of forming the same |
| US7294890B2 (en) * | 2005-03-03 | 2007-11-13 | Agency For Science, Technology And Research | Fully salicided (FUSA) MOSFET structure |
| US8101497B2 (en) * | 2008-09-11 | 2012-01-24 | Micron Technology, Inc. | Self-aligned trench formation |
| KR101087835B1 (en) * | 2009-11-26 | 2011-11-30 | 주식회사 하이닉스반도체 | Method of forming fine pattern of semiconductor device |
-
2011
- 2011-09-15 CN CN201110274490.0A patent/CN102412263B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1684262A (en) * | 2003-09-05 | 2005-10-19 | 台湾积体电路制造股份有限公司 | Static random access memory unit and semiconductor element |
| CN102446740A (en) * | 2011-08-29 | 2012-05-09 | 上海华力微电子有限公司 | Integrated process for improving gap fill property of PMD (pre-metal dielectric) |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102412263A (en) | 2012-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9613967B1 (en) | Memory device and method of fabricating the same | |
| JP6310577B2 (en) | Manufacturing method of split gate type power device | |
| CN104952718B (en) | A method of manufacturing a split-gate power device | |
| CN105702736A (en) | A shield grid oxide layer of a shield grid-deep groove MOSFET and a formation method thereof | |
| CN104916544B (en) | A method for manufacturing a trench-type split-gate power device | |
| CN209641689U (en) | Magnetic RAM | |
| CN104347422A (en) | Manufacturing method of groove type MOS (Metal Oxide Semiconductor) transistor with electrostatic discharge protection circuit | |
| CN103426823A (en) | Method for manufacturing flash memory | |
| CN104425220A (en) | Method for forming pattern | |
| CN108573079B (en) | Fabrication method of contact plug layout | |
| KR101917605B1 (en) | Semiconductor device and manufacturing method of the same | |
| CN104517824B (en) | The manufacture method of groove type double-layer grid | |
| TWI396261B (en) | Low parasitic capacitance bit line process for stack dram | |
| CN105655385B (en) | The manufacturing method of groove-shaped super-junction device | |
| CN102412263B (en) | Semiconductor device with pre-metal dielectric filling structure and preparation method thereof | |
| WO2023028825A1 (en) | Semiconductor device and preparation method therefor | |
| TW201349353A (en) | Transistor element and method of manufacturing same | |
| CN102651305A (en) | Preparation method of omega-shaped fin | |
| US9269618B2 (en) | Semiconductor device and method for manufacturing the same | |
| CN104576510A (en) | Self-alignment contact hole etching method | |
| CN104103576A (en) | Contacting hole technical method of groove-type double layer grid power MOS device | |
| CN209045527U (en) | Fleet plough groove isolation structure | |
| KR102029923B1 (en) | Method for manufacturing semiconductor device with side contact | |
| CN102446740B (en) | Integrated process for improving gap fill property of PMD (pre-metal dielectric) | |
| CN102543878B (en) | Manufacturing method of memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |