CN102403299A - Circuit board structure and its manufacturing method - Google Patents
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Abstract
Description
技术领域 technical field
本发明有关一种半导体装置及其制法,尤指一种电路板结构及其制法。The invention relates to a semiconductor device and its manufacturing method, especially to a circuit board structure and its manufacturing method.
背景技术 Background technique
随着电子产业的蓬勃发展,电子产品也逐渐迈向多功能、高性能的趋势。而为了满足半导体封装件高整合度(integration)及微型化(miniaturization)的封装需求,以供更多主、被动元件及线路载接,半导体封装基板亦逐渐由双层电路板演变成多层电路板(multi-layerboard),从而于有限的空间下运用层间连接技术(interlayer connection)以扩大半导体封装基板上可供利用的线路布局面积,并配合高线路密度的集成电路(integrated circuit)需要,而能达到封装件轻薄短小及提高电性功能的目的。With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. In order to meet the packaging requirements of high integration and miniaturization of semiconductor packages for more active and passive components and circuit loading, semiconductor packaging substrates have gradually evolved from double-layer circuit boards to multi-layer circuits. board (multi-layer board), so as to use interlayer connection technology (interlayer connection) in a limited space to expand the available circuit layout area on the semiconductor package substrate, and to meet the needs of integrated circuits with high circuit density, Therefore, the purpose of light, thin, small and small packages and improved electrical functions can be achieved.
美国专利第2008/0303131号及第2009/0068790号揭露一种封装基板上堆叠多个晶片的半导体组件,各该晶片通过如导电胶的导电元件与封装基板上的焊指垫电性连接。另一方面,由于为使封装基板的最外层能充分利用布线空间,于最外层的焊指垫的周围仍布设有线路,因此必须以如绿漆的阻焊层(solder mask layer)同时覆盖于该线路与焊指垫的部分表面上,并于该阻焊层中形成有外露部分焊指垫的阻焊层开孔,以通过该阻焊层用以保护最外线路层及焊指垫部分表面不受外界环境的空气与水气影响而氧化。然而,如图1A及1B所示,当封装基板表面产生凹陷120时,例如相邻线路之间或相邻焊指垫之间的阻焊层表面产生凹陷时,容易使导电胶流至凹陷处,而导致因桥接而短路。US Patent No. 2008/0303131 and No. 2009/0068790 disclose a semiconductor device in which a plurality of chips are stacked on a packaging substrate. Each chip is electrically connected to a pad on the packaging substrate through a conductive element such as conductive glue. On the other hand, in order to make full use of the wiring space on the outermost layer of the package substrate, there are still wiring lines around the outermost solder finger pads, so it is necessary to use a solder mask layer such as green paint at the same time. Covering part of the surface of the circuit and the solder finger pad, and forming a solder mask opening in the solder mask layer that exposes part of the solder finger pad, so as to pass through the solder mask layer to protect the outermost circuit layer and solder finger The surface of the pad part is not oxidized by the air and moisture in the external environment. However, as shown in FIGS. 1A and 1B , when a
请参阅图1A及1B所示的封装基板俯视图及其覆盖阻焊层的剖视示意图,该封装基板10的至少一表面设有线路层11,而该线路层11具有多个焊指垫110,此外,各该焊指垫110各别延设有线路112,且至少一对相邻的两焊指垫110a、110b之间设线路112a;如图1B所示,在该封装基板10及线路层11上覆盖有阻焊层12。Please refer to the top view of the package substrate and the schematic cross-sectional view of the
但是,上述的覆盖有阻焊层12的封装基板10,该封装基板10表面上的各该线路112之间的间距有大有小(如线段D1及D2),当该阻焊层12覆盖于该封装基板10上后,且该阻焊层12经加热固化后,该阻焊层12内部溶剂挥发,导致该阻焊层12外露的表面(线段D1)产生凹陷120,尤其是该线路112之间的间距越大的情况,该阻焊层12表面收缩后所产生的凹陷120越明显,因而该阻焊层12外露的表面不平整,而不利于后续进行封装或容易使导电胶流至凹陷处,而导致因桥接而短路。However, in the
鉴此,美国专利第6,692,988号揭露一种能减缓阻焊层表面产生凹陷的封装基板。In view of this, US Patent No. 6,692,988 discloses a packaging substrate capable of slowing down the sinking on the surface of the solder mask layer.
请参阅图2A及2B,为上述美国专利案第6,692,988号的封装基板俯视图及其覆盖阻焊层的剖视示意图。如图2A所示,是在一封装基板10的至少一表面设有线路层11,而该线路层11具有多个焊指垫110,此外,各该焊指垫110个别延设有线路112,且于两相邻的线路112a、112b之间设有至少一假线路(dummy traces)112c。如图2B所示,在该封装基板10及线路层11上覆盖有阻焊层12;从而能通过这些假线路112c将相对应覆盖的阻焊层12垫高,以令该阻焊层12的外露表面能保持较佳的平整性。Please refer to FIGS. 2A and 2B , which are a top view of the package substrate of the above-mentioned US Patent No. 6,692,988 and a schematic cross-sectional view of the solder resist layer covering it. As shown in FIG. 2A, a
但是,在高密度布线的要求下,虽这些线路112之间能通过该假线路112c将该相对应覆盖的阻焊层12垫高,但这些焊指垫110之间的间距缩小,却无法令该假线路112c穿过两相邻的焊指垫110之间,导致这些焊指垫110之间的阻焊层12容易产生凹陷,再加上这些相邻焊指垫110之间的间距过小,因而容易使导电胶113流至凹陷处,如图2C所示,而导致因桥接而短路的情况。However, under the requirement of high-density wiring, although the
因此,如何提供一种电路板结构及其制法,能避免外部电性连接结构因桥接而产生短路的情况,且能应用于细间距的产品,实为一重要课题。Therefore, how to provide a circuit board structure and its manufacturing method, which can avoid the short circuit of the external electrical connection structure due to bridging, and can be applied to products with fine pitches, is an important issue.
发明内容Contents of the invention
鉴于上述现有技术的种种缺失,本发明提供一种电路板结构,包括:层状本体;线路层,形成于该层状本体表面,且该线路层具有多个焊指垫及连接该焊指垫的导电迹线,其中,任两相邻的焊指垫的至少其中之一向相邻焊指垫延伸有突出部;以及阻焊层,形成于该层状本体、导电迹线、焊指垫及突出部上,且该阻焊层具有多个开口,以外露各该焊指垫的部分表面。In view of the various deficiencies of the above-mentioned prior art, the present invention provides a circuit board structure, comprising: a layered body; a circuit layer formed on the surface of the layered body, and the circuit layer has a plurality of welding finger pads and connecting the welding fingers conductive traces of pads, wherein at least one of any two adjacent pads has a protrusion extending toward the adjacent pad; and a solder resist formed on the layered body, conductive traces, finger pads and the protruding portion, and the solder resist layer has a plurality of openings exposing part of the surface of each of the pads.
本发明进一步提供一种电路板结构的制法,包括:提供一层状本体;通过图案化制造方法在该层状本体表面形成线路层,该线路层具有多个焊指垫及连接该焊指垫的导电迹线,其中,任两个相邻焊指垫的至少其中之一向相邻焊指垫延伸有突出部;以及于该层状本体、导电迹线、焊指垫及突出部上覆盖阻焊层,且令该阻焊层中形成多个开口,以外露各该焊指垫的部分表面。The present invention further provides a method for manufacturing a circuit board structure, comprising: providing a layered body; forming a circuit layer on the surface of the layered body by a patterned manufacturing method, the circuit layer having a plurality of welding finger pads and connecting the welding fingers Conductive traces of pads wherein at least one of any two adjacent finger pads has a protrusion extending toward the adjacent finger pad; and overlying the layered body, conductive trace, finger pad and protrusion A solder resist layer is formed, and a plurality of openings are formed in the solder resist layer to expose part of the surface of each solder finger pad.
依上述的电路板结构及其制法,该层状本体可为具有内层线路的线路板。According to the above-mentioned circuit board structure and its manufacturing method, the layered body can be a circuit board with inner-layer circuits.
此外,在一实施例中,该两相邻焊指垫皆延伸有突出部,且该突出部交错对应。这些突出部为交错对应。此外,本发明的电路板结构及其制法并未限制突出部外型,但通常该突出部可为矩形、三角形、半圆形或椭圆形。In addition, in one embodiment, protrusions are extended from the two adjacent pads, and the protrusions correspond alternately. These projections are in staggered correspondence. In addition, the circuit board structure and its manufacturing method of the present invention do not limit the shape of the protruding part, but generally the protruding part can be rectangular, triangular, semicircular or elliptical.
由上可知,本发明电路板结构及其制法,是在任两相邻的焊指垫之间的层状本体表面上使至少一焊指垫延伸有突出部,从而令后续形成的阻焊层表面保持平整,避免导电元件形成于焊指垫后因阻焊层表面产生凹陷,导致导电元件桥接而短路的情况,更能确保视需要的增层结构品质良好,进而能应用于细间距的产品。It can be seen from the above that the circuit board structure and its manufacturing method of the present invention are to make at least one solder finger pad extend with a protrusion on the surface of the layered body between any two adjacent solder finger pads, so that the subsequently formed solder resist layer The surface is kept flat to prevent conductive elements from forming on the solder finger pads due to depressions on the surface of the solder mask layer, resulting in bridging and short-circuiting of conductive elements. It can also ensure that the required build-up structure is of good quality, and can be applied to fine-pitch products. .
附图说明 Description of drawings
图1A至1B为现有封装基板俯视图及其覆盖阻焊层的剖视示意图,其中,图1B为图1A的1B-1B剖面线的剖视图;1A to 1B are schematic cross-sectional views of a top view of an existing package substrate and its covering solder resist layer, wherein, FIG. 1B is a cross-sectional view of the
图2A至2B为美国专利第6,692,988号的封装基板的俯视图及其剖视示意图,其中,图2B为图2A的2B-2B剖面线在线段D3的剖视图;2A to 2B are top views and schematic cross-sectional views of the package substrate of US Patent No. 6,692,988, wherein, FIG. 2B is a cross-sectional view of the line segment D3 of the
图2C显示图2A的2C-2C剖面线发生导电胶桥接的剖视图;以及FIG. 2C shows a cross-sectional view of conductive glue bridging on
图3A至4B为本发明的电路板结构及其制法的示意图,其中,图3A是图3B-1在3A-3A剖面线的剖视图;图3B-1至3B-4为不同突出部外型的实施例俯视图;以及图4B为图4A的俯视图。3A to 4B are schematic diagrams of the circuit board structure of the present invention and its manufacturing method, wherein, FIG. 3A is a cross-sectional view of FIG. 3B-1 at the
主要元件符号说明Explanation of main component symbols
10 封装基板10 Package Substrate
11 线路层11 Line layer
110、110a、110b 焊指垫110, 110a, 110b Welding finger pads
112、112a、122b 线路112, 112a, 122b lines
112c 假线路112c false line
113 导电胶113 Conductive adhesive
12 阻焊层12 Solder mask
120 凹陷120 Depression
20 层状本体20 Layered ontology
20a 表面20a Surface
21 线路层21 Line layer
210 焊指垫210 Welding finger pad
211a、211b、211c、211d 突出部211a, 211b, 211c, 211d protrusions
212 导电迹线212 Conductive traces
22 阻焊层22 Solder mask
220 开口220 opening
具体实施方式 Detailed ways
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. Limiting conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should still fall within the scope of the present invention. The disclosed technical content must be within the scope covered.
请参阅图3A至4B,为本发明所揭露的一种电路板结构的制法。Please refer to FIGS. 3A to 4B , which illustrate a manufacturing method of a circuit board structure disclosed by the present invention.
如图3A及3B-1所示,首先,提供一层状本体20,该层状本体20可为具有内层线路的线路板,该线路板可为封装基板。通过图案化制造方法在该层状本体20表面20a形成线路层21,该线路层21具有多个焊指垫210及连接该焊指垫210的导电迹线212,该导电迹线212可与层状本体20的内层线路电性连接。此外,如图3B-1所示,任两相邻的焊指垫210的至少其中之一向相邻焊指垫210延伸有突出部211a。或者,如图3B-2至3B-4所示该两相邻焊指垫210皆延伸有突出部211b、211c及211d,且该突出部211b、211c及211d交错对应。此外,该突出部可为任意外型,例如其中,该突出部211a(或211b)为矩形,如图3B-1及3B-2所示;或该突出部211c为三角形,如图3B-3所示;或该突出部211d为半圆形或椭圆形,如图3B-4所示。As shown in FIGS. 3A and 3B-1 , firstly, a
如图4A及4B所示,在该层状本体20、导电迹线212、焊指垫210及突出部211a(211b、211c或211d)上覆盖阻焊层22,且令该阻焊层22中形成多个开口220,以外露各该焊指垫210的部分表面对应外露于各该开口220,而这些突出部211a(211b、211c或211d)位于两相邻的焊指垫210之间,从而令该突出部211a(211b、211c或211d)将该阻焊层22垫高,以令该阻焊层22对应这些突出部211a(211b、211c或211d)的外露表面与其它外露表面保持平整,因而避免该阻焊层22的外露表面产生凹陷,而导致后续制造方法中因导电胶桥接而短路的情况,进而能应用于细间距的产品。As shown in FIGS. 4A and 4B , the
本发明进一步提供一种电路板结构,包括:层状本体20;线路层21,形成于该层状本体20表面20a,且该线路层21具有多个焊指垫210及连接该焊指垫210的导电迹线212,其中,任两相邻的焊指垫210的至少其中之一向相邻焊指垫210延伸有突出部211a(211b、211c或211d);以及阻焊层22,形成于该层状本体20、导电迹线212、焊指垫210及突出部211a(211b、211c或211d)上,且该阻焊层22具有多个开口220,以外露各该焊指垫210的部分表面。The present invention further provides a circuit board structure, comprising: a
依上述的电路板结构,该层状本体20可为具有内层线路的线路板,该线路板可为封装基板。此外,该线路层的导电迹线可与层状本体的内层线路电性连接。According to the above-mentioned circuit board structure, the
在一具体实施例中,该两相邻焊指垫210皆延伸有突出部211b、211c或211d,且该突出部211b、211c或211d为交错对应,如图3B-2至3B-4所示。此外,该突出部可为矩形、三角形、半圆形或椭圆形,但不以此为限。In a specific embodiment, the two
本发明电路板结构及其制法,是在该层状本体的至少一表面的线路层形成有多个焊指垫,而任两相邻的焊指垫的至少其中之一向相邻焊指垫延伸有突出部,且在该层状本体、导电迹线、焊指垫及突出部上覆盖一阻焊层,而该阻焊层中形成多个开口,以令各该焊指垫对应外露于各该开口,从而令这些突出部位于任两相邻的焊指垫之间,使该阻焊层对应这些突出部的外露表面与其它外露表面保持平整,避免导电元件形成于焊指垫后因阻焊层表面产生凹陷,导致导电元件桥接而短路的情况,更能确保视需要的增层结构品质良好,进而能应用于细间距的产品。The circuit board structure and its manufacturing method of the present invention are that a plurality of welding finger pads are formed on the circuit layer on at least one surface of the layered body, and at least one of any two adjacent welding finger pads is directed toward the adjacent welding finger pads. a protruding part is extended, and a solder resist layer is covered on the layered body, conductive traces, solder finger pads and protruding part, and a plurality of openings are formed in the solder resist layer, so that each of the solder finger pads is correspondingly exposed to the Each of the openings, so that these protrusions are located between any two adjacent solder finger pads, so that the exposed surface of the solder resist layer corresponding to these protrusions is kept flat with other exposed surfaces, so as to prevent conductive elements from being formed on the solder finger pads. Depressions on the surface of the solder resist layer lead to bridging and short-circuiting of conductive elements, which can ensure good quality of the build-up structure as required, and can be applied to fine-pitch products.
上述实施例是用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如本专利的权利要求书所列。The above-mentioned embodiments are used to illustrate the principles and effects of the present invention, but not to limit the present invention. Any person skilled in the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be as listed in the claims of this patent.
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US6692988B2 (en) * | 2001-08-27 | 2004-02-17 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a substrate-based semiconductor package without mold flash |
CN1708207A (en) * | 2004-06-04 | 2005-12-14 | 英业达股份有限公司 | Method to prevent tin overflow between pads of circuit board |
CN101609817A (en) * | 2008-06-19 | 2009-12-23 | 矽品精密工业股份有限公司 | Semiconductor packaging device, semiconductor packaging structure and manufacturing method thereof |
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Application publication date: 20120404 |