CN102394639A - Method to realize arbitrary-number frequency dividing of servo driver and arbitrary-number frequency divider based on field programmable gate array (FPGA) - Google Patents
Method to realize arbitrary-number frequency dividing of servo driver and arbitrary-number frequency divider based on field programmable gate array (FPGA) Download PDFInfo
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Abstract
The invention discloses a method to realize arbitrary-number frequency dividing of servo driver and arbitrary-number frequency divider based on field programmable gate array (FPGA), wherein the method comprises the following steps: filtering feedback pulse signals of an A phase and a B phase; carrying out quadrature pulse decoding on the A phase and B phase signals after being filtered, and outputting quadrature pulse direction and quadrature encoding pulses; counting according to the quadrature pulse direction and the quadrature encoding pulses; carrying out multiplication on the counting valve and the numerator of a frequency dividing ratio, storing the result in a dividend register, and storing the denominator of the frequency dividing ratio in a divisor register; calling a divider, and storing the quotient value in a register; comparing the quotient value with a quotient value at the front and adjacent to the quotient value, and judging whether the quotient value changes, if so, outputting a pulse high-arrangement level, and if not, outputting pulse low-arrangement level; and inputting the outputting pulses and the quadrature pulse direction into a pulser, and generating frequency-divided pulses by the pulser. The method has the advantages of having small occupied resources, being capable of accurately tracking frequency of two paths of encoder feedback pulses, pulse numbers, pulse phases and the like.
Description
Technical field
The present invention relates to servo-drive and dividing method technical field, relate to a kind of arbitrary number dividing method of servo-driver and arbitrary number frequency divider of realizing based on FPGA of being applied in particular.
Background technology
At present, servo-driver is widely used in the industrial automation field, and all can use the frequency division output of encoder feedback pulse in most occasions of using servo-driver.The pulse of frequency division output generally can be linked in the control system, and control system can be carried out the control of machine action according to the feedback pulse number that receives.So the frequency division output of encoder feedback pulse is quite important, it is related to control system and even can entire machine the correct execution action.
In present servo-driver, foreign brand name generally have an arbitrary number frequency division, and homemade servo major part all also only has integral frequency divisioil, but the integral frequency divisioil application scenario is limited.Shortcomings such as the frequency that yet has frequency division that part has the arbitrary number frequency division is even inadequately, and pulse number is accurate inadequately.The encoder feedback pulse of servo-driver has the frequency uncertainty, pulse number is uncertain; And be the two-way orthogonal pulses; But its frequency division output pulse must be according to accurate output pulse frequency of frequency dividing ratio and pulse number; And anything but accumulated error can be arranged, must guarantee that also the two-way pulse of output keeps quadrature phase.This has proposed higher requirement to its frequency division algorithm.
In present existing frequency splitting technology, having much is that frequency division is carried out in the pulse that is directed against single-frequency, and the pulse of output is only required that frequency is even, and the requirement of pulse number is not fairly simple certainly, mainly contains the phase-locked loop method, linear interpolation etc.The frequency splitting technology of in servo-driver, using mainly contains based on the integral frequency divisioil of counter with based on the preposition fractional frequency division of bimodulus at present, generally all is in FPGA, to realize.
Integral frequency divisioil is divided into even frequency division and frequency division by odd integers, generally adopts counter to realize.When carrying out even frequency division, to the rising edge of input pulse counting, when Counter Value from 0 to N/2-1 the time, the output impulse level overturns, and counter is resetted, counter counts from zero.Circulation just can obtain needed even frequency division pulse so repeatedly.When carrying out frequency division by odd integers, to the rising edge of input pulse counting, when Counter Value from 0 during to (N-1)/2, the output impulse level overturns, and produces one tunnel output pulse.Trailing edge to input pulse is also counted, when Counter Value from 0 during to (N-1)/2, the output impulse level overturns, and produces another road output pulse.The phase exclusive disjunction is carried out in the pulse that produces this two-way then, just can obtain needed frequency division by odd integers pulse.
Fractional frequency division generally adopts the preposition method of bimodulus to realize.The preposition method of bimodulus is exactly to make output pulse every at a distance from a several cycles many outputs pulse according to frequency division numerical value at several input pulses in the cycle, obtains a fractional frequency division ratio thereby make on the output pulse population mean meaning.The divided pulse phase jitter of this method output is bigger, and the output pulse duty factor is inhomogeneous.When servomotor rotates for a long time repeatedly, also have bigger accumulated error.Work as decimal place more in addition, can take very many FPGA resources, can not realize basically from reality.
In sum, the major defect of frequency splitting technology scheme has at present: the one, and scheme realizes complicated, algorithm is realized difficulty.The 2nd, the pulse frequency shake of frequency division output is big, and duty ratio is inhomogeneous.The 3rd, accumulated error is arranged, can cause the control system misjudgment of received pulse, finally cause machine malfunction.The 4th, the stock number that takies FPGA is bigger, particularly during fractional frequency division, under the more situation of decimal digits, almost is difficult to realize.
Summary of the invention
Deficiency in view of prior art the object of the present invention is to provide a kind of arbitrary number dividing method that can be applied to servo-driver, and can be based on the arbitrary number frequency divider of FPGA realization.It has realizes simply, and it is few to take resource, frequency that can the pulse of accurate tracking two-way encoder feedback, umber of pulse, impulse phase etc.
Technical scheme of the present invention is: a kind of arbitrary number dividing method of realizing servo-driver based on FPGA is provided, comprises the steps:
110, A phase, B are fed back pulse signal mutually and carry out filtering;
120, filtered A phase, B phase signals are carried out the orthogonal pulses decoding, and output orthogonal pulse direction and quadrature decoder pulse;
130, count according to orthogonal pulses direction and quadrature decoder pulse;
140 130 count values that draw of step and the molecule of frequency dividing ratio multiply each other, and with the accumulating into the dividend register of gained, deposit the denominator of frequency dividing ratio except that number register in;
150 call divider calculates, and deposits the gained quotient in register;
160, the 150 step gained quotients quotient adjacent with this quotient front compared, judge whether 150 step gained quotients change, if this quotient changes, high level is put in the output pulse; If this quotient does not change, low level is put in the output pulse;
Output pulse of 170 160 steps and 120 step orthogonal pulses directions are input to pulse generator simultaneously, and pulse generator can produce the pulse behind the frequency division according to logical sequence.
As to improvement of the present invention, said step 120 further comprises:
121 power-up initializings are quadrature decoder pulse and the zero setting of orthogonal pulses direction;
122 when A phase input pulse level be high, then quadrature decoder pulse output level be a height, the orthogonal pulses direction puts 1, and entering step 123; When B phase input pulse level is high, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 125;
123 when B phase input pulse level be high, then quadrature decoder pulse output level be a height, the orthogonal pulses direction puts 1, and entering step 124; When A phase input pulse level is low, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 122;
124 when A phase input pulse level be low, then quadrature decoder pulse output level be high, the orthogonal pulses direction puts 1, and entering step 125; When B phase input pulse level is low, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 123;
125 when B phase input pulse level be low, then quadrature decoder pulse output level be high, the orthogonal pulses direction puts 1, and entering step 122; When A phase input pulse level is high, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 124.
As to improvement of the present invention, said step 170 further comprises:
171 power-up initializings are put output orthogonal pulse OA and OB level low;
172 output orthogonal pulse OA and OB level are put low, when input pulse is high level and orthogonal pulses direction during also for high level, then get into step 173; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 175;
173 output orthogonal pulse OA level are put height, and the OB level is put low; When input pulse is high level and orthogonal pulses direction during also for high level, then get into step 174; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 172;
174 output orthogonal pulse OA level are put height, and the OB level is put height; When input pulse is high level and orthogonal pulses direction during also for high level, then get into step 175; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 173;
It is low that 175 output orthogonal pulse OA level are put, and the OB level is put height; When input pulse is high level and orthogonal pulses direction during also for high level, then get into step 172; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 174.
The present invention also provides a kind of arbitrary number frequency divider of realizing based on FPGA, comprising: signal filtering unit, quadrature decoder unit, step-by-step counting unit, multiplier unit, divider unit, numerical value discriminating unit, pulse generation unit; Wherein:
Said signal filtering unit is used for carrying out filtering to A phase input pulse signal, B phase input pulse signal, interference signals such as filtering spike;
Said quadrature decoder unit is used for carrying out quadrature decoder to filtered A phase, B phase signals output orthogonal decode pulses and orthogonal pulses direction signal;
Said step-by-step counting unit is used for counting according to quadrature decoder pulse and orthogonal pulses signal, and count value is saved in register;
Said multiplier unit is used for multiplying each other the molecule of pulse count value and frequency dividing ratio, and is saved in the dividend register to value;
Said divider unit is used for being divided by the denominator of multiplier output valve and frequency dividing ratio, and is saved in register to quotient;
Said numerical value discriminating unit is used to differentiate whether quotient changes; If change, then export high level; If no change, then output low level;
Said pulse generation unit, the orthogonal pulses behind the two-way frequency division that is used for generating according to orthogonal pulses direction and numerical value discriminating unit output pulse.
As the improvement to above-mentioned arbitrary number frequency divider, said quadrature decoder unit comprises: state machine initialization unit, state machine first state cell, state machine second state cell, state machine third state unit, state machine four condition unit; Wherein:
Said state machine initialization unit is used for the initial value of init state machine and pulse of initialization quadrature decoder and orthogonal pulses direction;
Said state machine first state cell, be used for judging when the A phase signals for high perhaps when the B phase signals is high, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine;
Said state machine second state cell, be used for judging when the A phase signals for low perhaps when the B phase signals is high, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine;
Said state machine third state unit, be used for judging when the A phase signals for low or B phase signals when hanging down, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine;
Said state machine four condition unit, be used for judging when the A phase signals for high or B phase signals when hanging down, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine.
As the improvement to above-mentioned arbitrary number frequency divider, said pulse generation unit comprises: state machine initialization unit, state machine first state cell, state machine second state cell, state machine third state unit, state machine four condition unit; Wherein:
Said state machine initialization unit is used for the initial value of init state machine and the original levels of initialization two-way output orthogonal pulse OA and OB;
Said state machine first state cell, it is low being used for output orthogonal pulse OA level, the OB level is low; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change;
Said state machine second state cell is used for output orthogonal pulse OA level for high, and the OB level is low; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change;
Said state machine first state cell is used for output orthogonal pulse OA level for high, and the OB level is high; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change;
Said state machine first state cell, it is low being used for output orthogonal pulse OA level, the OB level is high; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change.
Arbitrary number dividing method that can be applied to servo-driver provided by the invention and the arbitrary number frequency divider of realizing based on FPGA, scheme is simple, realizes being easier to; It is few to take the FPGA resource, and can be in the frequent acceleration and deceleration of servomotor, repeatedly under the situation such as rotating; Can follow the tracks of the output frequency of encoder feedback pulse according to frequency dividing ratio accurately; Output phase and output pulse number, and the impulse phase delay of pulse behind the frequency division and encoder output is very little, and real-time is fine.When the pulse behind the frequency division was input to control system, control system just can be known the position and the speed of servomotor in real time accurately, and control system just can be sent correct action command like this, and can guarantee that the machining accuracy of complete machine is higher.The present invention and traditional dividing method are compared, and having abandoned conventional method need be divided into integer and decimal with frequency dividing ratio, the thinking of implementing respectively then; But adopted multiplier, divider, pulse generator etc.; Only need the molecule and the denominator of input frequency division, it is accurate just can to obtain output frequency, and output phase is consistent; The output pulse number is the two-way orthogonal pulses accurately, and it is inaccurate fundamentally to have overcome the output frequency in the conventional method, and output phase changes greatly; The shortcoming that the output pulse number has influence such as cumulative errors to use in practical application, has advantage undoubtedly more.
Description of drawings
Fig. 1 is the detailed process sketch map that the present invention is applied to the arbitrary number dividing method of servo-driver;
Fig. 2 carries out the orthogonal pulses decoding to filtered A phase, B phase signals among Fig. 1, and the detailed process sketch map of output orthogonal pulse direction and quadrature decoder pulse;
Fig. 3 is input to pulse generator to 160 output pulses and 120 orthogonal pulses directions among Fig. 1 simultaneously, and pulse generator can produce the detailed process sketch map of the pulse behind the frequency division according to logical sequence;
Fig. 4 is the structural representation that the present invention is based on the arbitrary number frequency divider of FPGA realization.
Embodiment
The embodiment of the invention provides a kind of can be applied to the arbitrary number dividing method of servo-driver and the arbitrary number frequency divider of realizing based on FPGA.Its principle is when the multiple of encoder pulse count value and frequency dividing ratio changes, and its quotient that is divided by also must change, and this moment just can be according to the direction of the variation of quotient and orthogonal pulses and the output frequency division pulse.
The embodiment of the invention provides a kind of dividing method that is different from conventional thought.For servo-driver; Be not only that preceding frequency of frequency division and the frequency behind the frequency division are keeping frequency dividing ratio multiple relation; And preceding umber of pulse and the umber of pulse behind the frequency division of frequency division also will keep the frequency dividing ratio multiple to concern that the impulse phase behind the frequency division also will be consistent with the impulse phase before the frequency division.The rotation of servomotor is very irregular; Frequent acceleration and deceleration and rotating repeatedly; So the frequency of encoder feedback pulse, phase place, pulse number also are in the variation at any time; And these information of encoder pulse all can real-time embodying on its counted number of pulses, we just parse pulse frequency, phase place, pulse number information behind the frequency division from its counted number of pulses so.When its counted number of pulses divided by frequency dividing ratio after, its quotient has comprised the pulse number behind the frequency division respectively, the pulse frequency information behind the frequency division.Utilize the pulse and the pulse orthogonal direction driven in common trigger generator that detect the quotient variation and generate again, so just can reconstruct two-way fully and keep quadrature phase, the accurate divided pulse of pulse number and pulse frequency.
The embodiment of the invention provides a kind of arbitrary number dividing method that can be applied to servo-driver, and is as shown in Figure 1, comprising:
110, A phase, B are fed back pulse signal mutually and carry out filtering;
120, filtered A phase, B phase signals are carried out the orthogonal pulses decoding, and output orthogonal pulse direction and quadrature decoder pulse;
130, count according to orthogonal pulses direction and quadrature decoder pulse;
140, multiply each other the molecule of above-mentioned count value and frequency dividing ratio, and deposit the dividend register in, deposit the denominator of frequency dividing ratio except that number register in;
150, call divider, and deposit the merchant in register;
160, judge whether quotient changes, if quotient changes, high level is put in the output pulse; If quotient does not change, low level is put in the output pulse;
170, be input to pulse generator to 160 output pulses and 120 orthogonal pulses directions simultaneously, pulse generator can produce the pulse behind the frequency division according to logical sequence;
Wherein, as shown in Figure 2 in a further embodiment, this figure carries out the orthogonal pulses decoding to filtered A phase, B phase signals among Fig. 1, and the detail flowchart of output orthogonal pulse direction and quadrature decoder pulse (step 120):
This step 120 further comprises:
121, power-up initializing is quadrature decoder pulse and the zero setting of orthogonal pulses direction;
122, when A phase input pulse level be high, then quadrature decoder pulse output level be high, the orthogonal pulses direction puts 1, and entering step 123; When B phase input pulse level is high, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 125;
123, when B phase input pulse level be high, then quadrature decoder pulse output level be high, the orthogonal pulses direction puts 1, and entering step 124; When A phase input pulse level is low, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 122;
124, when A phase input pulse level be low, then quadrature decoder pulse output level is high, the orthogonal pulses direction puts 1, and gets into step 125; When B phase input pulse level is low, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 123;
125, when B phase input pulse level be low, then quadrature decoder pulse output level is high, the orthogonal pulses direction puts 1, and gets into step 122; When A phase input pulse level is high, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 124;
Wherein, as shown in Figure 3 in a further embodiment, be to be input to pulse generator to 160 output pulses and 120 orthogonal pulses directions simultaneously among Fig. 1, pulse generator can produce the detail flowchart of the pulse (step 170) behind the frequency division according to logical sequence,
This step 170 further comprises:
171, power-up initializing is put output orthogonal pulse OA and OB level low;
172, put output orthogonal pulse OA and OB level low,, then get into step 173 when input pulse is high level and orthogonal pulses direction during also for high level; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 175;
173, put height to output orthogonal pulse OA level, the OB level is put low; When input pulse is high level and orthogonal pulses direction during also for high level, then get into step 174; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 172;
174, put height to output orthogonal pulse OA level, the OB level is put height; When input pulse is high level and orthogonal pulses direction during also for high level, then get into step 175; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 173;
175, put output orthogonal pulse OA level low, the OB level is put height; When input pulse is high level and orthogonal pulses direction during also for high level, then get into step 172; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 174;
The embodiment of the invention also provides a kind of frequency divider of realizing based on FPGA; As shown in Figure 4; It comprises: signal filtering unit 100, quadrature decoder unit 200, step-by-step counting unit 300, multiplier unit 400, divider unit 500, numerical value discriminating unit 600, pulse generation unit 700; Wherein:
Said signal filtering unit 100 is used for carrying out filtering to A phase input pulse signal, B phase input pulse signal, interference signals such as filtering spike;
Said quadrature decoder unit 200 is used for carrying out quadrature decoder to filtered A phase, B phase signals output orthogonal decode pulses and orthogonal pulses direction signal;
Said step-by-step counting unit 300 is used for counting according to quadrature decoder pulse and orthogonal pulses signal, and count value is saved in register;
Said multiplier unit 400 is used for multiplying each other the molecule of pulse count value and frequency dividing ratio, and is saved in the dividend register to value;
Said divider unit 500 is used for being divided by the denominator of multiplier output valve and frequency dividing ratio, and is saved in register to quotient;
Said numerical value discriminating unit 600 is used to differentiate whether quotient changes; If change, then export high level; If no change, then output low level;
Said pulse generation unit 700, the orthogonal pulses behind the two-way frequency division that is used for generating according to orthogonal pulses direction and numerical value discriminating unit output pulse.
Further among the embodiment, as shown in Figure 4, said quadrature decoder unit 200 comprises:
State machine initialization unit 201, state machine first state cell 202, state machine second state cell 203, state machine third state unit 204, state machine four condition unit 205; Wherein:
Said state machine initialization unit 201 is used for the initial value of init state machine and pulse of initialization quadrature decoder and orthogonal pulses direction;
Said state machine first state cell 202, be used for judging when the A phase signals for high perhaps when the B phase signals is high, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine;
Said state machine second state cell 203, be used for judging when the A phase signals for low perhaps when the B phase signals is high, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine;
Said state machine third state unit 204, be used for judging when the A phase signals for low or B phase signals when hanging down, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine;
Said state machine four condition unit 205, be used for judging when the A phase signals for high or B phase signals when hanging down, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine.
Further among the embodiment, as shown in Figure 4, said pulse generation unit 700 comprises:
State machine initialization unit 701, state machine first state cell 702, state machine second state cell 703, state machine third state unit 704, state machine four condition unit 705; Wherein:
Said state machine initialization unit 701 is used for the initial value of init state machine and the original levels of initialization two-way output orthogonal pulse OA and OB;
Said state machine first state cell 702, it is low being used for output orthogonal pulse OA level, the OB level is low; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change;
Said state machine second state cell 703 is used for output orthogonal pulse OA level for high, and the OB level is low; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change;
Said state machine first state cell 704 is used for output orthogonal pulse OA level for high, and the OB level is high; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change;
Said state machine first state cell 705, it is low being used for output orthogonal pulse OA level, the OB level is high; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change.
Should be understood that, concerning those of ordinary skills, can improve or conversion, and all these improvement and conversion all should belong to the protection range of accompanying claims of the present invention according to above-mentioned explanation.
Claims (6)
1. the arbitrary number dividing method based on FPGA realization servo-driver is characterized in that, comprising:
110, A phase, B are fed back pulse signal mutually and carry out filtering;
120, filtered A phase, B phase signals are carried out the orthogonal pulses decoding, and output orthogonal pulse direction and quadrature decoder pulse;
130, count according to orthogonal pulses direction and quadrature decoder pulse;
140 130 count values that draw of step and the molecule of frequency dividing ratio multiply each other, and with the accumulating into the dividend register of gained, deposit the denominator of frequency dividing ratio except that number register in;
150 call divider calculates, and deposits the gained quotient in register;
160, the 150 step gained quotients quotient adjacent with this quotient front compared, judge whether 150 step gained quotients change, if this quotient changes, high level is put in the output pulse; If this quotient does not change, low level is put in the output pulse;
Output pulse of 170 160 steps and 120 step orthogonal pulses directions are input to pulse generator simultaneously, and pulse generator can produce the pulse behind the frequency division according to logical sequence.
2. according to the said arbitrary number dividing method of claim 1, it is characterized in that said step 120 further comprises:
121 power-up initializings are quadrature decoder pulse and the zero setting of orthogonal pulses direction;
122 when A phase input pulse level be high, then quadrature decoder pulse output level be a height, the orthogonal pulses direction puts 1, and entering step 123; When B phase input pulse level is high, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 125;
123 when B phase input pulse level be high, then quadrature decoder pulse output level be a height, the orthogonal pulses direction puts 1, and entering step 124; When A phase input pulse level is low, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 122;
124 when A phase input pulse level be low, then quadrature decoder pulse output level be high, the orthogonal pulses direction puts 1, and entering step 125; When B phase input pulse level is low, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 123;
125 when B phase input pulse level be low, then quadrature decoder pulse output level be high, the orthogonal pulses direction puts 1, and entering step 122; When A phase input pulse level is high, then quadrature decoder pulse output level is high, and the orthogonal pulses direction puts 0, and gets into step 124.
3. according to the said arbitrary number dividing method of claim 1, it is characterized in that said step 170 further comprises:
171 power-up initializings are put output orthogonal pulse OA and OB level low;
172 output orthogonal pulse OA and OB level are put low, when input pulse is high level and orthogonal pulses direction during also for high level, then get into step 173; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 175;
173 output orthogonal pulse OA level are put height, and the OB level is put low; When input pulse is high level and orthogonal pulses direction during also for high level, then get into step 174; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 172;
174 output orthogonal pulse OA level are put height, and the OB level is put height; When input pulse is high level and orthogonal pulses direction during also for high level, then get into step 175; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 173;
It is low that 175 output orthogonal pulse OA level are put, and the OB level is put height; When input pulse is high level and orthogonal pulses direction during also for high level, then get into step 172; When input pulse is high level and orthogonal pulses direction when being low level, then get into step 174.
4. an arbitrary number frequency divider of realizing based on FPGA is characterized in that, comprising: signal filtering unit, quadrature decoder unit, step-by-step counting unit, multiplier unit, divider unit, numerical value discriminating unit, pulse generation unit; Wherein:
Said signal filtering unit is used for carrying out filtering to A phase input pulse signal, B phase input pulse signal, interference signals such as filtering spike;
Said quadrature decoder unit is used for carrying out quadrature decoder to filtered A phase, B phase signals output orthogonal decode pulses and orthogonal pulses direction signal;
Said step-by-step counting unit is used for counting according to quadrature decoder pulse and orthogonal pulses signal, and count value is saved in register;
Said multiplier unit is used for multiplying each other the molecule of pulse count value and frequency dividing ratio, and is saved in the dividend register to value;
Said divider unit is used for being divided by the denominator of multiplier output valve and frequency dividing ratio, and is saved in register to quotient;
Said numerical value discriminating unit is used to differentiate whether quotient changes; If change, then export high level; If no change, then output low level;
Said pulse generation unit, the orthogonal pulses behind the two-way frequency division that is used for generating according to orthogonal pulses direction and numerical value discriminating unit output pulse.
5. like the said arbitrary number frequency divider of claim 4, it is characterized in that said quadrature decoder unit comprises: state machine initialization unit, state machine first state cell, state machine second state cell, state machine third state unit, state machine four condition unit; Wherein:
Said state machine initialization unit is used for the initial value of init state machine and pulse of initialization quadrature decoder and orthogonal pulses direction;
Said state machine first state cell, be used for judging when the A phase signals for high perhaps when the B phase signals is high, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine;
Said state machine second state cell, be used for judging when the A phase signals for low perhaps when the B phase signals is high, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine;
Said state machine third state unit, be used for judging when the A phase signals for low or B phase signals when hanging down, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine;
Said state machine four condition unit, be used for judging when the A phase signals for high or B phase signals when hanging down, output orthogonal decode pulses and orthogonal pulses direction, and the state variation of state machine.
6. like the said arbitrary number frequency divider of claim 4, it is characterized in that said pulse generation unit comprises: state machine initialization unit, state machine first state cell, state machine second state cell, state machine third state unit, state machine four condition unit; Wherein:
Said state machine initialization unit is used for the initial value of init state machine and the original levels of initialization two-way output orthogonal pulse OA and OB;
Said state machine first state cell, it is low being used for output orthogonal pulse OA level, the OB level is low; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change;
Said state machine second state cell is used for output orthogonal pulse OA level for high, and the OB level is low; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change;
Said state machine first state cell is used for output orthogonal pulse OA level for high, and the OB level is high; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change;
Said state machine first state cell, it is low being used for output orthogonal pulse OA level, the OB level is high; And judge when the input pulse rising edge triggers, export different state with different orthogonal pulses directions and change.
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| US9059646B2 (en) | 2013-09-12 | 2015-06-16 | Rdc Semiconductor Co., Ltd. | Pulse processor of servo motor system |
| CN104821771A (en) * | 2015-05-21 | 2015-08-05 | 中国科学院自动化研究所 | CPLD (Complex Programmable Logic Device)-based photoelectric encoder orthogonal frequency division method |
| CN106595724A (en) * | 2016-12-02 | 2017-04-26 | 中国科学院自动化研究所 | Incremental encoder frequency-dividing circuit |
| CN109245637A (en) * | 2018-11-16 | 2019-01-18 | 庸博（厦门）电气技术有限公司 | Servo-driver arbitrarily divides output method and servo-driver |
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| CN112653427A (en) * | 2020-12-11 | 2021-04-13 | 深圳市英威腾电气股份有限公司 | Frequency division method, frequency division device and computer readable storage medium |
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| US9059646B2 (en) | 2013-09-12 | 2015-06-16 | Rdc Semiconductor Co., Ltd. | Pulse processor of servo motor system |
| TWI494720B (en) * | 2013-09-12 | 2015-08-01 | Rdc Semiconductor Co Ltd | Pulse processing device applied to servo motor system |
| CN104647331A (en) * | 2015-03-23 | 2015-05-27 | 常州米泽智能装备科技有限公司 | Master-slave follow-up teaching industrial robot system |
| CN104821771A (en) * | 2015-05-21 | 2015-08-05 | 中国科学院自动化研究所 | CPLD (Complex Programmable Logic Device)-based photoelectric encoder orthogonal frequency division method |
| CN104821771B (en) * | 2015-05-21 | 2017-09-22 | 中国科学院自动化研究所 | Photoelectric code disk orthogonal frequency division method based on CPLD |
| CN106595724A (en) * | 2016-12-02 | 2017-04-26 | 中国科学院自动化研究所 | Incremental encoder frequency-dividing circuit |
| CN106595724B (en) * | 2016-12-02 | 2019-07-30 | 中国科学院自动化研究所 | A kind of incremental encoder frequency dividing circuit |
| CN109839064B (en) * | 2017-11-27 | 2021-03-26 | 中国航空工业集团公司西安航空计算技术研究所 | Displacement or angle measurement's grating data acquisition system |
| CN109839064A (en) * | 2017-11-27 | 2019-06-04 | 中国航空工业集团公司西安航空计算技术研究所 | It is a kind of displacement or angle measurement grating data acquisition system |
| CN109245637A (en) * | 2018-11-16 | 2019-01-18 | 庸博（厦门）电气技术有限公司 | Servo-driver arbitrarily divides output method and servo-driver |
| CN110798205A (en) * | 2019-11-14 | 2020-02-14 | 西安微电子技术研究所 | Zero position detection method and system for orthogonal coding pulse signal |
| CN110798205B (en) * | 2019-11-14 | 2023-02-07 | 西安微电子技术研究所 | Zero position detection method and system for orthogonal coding pulse signal |
| CN112653427A (en) * | 2020-12-11 | 2021-04-13 | 深圳市英威腾电气股份有限公司 | Frequency division method, frequency division device and computer readable storage medium |
| CN112653427B (en) * | 2020-12-11 | 2024-05-31 | 深圳市英威腾电气股份有限公司 | Frequency division method, apparatus and computer readable storage medium |
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