CN102386045A - Field emission cathode array with grid control function and manufacturing method thereof - Google Patents

Abstract

The invention relates to a field emission cathode array with a gate control function, which is characterized in that alternate cathodes and grids are arranged on the same plane of a glass substrate, the grid is composed of multiple columns of grid electrodes parallel to each other, and the grid The electrode is composed of a longitudinal electrode and several transverse strips. The cathode is composed of multiple rows of strip cathode electrodes parallel to each other and electron emission layers and dielectric layers are alternately arranged on each strip cathode electrode. Adjacent cathode electrodes with electron emission layers face each other in parallel. The field emission cathode array with gate control function can realize low-voltage control, reduce the open electric field of the field emission cathode array, improve the uniformity and efficiency of electron emission, and has simple structure, easy manufacturing process, low cost and stable manufacturing process Reliable advantages. The invention also discloses a manufacturing method of the field emission cathode array with gate control function.

Description

Field emission cathode array with gate control function and its manufacturing method

technical field

The invention relates to the technical field of manufacturing vacuum microelectronic devices, in particular to a field emission cathode array device with gate regulation and a manufacturing method thereof.

the

Background technique

Field Emission Display (Field Emission Display, FED) is a new type of flat panel display technology. It is an extension of Cathode Ray Tube (CRT) technology. Its working principle is to suppress the surface of objects by a strong external electric field. The potential barrier reduces the height of the potential barrier and narrows the width. When the width of the potential barrier is narrow enough to be comparable to the wavelength of electrons, the electrons penetrate the potential barrier through the tunnel effect and escape into the vacuum to bombard the anode phosphor to emit light.

The field emission cathode array is the core of the field emission display, and the commonly used cathode structures can be divided into two-pole and three-pole structures. Although the manufacturing process of the two-pole field emission cathode is simple, the anode needs high voltage to give electrons enough energy to bombard the phosphor to achieve high brightness. On the other hand, the anode electrode acts as a modulation electrode, and the connection to the driving circuit requires low-voltage modulation, so there is luminous brightness. The irreconcilable contradiction between the modulation voltage and the modulation voltage must introduce a modulation grid on the basis of the diode structure, the voltage is modulated by the grid, and the brightness is controlled by the anode. The three-pole field emission cathode array can be divided into front grid type cathode structure, rear grid type cathode structure and planar type cathode structure according to different positions. The fabrication of the front gate structure is relatively difficult, and requires 3-5 masking processes, and the field emission source is easily damaged during the fabrication process, and the field emission electrons may hit the gate due to the positive voltage applied to the gate and be destroyed. Both interception and cathode emission are sensitive to parameters such as dielectric layer thickness and modulator opening. The gate-back structure is to bury the gate under the cathode, which solves the difficulty of making the front gate structure, but this structure loses the shielding effect of the gate on the anode and makes the cathode vulnerable to ion bombardment, and the anode voltage cannot be too high , otherwise the gate control function is weakened or even transformed into a two-pole FED. Both front-gate and rear-gate field emission displays need to make a cathode-gate insulating layer, and the production of a large-area insulating layer requires high technology, and the insulating performance is difficult to guarantee, so the cost of the device is high, and it is difficult to realize large-area display. The planar structure means that the grid and cathode are on the same plane, the structure is simple to manufacture, and the cost is low, which is very suitable for large-area production and future industrial production.

In the planar cathode structure, the cathode and the grid are located on the same plane, and the cathode and the grid are separated by a vacuum gap. The cathode and the grid can be fabricated on the substrate at one time by using traditional photolithography technology. The perspective view and structural schematic view of the known prior art planar field emission cathode are shown in accompanying drawings 1 and 2 respectively. The planar field emission cathode comprises a cathode substrate 200, a cathode 210 and a grid 220 arranged on the cathode substrate 200, The cathode 210 is composed of a cathode electrode 211 and an electron emission layer 212 disposed on the cathode electrode 211, wherein the cathode 210 and the grid 220 are parallel to each other. However, the turn-on voltage of the traditional planar field emission cathode structure is high. To reduce the operating voltage of the array, the distance between the cathode 210 and the grid 220 must be reduced, which increases the difficulty and cost of the manufacturing process; at the same time, the electron emission layer 212 It is difficult to control the uniform distribution on the surface of the cathode electrode 211, thus affecting the electron emission uniformity of the field emission cathode array.

In summary, it is necessary to provide a new type of field emission array with a gate control function. The fabrication process of the cathode and grid is simple, the electron emission layer can be uniformly and graphically deposited on the surface of the cathode electrode, and the gate control voltage is low. , At the same time, the electron emission layer on the surface of the cathode electrode can realize uniform emission under the action of a uniform electric field, effectively improving the electron emission uniformity and electron emission efficiency of the field emission cathode array.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies of the prior art and provide a field emission cathode array with a simple manufacturing process and a grid control function and its manufacturing method. The field emission array cathode can not only realize grid low voltage regulation, but also uniform electron emission And the efficiency is high, and the manufacturing process is extremely simple, and it is easy to realize the production and manufacture of a large-area field emission cathode array with a grid regulation function.

For realizing the above object, technical scheme of the present invention is:

A field emission cathode array with a gate control function, comprising a glass substrate, a cathode and a grid arranged on the glass substrate, characterized in that: the cathode and the grid are arranged on the same plane of the glass substrate, and the cathode is made of Multiple rows of strip cathode electrodes parallel to each other and electron emission layers and dielectric layers are alternately arranged on each row of strip cathode electrodes, the dielectric layers are arranged on the cathode electrodes at equal intervals, and the electron emission layers are Arranged at equal intervals on the cathode electrodes that are not covered by the dielectric layer, the grid is composed of multiple columns of grid electrodes parallel to each other, and the grid electrodes of each column are composed of longitudinal electrodes and several transverse strips. The configuration is that the grid electrodes and cathode electrodes are arranged alternately on the glass substrate, and the electron emission layers located in each row of cathode electrodes are parallel to and opposite to the lateral strips of the adjacent grid electrodes.

Preferably, the horizontal strips of each row of grid electrodes are symmetrically arranged on both sides of the vertical electrodes of the grid electrodes at equal intervals, the horizontal strips are perpendicular to the longitudinal electrodes, the width of the horizontal strips is 1 μm-1 mm, and the length of the horizontal strips is 100 μm-2 mm , the distance between adjacent lateral strips on each column of gate electrodes is 100 μm-2 mm.

Preferably, the length of the electron emission layer disposed on the cathode electrode is consistent with the width of the lateral strip of the adjacent gate electrode, and the distance between the electron emission layer and the transverse strip of the adjacent gate electrode is 0.01 μm-200 μm.

Preferably, the dielectric layer is a rectangular dielectric layer covering the cathode electrode, or a strip dielectric layer covering the cathode electrode, the glass substrate and the longitudinal electrodes of the gate electrode, and the thickness of the dielectric layer is 10nm-100nm, The material constituting the dielectric layer includes one or a combination of two or more of SiO ₂ , Ta ₂ O ₅ , AlN, Al ₂ O ₃ , Si ₃ N ₄ , BN, and TiO ₂ .

Preferably, the electron emission layer contains one or a combination of two or more of carbon nanotubes, zinc oxide, tin oxide, magnesium oxide, and bismuth oxide.

Preferably, the electron emission layer can be doped with one or a combination of two or more of nano-silver particles, nano-gold particles, nano-copper particles, nano-tin particles, nano-zinc oxide particles, and nano-nickel particles, and the particle diameter is 0.1 nm-10μm.

The invention also discloses a method for manufacturing a field emission cathode array with gate control function, which is characterized in that it includes the following steps:

(1) Scribing and cleaning the entire glass;

(2) Prepare the grid and cathode electrodes on the glass substrate by coating, photolithography or printing, photolithography, and sintering;

(3) Prepare the dielectric layer on the glass substrate with cathode electrodes and grids by photolithography, coating, and lift-off techniques;

(4) Electrophoretic deposition, sintering or printing, photolithography, sintering or printing and sintering are used to prepare an electron emission layer with field electron emission properties on the surface of the cathode electrode not covered by the dielectric layer.

Preferably, the electrophoretic deposition in the step (4) uses the gate as the electrophoretic anode, and the cathode electrode as the electrophoretic cathode, and changes the electric field by changing the voltage during electrophoresis, so that the electron emission layer is uniformly deposited on the undisturbed medium Layer covered cathode electrode surface, thus forming a patterned electron emission layer.

The beneficial effect of the present invention is to provide a field emission cathode array with a gate control function, the electron emission source of the field emission cathode array can realize patterned growth uniformly, and is parallel to the transverse strip of the gate electrode, which is beneficial to improve The electron emission uniformity and electron emission efficiency of the field emission cathode array; in addition, the field emission cathode array can complete the cathode electrode and grid on the substrate by using ordinary coating and photolithography processes, using electrophoretic deposition, sintering or printing , photolithography, sintering or printing, and sintering can prepare the array electron emission layer. The manufacturing process is simple, which greatly reduces the complexity and difficulty of the process. It is not only easy to produce but also low in manufacturing cost. It is very suitable for large-scale production and future industrial production. , has a broad market application prospect.

Description of drawings

FIG. 1 is a top view of a field emission cathode with a planar structure in the prior art.

Fig. 2 is a cross-sectional view of a field emission cathode with a planar structure in the prior art.

Fig. 3 is a schematic structural diagram of a field emission cathode array with gate control function according to the first preferred embodiment of the present invention.

Fig. 4 is a top view of a field emission cathode array with gate control function according to the first preferred embodiment of the present invention.

Fig. 5 is an optical micrograph of the field emission cathode array structure with gate control function before the electron emission layer is prepared according to the first preferred embodiment of the present invention.

Fig. 6 is an optical micrograph of the field emission cathode array for preparing the electron emission layer according to the first preferred embodiment of the present invention.

Fig. 7 is a luminescent diagram of the anode fluorescent screen emitting in a vacuum field by cooperating the field emission cathode array with grid control function and the anode fluorescent screen according to the first preferred embodiment of the present invention.

FIG. 8 is a schematic structural diagram of a field emission cathode array with a gate control function according to a second preferred embodiment of the present invention.

FIG. 9 is a top view of a field emission cathode array with gate control function according to the second preferred embodiment of the present invention.

Fig. 10 is a cross-sectional view of a field emission cathode array with gate control function according to the second preferred embodiment of the present invention.

the

[Description of main component symbols]

200—glass substrate; 210—cathode; 211—cathode electrode; 212—electron emission layer; 213—dielectric layer; 220—grid; 221—longitudinal electrode; 222—transverse strip.

Detailed ways

A field emission cathode array with gate control function and its manufacturing method according to the preferred embodiment 1 of the present invention will be described below with reference to the accompanying drawings 3-7.

As shown in Figures 3 and 4, a field emission cathode array with gate control function of the present invention includes a glass substrate 200, a cathode 210 and a grid 220 arranged on the glass substrate 200, and the cathode 210 and grid The pole 220 is arranged on the same plane as the glass substrate 200, and the cathode 210 is composed of a plurality of rows of strip cathode electrodes 211 parallel to each other and electron emission layers 212 and dielectric layers 213 are alternately arranged on each row of strip cathode electrodes 211. The dielectric layer 213 is arranged on the cathode electrode 211 at equal intervals, and the dielectric layer 213 is a strip-shaped dielectric layer covering the cathode electrode 211, the glass substrate 200 and the vertical electrode 211 of the grid 220, and the thickness of the dielectric layer 213 is 10nm-100nm, and the material constituting the dielectric layer 213 includes one or a combination of two or more of SiO ₂ , Ta ₂ O ₅ , AlN, Al ₂ O ₃ , Si ₃ N ₄ , BN, and TiO ₂ . The electron emission layer 212 is equidistantly arranged on the cathode electrodes 211 covered by the dielectric layer 213, and the grid 220 is composed of multiple rows of grid electrodes parallel to each other, and the grid electrodes of each row are Composed of longitudinal electrodes 221 and several transverse strips 222, the gate electrodes and cathode electrodes 211 are alternately arranged on the glass substrate 200, and the electron emission layer 212 located in each row of cathode electrodes 211 is connected to the adjacent gate electrodes The transverse strips 222 are parallel to each other. The length of the electron emission layer 212 arranged on the cathode electrode 211 is consistent with the width of the lateral strip 222 of the adjacent gate electrode, and the distance between the electron emission layer 212 and the transverse strip 222 of the adjacent gate electrode is 0.01 μm-200 μm . The electron emission layer contains one or a combination of two or more of carbon nanotubes, zinc oxide, tin oxide, magnesium oxide, and bismuth oxide. The electron emission layer 212 can also be doped with one or a combination of two or more of nano-silver particles, nano-gold particles, nano-copper particles, nano-tin particles, nano-zinc oxide particles, and nano-nickel particles, with a particle diameter of 0.1 nm. -10 μm.

A method for preparing a field emission cathode array with gate control function provided by the preferred embodiment 1 of the present invention comprises the following steps:

(S11) Preparation of the glass substrate 200: scribing and cleaning the entire glass;

(S12) Fabrication of the cathode electrode 211 and the grid 220, the specific process includes:

( S121 ) Fabricate a conductive film on the glass substrate 200 after slicing by sputtering deposition or printing, photolithography, and sintering.

The cathode electrode 211 and the grid 220 are formed on the surface of the substrate 200, and the materials used can be selected from Cu, W, Co, Ni, Ta, TaN, Ti, Zn, Al, Cr, one metal electrode or two kinds of photosensitive silver paste. Composite metal electrodes and combinations thereof. In this embodiment, the CrNi composite film is preferably deposited by magnetron sputtering.

(S122) Photoresist spin coating. The RZJ-304 photoresist was transferred to the surface of the glass substrate 200 with the CrNi composite film by spin-coating process, and kept at 110° C. for 25 minutes.

(S123) exposure. After the pre-dried photoresist film layer is naturally cooled to room temperature, it is exposed, and the mask plate of the required pattern is covered on the photoresist film layer, and the photoresist film layer is exposed for 11 seconds on a photolithography machine with a light intensity of 4.4mW/ ^cm2 . The photosensitizer of the photoresist is positive, so the pattern subjected to ultraviolet light is dissolved by light, and the pattern not subjected to ultraviolet light remains unchanged.

(S124) Developing. Develop with a concentration of 3% RZX-3038 solution, and the photoresist cured by light is removed by RZX-3038 solution, leaving the desired pattern.

(S125) Wet etching. Etching in a water bath at 50°C with a mixed solution consisting of 15-20 grams of cerium nitrate, 5 ml of glacial acetic acid, and 100 ml of water.

(S126) Unglue. The wet-etched substrate is immersed in an acetone solution, and the photoresist on the electrode surface is peeled off due to being dissolved in acetone, forming a cathode electrode 211 and a grid 220 .

( S13 ) Fabrication of the dielectric layer 213 . In this first preferred embodiment, the dielectric layer 213 in the field emission cathode array with grid control function is a rectangular shape 213 covering the cathode electrode 211, or it may be a rectangular shape 213 covering the cathode electrode 211, the glass substrate 200 and the grid electrode. The strip-shaped dielectric layer 213 on the longitudinal electrode 221, the thickness of the dielectric layer 213 is 10nm-100nm, and the material of the dielectric layer 213 includes SiO ₂ , Ta ₂ O ₅ , AlN, Al ₂ O ₃ , Si ₃ N ₄ , BN, TiO ₂ or a combination of two or more. In this embodiment, the SiO ₂ strip dielectric layer 213 is preferably used. (S13) The specific implementation steps are as follows:

(S131) Photoresist spin coating. Transfer the RZJ-304 photoresist to the glass substrate with the cathode electrode 211 and the grid 220 by spin-coating process, and bake in an oven with a baking temperature of 110°C and a holding time of 25 minutes;

(S132) Exposure and development. The pre-dried photoresist film layer was naturally cooled to room temperature and then exposed. The prepared mask was covered on the photoresist film layer and exposed for 11 seconds on a photolithography machine with a light intensity of 4.4mW/ ^cm2 . Developing the 3% RZX-3038 solution, the photoresist cured by light is removed by the RZX-3038 solution, leaving a striped photoresist pattern covering the horizontal band 222 on the gate electrode and perpendicular to the cathode electrode 211;

(S133) SiO ₂ dielectric thin film plating. Using sputtering or electron beam evaporation to deposit a layer of thickness on the above-mentioned glass substrate is 10nm-100nmSiO Dielectric _thin film;

(S134) Photoresist stripping. The substrate coated with _SiO2 dielectric film is soaked in the acetone solution, the photoresist covering the lateral strip 222 of the gate electrode and perpendicular to the cathode electrode 211 will be dissolved by acetone to remove the _SiO2 dielectric layer on its surface, leaving Under the required strip dielectric layer 213, at this time, observe the field emission cathode array structure with grid control effect before the preparation of the electron emission layer of the first preferred embodiment of the present invention through an optical microscope, as shown in Figure 5 ;

(S14) Fabrication of the electron emission layer 212. The electron emission source in the field emission cathode array with gate control function may contain one or a combination of two or more of carbon nanotubes, zinc oxide, tin oxide, magnesium oxide, and bismuth oxide; electrophoretic deposition, silk On the cathode electrode 211 not covered by the dielectric layer 213 , an electron emission layer 212 with field electron emission performance is prepared on the surface by screen printing or photolithography. In this embodiment, the carbon nanotube electron emission source is preferably prepared by electrophoretic deposition, and the specific implementation process is as follows:

(S141) Preparation of carbon nanotube organic slurry. Before electrophoresis, the original powder of carbon nanotubes was placed in 1:1 concentrated sulfuric acid and concentrated nitric acid at 100 ° C for 3 h; 100 ml terpineol and 1 g ethyl cellulose were mixed and dispersed evenly in a water bath at 95 ° C. After the ethyl cellulose is mixed and completely dissolved, add 5 g of acidified carbon nanotube powder and stir evenly; finally, fully ball mill for 24 h in a three-dimensional ball mill to make the carbon nanotubes evenly dispersed;

(S142) Electrophoresis solution preparation. Mix 1-5g of carbon nanotube organic slurry, 500 ml of isopropanol, and 100-500 mg of magnesium nitrate (Mg(NO ₃ ) _2· 6H ₂ O), and disperse for 5 hours under the action of ultrasonic waves at room temperature to increase carbon The dispersibility of nanotubes in the solution, finally forming a stable suspension of carbon nanotubes, cooling to room temperature naturally or accelerated cooling to a lower temperature with a cold water bath;

(S143) Electrophoretic deposition of the carbon nanotube electron emission layer. In the electrophoresis process, the gate 220 is used as the electrophoresis anode, and the cathode electrode 211 is used as the electrophoresis cathode. The electric field is changed by changing the voltage during electrophoresis. The electrophoresis voltage is 2-20 V, and the electrophoresis time is 5-30 min. The tube electron emission layer 212 is evenly deposited on the surface of the cathode electrode 211 not covered by the dielectric layer 213, thereby forming a patterned electron emission layer 212;

(S144) Carbon nanotube sintering. After the substrate after electrophoresis is kept at 350°C for 20 minutes under the protection of nitrogen, a layer of carbon nanotube film with uniform thickness can be attached to the surface of the cathode electrode 211 not covered by the dielectric layer 213, and the electron emission layer is studied by optical microscope. The situation of preparation is as shown in accompanying drawing 6. In the present invention, the grid 220 in the field emission cathode array is used as the electrophoretic anode, and the cathode electrode 211 is used as the electrophoretic cathode. The prepared electron emission layer is uniformly and graphically distributed on the cathode electrode 211 not covered by the dielectric layer 213, and the operation is simple. , the cost is low, and the preparation of a large-area cathode array can be realized at the same time.

So far, the fabrication of the field emission cathode array with grid control function in the first preferred embodiment of the present invention is completed. In order to further study the field emission performance of the field emission cathode array with grid control function, the field emission cathode array with grid control function The emission cathode array cooperates with the anode fluorescent screen, and the electron emission of the field emission cathode array is tested in vacuum. From the luminescence diagram of the anode fluorescent screen in the accompanying drawing 7, the field emission uniformity of the field emission cathode array with grid control effect good.

In order to reduce the cost, the first preferred embodiment of the present invention is improved, and the strip-shaped dielectric layer 213 is changed to an array-distributed dielectric layer 213. The field emission cathode array with gate control effect in the second preferred embodiment of the present invention is shown in Figure 7 , 8 and 9, including a glass substrate 200, a cathode 210 and a grid 220 arranged on the glass substrate 200, the cathode 210 and the grid 220 are arranged on the same plane of the glass substrate 200, and the cathode 210 is composed of multiple columns Strip cathode electrodes 211 parallel to each other and electron emission layers 212 and dielectric layers 213 are alternately arranged on the strip cathode electrodes 211 of each row. The dielectric layers 213 are arranged on the cathode electrodes 211 at equal intervals, and the dielectric layer It is a rectangular dielectric layer covering the cathode electrode. The thickness of the dielectric layer is 10nm-100nm. The material of the dielectric layer includes SiO ₂ , Ta ₂ O ₅ , AlN, Al ₂ O ₃ , Si ₃ N ₄ , BN, TiO ₂ One or a combination of two or more. The electron emission layer 212 is equidistantly arranged on the cathode electrodes 211 not covered by the dielectric layer 213, and the grid 220 is composed of multiple rows of grid electrodes parallel to each other. Pole electrodes are composed of longitudinal electrodes 221 and several transverse strips 222. The grid electrodes and cathode electrodes 211 are alternately arranged on the glass substrate 200. The electron emission layers 212 located in each row of cathode electrodes 211 are connected to adjacent grid electrodes. The transverse strips 222 of the pole electrodes are parallel to each other. The horizontal strips 222 of each row of grid electrodes can be symmetrically arranged on both sides of the vertical electrode 221 of the grid electrode at equal intervals, the horizontal strips 222 are perpendicular to the vertical electrodes 221, the width of the horizontal strips 222 is 1 μm-1mm, and the length of the horizontal strips 222 100 μm-2 mm, and the distance between adjacent lateral strips 222 on each column of gate electrodes is 100 μm-2 mm.

The manufacturing method of the field emission cathode array with gate control function comprises the following steps:

(S21) Preparation of the glass substrate 200: scribing and cleaning the entire glass;

( S22 ) Fabrication of the cathode electrode 211 and the grid 220 . The cathode electrode 211 and the grid 220 are formed on the surface of the substrate 200, and the materials used can be selected from Cu, W, Co, Ni, Ta, TaN, Ti, Zn, Al, Cr, one metal electrode or two kinds of photosensitive silver paste. Composite metal electrodes and combinations thereof. In this embodiment, printing, photolithography and sintering techniques are preferably used to prepare thick-film silver paste conductive electrodes. The specific process includes:

(S221) Photosensitive silver paste printing. Use a 250-mesh screen to print photosensitive silver paste onto the surface of the glass substrate 200, and keep it warm at 110°C for 20 minutes.

(S222) exposure. The pre-dried photosensitive silver paste film layer is naturally cooled to room temperature before exposure, and the mask plate of the cathode pattern is covered on the photosensitive silver paste film layer. The photosensitizer of the photosensitive silver paste is negative, so the pattern subjected to ultraviolet light is exposed Light curing, graphics that are not exposed to UV light remain unchanged.

(S223) Developing. Develop with a Na ₂ CO ₃ solution with a concentration of 0.4%, and the photosensitive silver paste that has not been cured by light is removed by the Na ₂ CO ₃ solution, leaving the desired pattern.

(S224) High temperature sintering. The developed pattern is sintered at 530° C. for 30 minutes under the protection of nitrogen to form the cathode electrode 211 and the grid 220 .

( S23 ) Fabrication of the dielectric layer 213 . The dielectric layer 213 in the field emission cathode array with gate control function can be a strip-shaped dielectric layer covering the cathode electrode 211, the glass substrate 200 and the vertical electrode 221 on the grid 220, or it can be a rectangular dielectric layer covering the cathode electrode 211. The composition of the dielectric layer can be SiO ₂ , Ta ₂ O ₅ , AlN, Al ₂ O ₃ , Si ₃ N ₄ , BN, TiO ₂ . In this embodiment, the SiO ₂ rectangular dielectric layer is preferably used. The specific implementation process is basically similar to Step 2 in Embodiment 1, except that the dielectric layer 213 only covers the cathode electrode 211 parallel to the vertical electrode 221 on the gate electrode to form a rectangular dielectric layer 213. The process is as follows:

(S231) Photoresist spin coating. Transfer the RZJ-304 photoresist to the glass substrate with the cathode electrode 211 and the grid 220 by spin-coating process, and bake in an oven with a baking temperature of 110°C and a holding time of 25 minutes;

(S232) Exposure and development. The pre-dried photoresist film layer was naturally cooled to room temperature and then exposed. The prepared mask was covered on the photoresist film layer and exposed for 11 seconds on a photolithography machine with a light intensity of 4.4mW/ ^cm2 . For the development of 3% RZX-3038 solution, the photoresist on the cathode electrode 211 that is photocured and parallel to the vertical electrode 221 on the grid electrode is removed by the RZX-3038 solution;

(S233) SiO ₂ dielectric thin film plating. Utilizing sputtering or electron beam evaporation to deposit a _layer of SiO with a thickness of 10nm-100nm on the above-mentioned prepared glass substrate Dielectric film;

(S234) The photoresist is stripped. Soak the substrate coated with _SiO2 dielectric film in the acetone solution, and the photoresist covering the grid electrode, the cathode electrode 211 opposite to the horizontal band 222 on the grid electrode and the electrodeless place will be dissolved and removed by acetone The dielectric layer on the surface leaves a rectangular dielectric layer 213 on the cathode electrode 211 parallel to the longitudinal electrode 221 on the gate electrode.

(S24) Fabrication of an electron emission source. In order to improve the binding force between the emission material and the substrate in the electron emission layer 212 and improve the field electron emission capability of the electron emission layer, the electron emission layer 212 can also be doped with nano-silver particles, nano-gold particles, nano-copper particles, nano Tin particles, nano-zinc oxide particles, nano-nickel particles, the particle diameter is 0.1 nm-10 μm, in combination with the electrophoretic deposition method in this preferred embodiment 1 to prepare the electron emission layer 212, the nano-silver metal particles can be added to the electrophoretic liquid, It is deposited on the cathode electrode 211 not covered by the dielectric layer 213 by electrophoretic deposition process. The specific implementation process is as follows:

(S241) Preparation of nano-silver/carbon nanotube organic paste. Before electrophoresis, the original powder of carbon nanotubes was placed in 1:1 concentrated sulfuric acid and concentrated nitric acid at 100°C for 3 hours; 100 ml of terpineol and 1 g of ethyl cellulose were mixed and dispersed evenly in a water bath at 95°C. Add 5 g carbon nanotube powder and 5 g nano-silver particles after the acidification after ethyl cellulose is mixed and completely dissolved, and stir evenly. Finally, full ball milling was carried out in a three-dimensional ball mill for 24 h to disperse the carbon nanotubes evenly;

(S242) Electrophoresis solution preparation. Take 1-5 g of nano-silver/carbon nanotube organic slurry, 500 ml of isopropanol, 100-500 mg of magnesium nitrate (Mg(NO ₃ ) _2· 6H ₂ O), mix them, and disperse under the action of ultrasonic waves at room temperature 5h, improve the dispersion of carbon nanotubes in the solution, and finally form a stable suspension of carbon nanotubes, naturally cool to room temperature or use a cold water bath to accelerate cooling to a lower temperature;

(S243) Electrophoretic deposition of nano-silver/carbon nanotube composite materials. In the electrophoresis process, the gate 220 is used as the electrophoresis anode, and the cathode electrode 211 is used as the electrophoresis cathode. The electric field is changed by changing the voltage during electrophoresis. The electrophoresis voltage is 2-20 V, and the electrophoresis time is 5-30 min. The tube electron emission layer 212 is uniformly deposited on the surface of the cathode electrode 211 not covered by the dielectric layer 213, thereby forming a patterned nano-silver/carbon nanotube electron emission layer 212;

(S244) Nanosilver/carbon nanotube sintering. After the electrophoretic deposition substrate is kept at 350° C. for 20 minutes under the protection of nitrogen, a layer of nano-silver/carbon nanotube electron emission layer 212 with a uniform thickness can be attached to the surface of the cathode electrode 211 not covered by the dielectric layer.

In summary, the field emission cathode array with gate control function disclosed by the present invention can realize low-voltage regulation, reduce the open electric field of the field emission cathode array, improve the uniformity and efficiency of electron emission, and has a simple structure and a manufacturing process Easy, low cost, stable and reliable manufacturing process.

The present invention provides preferred embodiments, but should not be considered limited to the embodiments set forth herein. In accompanying drawings 3-10, the thicknesses of layers and regions are exaggerated for clarity, but as schematic diagrams, it should not be regarded as strictly reflecting the proportional relationship of geometric dimensions. The drawings are schematic illustrations of idealized embodiments of the invention. The illustrated embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated in the drawings but are to include resulting shapes such as manufacturing-induced deviations. In this embodiment, they are all represented by rectangles, and the representations in the drawings are schematic, but this should not be considered as limiting the scope of the present invention.

The above example mainly illustrates the preparation method of a field emission cathode with gate control function of the present invention. Although only some of the embodiments of the present invention have been described, those skilled in the art should appreciate that the present invention can be implemented in many other forms without departing from the spirit and scope thereof. Accordingly, the examples and embodiments shown are to be regarded as illustrative and not restrictive, and the invention may cover various aspects without departing from the spirit and scope of the invention as defined in the appended claims. Modify and replace. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (8)

1. field emission cathode array that has the grid-control effect; Comprise glass substrate; Be arranged at negative electrode and grid on the glass substrate; It is characterized in that: described negative electrode and grid are arranged on the same plane of glass substrate; Negative electrode is the strip cathode electrode that is parallel to each other by multiple row and on each row strip cathode electrode, alternately electron emission layer is set and dielectric layer constitutes, and described dielectric layer is to be arranged on equally spacedly on the cathode electrode, and described electron emission layer is to be arranged on equally spacedly not by on the cathode electrode that dielectric layer covered; Described grid is to be made up of the gate electrode that multiple row is parallel to each other; Gate electrode of said each row is made up of longitudinal electrode and several transverse belts, and described gate electrode and cathode electrode are arranged alternately on glass substrate, and the described electron emission layer that is positioned at each row cathode electrode is parallel with the transverse belt of neighboring gates electrode relative.

2. the field emission cathode array that has the grid-control effect according to claim 1; It is characterized in that: the transverse belt of every row gate electrode equidistantly is arranged on the longitudinal electrode both sides of gate electrode symmetrically; Transverse belt is perpendicular to longitudinal electrode; The width of transverse belt is 1 μ m-1mm, and the length of transverse belt is 100 μ m-2mm, the distance 100 μ m-2mm between the adjacent transverse band on each row gate electrode.

3. the field emission cathode array that has the grid-control effect according to claim 1; It is characterized in that: the length that is arranged at the electron emission layer on the cathode electrode is consistent with the width of the transverse belt of neighboring gates electrode, and the distance between the transverse belt of electron emission layer and neighboring gates electrode is 0.01 μ m-200 μ m.

4. the field emission cathode array that has the grid-control effect according to claim 1; It is characterized in that: said dielectric layer is the rectangular-shaped dielectric layer that covers on the cathode electrode; Or cover the strip dielectric layer on the longitudinal electrode of cathode electrode, glass substrate and gate electrode; Thickness of dielectric layers is 10nm-100nm, constitutes the dielectric layer material and comprises SiO ₂, Ta ₂O ₅, AlN, Al ₂O ₃, Si ₃N ₄, BN, TiO ₂In a kind of or two kinds and above combination.

5. the field emission cathode array that has the grid-control effect according to claim 1 is characterized in that: said electron emission layer comprises a kind of or two kinds and the above combination in CNT, zinc oxide, tin oxide, magnesia, the bismuth oxide.

6. the field emission cathode array that has the grid-control effect according to claim 5; It is characterized in that: electron emission layer can doping nano-Ag particles, a kind of or two kinds and above combination in the nanogold particle, nano copper particle, nanometer tin particles, nano granular of zinc oxide, nano nickle granules, and particle diameter is 0.1nm-10 μ m.

7. a manufacturing approach that has the field emission cathode array of grid-control effect is characterized in that, may further comprise the steps:

(1) whole glass is carried out scribing, clean;

(2) on glass substrate, adopt the method for plated film, photoetching or printing, photoetching, sintering to prepare grid and cathode electrode;

(3) on the glass substrate that has cathode electrode and grid, adopt photoetching, plated film, lift-off technology to prepare dielectric layer;

(4) on not by the cathode electrode that dielectric layer covered, adopt electrophoretic deposition, sintering or printing, photoetching, sintering or printing, sintering preparation surface to have the electron emission layer of electronic emission performance.

8. a kind of manufacturing approach that has the field emission cathode array of grid-control effect according to claim 7; It is characterized in that: the electrophoretic deposition in said step (4) is to adopt grid as the electrophoresis anode; Adopt cathode electrode as the electrophoresis negative electrode; Voltage changes electric field level during through the change electrophoresis, makes electron emission layer be deposited on equably not by the cathode electrode surface that dielectric layer covered, and forms patterned electron emission layer.

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