CN102376582A

CN102376582A - Semiconductor device structure and method for producing same

Info

Publication number: CN102376582A
Application number: CN2010102675677A
Authority: CN
Inventors: 宁先捷
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2010-08-24
Filing date: 2010-08-24
Publication date: 2012-03-14

Abstract

The invention provides a semiconductor device structure and a method for producing the same. The method for producing the semiconductor device structure comprises the following steps of: (a) providing a front-end device layer structure comprising a substrate, wherein a gate oxide layer and a polysilicon gate are formed on the surface of the substrate, the polysilicon gate is encircled by a side wall and a source/drain region is formed in a region of the substrate, which is positioned at the outer side of the side wall; (b) forming interlayer dielectric layers on the surfaces of the polysilicon gate, the side wall and the surface of the source/drain region; (c) flattening the interlayer dielectric layers until the surface of the polysilicon gate is exposed; (d) removing the polysilicon gate by etching until the gate oxide layer is exposed so as to form a trench for accommodating a metal gate; (e) filling metal in the trench so as to form a metal gate structure; (f) flattening the metal gate structure until the side wall is exposed so as to form the metal gate; (g) removing the upper part of the side wall and all interlayer dielectric layers; and (h) forming a self-aligning silicide layer on the surface of the source/drain region.

Description

Semiconductor device structure and the method for making this semiconductor device structure

Technical field

The present invention relates to semiconductor fabrication process, more particularly, the present invention relates to a kind of semiconductor device structure and the method for making this semiconductor device structure.

Background technology

Grid has the minimum physical size in the semiconductor fabrication process usually, and its width critical dimension of most critical on the wafer normally, and therefore the making of grid is the step of most critical in the flow process in fabrication of semiconductor device.

Because that polycrystalline silicon material has is high temperature resistant, can stop that injecting the atom mixed with ion gets into advantages such as channel region; So, when making typical CMOS transistor, can use polycrystalline silicon material to make transistorized grid usually.But polysilicon gate has some shortcomings, and for example, polysilicon gate has higher resistance value, is easy to generate depletion effects and boron penetration to channel region etc.Therefore, as far as the semiconductor wafer of inferior 45 nanometers, adopt metal gates to replace conventional polysilicon gate usually.

Generally, utilize prior art to make to have the cross-sectional view of semiconductor device structure of metal gates following:

At first, shown in Figure 1A, front end device layer structure 101 is provided, the surface of this front end device layer structure 101 is formed with polysilicon gate 102 and side wall 103; The second, shown in Figure 1B, at the surface deposition metallic nickel of front end device layer structure 101 to form self-aligned silicide layer 104; The 3rd, shown in Fig. 1 C, the surface deposition interlayer dielectric layer 105 at said structure etches away polysilicon gate 102 then, forms the groove 106 that holds metal gates; The 4th, shown in Fig. 1 D, plated metal forms stressor layers 108 on the surface of metal gates 107 and interlayer dielectric layer 105 then to form metal gates 107.

But there are some defectives in the method for above-mentioned making semiconductor device structure: the first, because the self-aligned silicide layer forms early, therefore, the high temperature in the subsequent technique will influence the performance of self-aligned silicide layer, cause it undesirable higher resistance to occur; The second, owing to before forming the self-aligned silicide layer, need to form silicide barrier layer, therefore need to use separately a mask plate to make silicide barrier layer, but the expense of mask plate is very high, this just causes the cost of entire making process to increase; The 3rd, because the isolation of interlayer dielectric layer causes the distance in stressor layers and source/drain region far away, make that the stress effect of stressor layers is not too obvious.

Therefore, be necessary the manufacture method of conventional semiconductor device architecture is improved, with performance and the effect of improving semiconductor device structure, thereby improve quality of semiconductor devices, and reduce manufacturing cost.

Summary of the invention

In the summary of the invention part, introduced the notion of a series of reduced forms, this will further explain in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to confirm technical scheme required for protection.

Therefore, for the performance that in the manufacturing process of semiconductor device structure, guarantees self-aligned silicide, the stress effect that reduces cost of manufacture and increase stressor layers, the present invention provides a kind of method of making semiconductor device structure, comprises the following steps:

A) front end device layer structure is provided; Wherein, said front end device layer structure comprises substrate, and the surface of said substrate is formed with gate oxide and polysilicon gate from bottom to top; Said polysilicon gate forms active/drain region by side wall around the zone in, the outside that is arranged in said side wall of said substrate;

B) form interlayer dielectric layer on the surface of the surface of said polysilicon gate, said side wall and the surface in said source/drain region;

C) the said interlayer dielectric layer of planarization is to the surface that exposes said polysilicon gate;

D) remove said polysilicon gate best through etching and expose said gate oxide, to be formed for holding the groove of metal gates;

E) in said groove, fill metal, to form metal gate structure;

F) the said metal gate structure of planarization is to exposing said side wall to form said metal gates;

G) top and all said interlayer dielectric layers of the said side wall of removal; And

H) form the self-aligned silicide layer on the surface in said source/drain region.

Further, also comprise:

I) form stressor layers on the surface of the surface of said self-aligned silicide layer, said remaining side wall and the surface of said metal gates.

Further, said metal gates is the N type metal gates utmost point or the P type metal gates utmost point.

Further, the said N type metal gates utmost point is positioned at N type trap core space or N type trap I/O area.

Further, the said P type metal gates utmost point is positioned at P type trap core space or P type trap I/O area.

Further, said metal is that work function is applicable to the metal of nmos device or the metal that work function is applicable to the PMOS device.

The present invention also provides a kind of method of making semiconductor device structure, comprises the following steps:

A) front end device layer structure is provided; Said front end device layer structure comprises substrate; Said substrate have at least above that first device that forms and left by shallow trench isolation and with opposite polarity second device of said first device; Wherein, the surface of said first device is formed with the first grid oxide layer and first polysilicon gate from bottom to top, and the surface of said second device is formed with second gate oxide and second polysilicon gate from bottom to top; The both sides of the both sides of said first polysilicon gate and said second polysilicon gate form active/drain region by side wall around the zone in, the outside that is arranged in said side wall of said substrate;

B) on the surface of said first polysilicon gate, the surface of the surface of said second polysilicon gate, said side wall and the surface in said source/drain region form interlayer dielectric layer;

C) surface of the said interlayer dielectric layer of planarization to surface that exposes said first polysilicon gate and said second polysilicon gate;

D) above said second device, form the cover layer that covers said second polysilicon gate;

E) remove the said first polysilicon gate best through etching and expose said first grid oxide layer, to be formed for holding the groove of metal gates;

F) remove said cover layer;

G) in said groove, fill metal, to form metal gate structure;

H) the said metal gate structure of planarization is to exposing said side wall to form said metal gates;

I) top and all said interlayer dielectric layers of the said side wall of removal; And

J) form the self-aligned silicide layer on the surface in said source/drain region.

Further, also comprise:

K) form stressor layers on the surface of the surface of the surface of said self-aligned silicide layer, said remaining side wall, said metal gates and the surface of said second polysilicon gate.

Further, said first device is nmos device or PMOS device.

The present invention also provides a kind of semiconductor device structure, comprising:

Substrate;

Gate oxide, said gate oxide is formed on the surface of said substrate;

Metal gates, said metal gates is formed on the surface of said gate oxide;

Side wall, said side wall is around said metal gates;

Source/drain region, said source/drain region are formed on the zone in the outside that is arranged in said side wall of said substrate;

The self-aligned silicide layer, said self-aligned silicide layer is formed on the surface in said source/drain region;

Stressor layers, said stressor layers are formed on the surface of the surface of said metal gates, said side wall and the surface of said self-aligned silicide layer.

Further, the work function of said metal gates with the metal that is applicable to nmos device set metal level or is applicable to that the work function of the metal of PMOS device sets metal level.

The present invention should provide a kind of semiconductor device structure, comprising:

Substrate, said substrate have at least above that first device that forms and left by shallow trench isolation and with opposite polarity second device of said first device;

The first grid oxide layer and second gate oxide, said first grid oxide layer is formed on the surface of said first device, and said second gate oxide is formed on the surface of said second device;

Metal gates, said metal gates is formed on the surface of said first grid oxide layer;

Polysilicon gate, said polysilicon gate is positioned at the surface of said second gate oxide;

Side wall, said side wall is around said metal gates and said polysilicon gate;

Stressor layers, said stressor layers are formed on the surface of the surface of the surface of said metal gates, said polysilicon gate, said side wall and the surface of said self-aligned silicide layer.

Further, said first device is nmos device or PMOS device.

The present invention provides a kind of integrated circuit that comprises the semiconductor device of said method manufacturing, and wherein said integrated circuit is selected from the wherein at least a of random access memory, dynamic random access memory, Synchronous Dynamic Random Access Memory, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type dynamic random access memory and radio circuit.

The present invention provides a kind of electronic equipment that comprises the semiconductor device of said method manufacturing, and wherein said electronic equipment is selected from the wherein at least a of personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera and mobile phone.

The present invention provides a kind of integrated circuit that comprises the above-mentioned semiconductor device structure, and wherein said integrated circuit is selected from the wherein at least a of random access memory, dynamic random access memory, Synchronous Dynamic Random Access Memory, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type dynamic random access memory and radio circuit.

The present invention provides a kind of electronic equipment that comprises the above-mentioned semiconductor device structure, and wherein said electronic equipment is selected from the wherein at least a of personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera and mobile phone.

In sum; The method of making semiconductor device structure of the present invention just forms the self-aligned silicide layer after metal gates forms; Therefore the situation that does not exist the high temperature in the subsequent technique that the performance of self-aligned silicide layer is exerted an influence, thus the performance of device guaranteed; Second; The method of making semiconductor device structure of the present invention can be selected the processing mode to polysilicon gate according to the characteristics of components and parts, both can keep this polysilicon gate; Also can be made into metal gates; Can also it be processed into high resistant, can increase the function of device like this, perhaps save mask plate and then reduce manufacturing cost; The 3rd, the method for making semiconductor device structure of the present invention, the close together between stressor layers and the source/drain region makes that the stress effect of stressor layers is apparent in view, thereby has increased mobility of charge carrier speed, has improved the overall performance of semiconductor device; The 4th, the method for making semiconductor device structure of the present invention makes full use of existing equipment, material and technology, can not increase the complexity of production line, and manufacture method is simple, need not expend extra man power and material; The 5th, the self-aligned silicide layer of semiconductor device structure of the present invention has preferable performance, higher resistance can not occur; The 6th, the stressor layers of semiconductor device structure of the present invention and the close together in source/drain region have stress effect preferably.

Description of drawings

Attached drawings of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,

Figure 1A to 1D shows the cross-sectional view of utilizing prior art to make semiconductor device structure;

Fig. 2 A to 2G shows the cross-sectional view of the making semiconductor device structure of first execution mode according to the present invention;

Shown in Figure 3 is the method flow diagram of the making semiconductor device structure of first execution mode according to the present invention;

Shown in Figure 4 for the sketch map of the semiconductor device structure that first execution mode is produced according to the present invention;

Fig. 5 A to Fig. 5 I shows the cross-sectional view of the making semiconductor device structure of second execution mode according to the present invention;

Shown in Figure 6 is the method flow diagram of the making semiconductor device structure of second execution mode according to the present invention;

The sketch map of the semiconductor device structure of producing for second execution mode shown in Figure 7 according to the present invention.

Embodiment

In the description hereinafter, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be able to enforcement.In other example,, describe for technical characterictics more well known in the art for fear of obscuring with the present invention.

In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that explanation the present invention is semiconductor device structure and the method for making this semiconductor device structure.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.

It should be noted that employed term only is in order to describe specific embodiment here, but not the intention restriction is according to exemplary embodiment of the present invention.As used herein, only if context spells out in addition, otherwise singulative also is intended to comprise plural form.In addition; It is to be further understood that; When using a technical term " comprising " and/or " comprising " in this manual; It indicates and has said characteristic, integral body, step, operation, element and/or assembly, does not exist or additional one or more other characteristics, integral body, step, operation, element, assembly and/or their combination but do not get rid of.

For the ease of describing; Here can the usage space relative terms; As " ... under ", " ... on ", " following ", " in ... top ", " top " etc., be used for describing spatial relation like an element shown in the figure or characteristic and other elements or characteristic.Should be understood that the space relative terms is intended to comprise the different azimuth in using or operating the orientation of being described in the drawings except device.For example, if the device in the accompanying drawing is squeezed, then be described as to be positioned as " above other elements or characteristic " or " on other elements or characteristic " after the element of " in other elements or beneath " or " under other elements or characteristic ".Thereby exemplary term " in ... below " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (revolve turn 90 degrees or be in other orientation), and employed space relative descriptors is here made respective explanations.

Now, will describe in more detail according to exemplary embodiment of the present invention with reference to accompanying drawing.Yet these exemplary embodiments can multiple different form be implemented, and should not be interpreted as the embodiment that is only limited to here to be set forth.Should be understood that, provide these embodiment of the present inventionly to disclose thoroughly and complete, and the design of these exemplary embodiments fully conveyed to those of ordinary skills in order to make.In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and zone, and used the identical Reference numeral to represent components identical, thereby will omit description of them.

[first execution mode]

Method step below in conjunction with Fig. 2 A to 2G and Fig. 3 detailed description making semiconductor device structure of first execution mode according to the present invention.Fig. 2 A to 2G is depicted as the cross-sectional view of the making semiconductor device structure of first execution mode according to the present invention.

At first, shown in Fig. 2 A, front end device layer structure is provided.

Under normal conditions, front end device layer structure comprises formed device architecture layer in the preorder technology.

As an example; Front end device layer structure comprises substrate 201; The surface of substrate 201 is formed with gate oxide 202 and polysilicon gate 203 from bottom to top, polysilicon gate 203 by side wall 204 around, the zone in the outside that is arranged in side wall 204 of substrate 201 also forms active/drain region 205/206.Can have the p type impurity or the N type impurity that mix and form through modes such as ion injections in said source/drain region 205/206.

Further, the material that constitutes substrate 201 can be unadulterated monocrystalline silicon, be doped with the monocrystalline silicon or the silicon-on-insulator (SOI) of impurity, can also comprise other material, for example indium antimonide, lead telluride, indium arsenide, GaAs or gallium antimonide etc.

In addition, it should be noted that front end device layer structure as herein described is not to be restrictive, but can also have other structures.For example, the surface of substrate 201 can also have the groove (not shown) that is formed with germanium silicon stressor layers; Source/drain region 205/206 can also be formed has lightly doped drain (LDD) structure; The surface of polysilicon gate 203 can also have mask layer; Deng.

The second, shown in Fig. 2 B, form interlayer dielectric layer 207 on the surface of polysilicon gate 203, the surface of side wall 204 and the surface in source/drain region 205/206; Then, planarization interlayer dielectric layer 207 is to the surface that exposes polysilicon gate 203; Then, remove polysilicon gate 203 to exposing gate oxide 202, to be formed for holding the groove 208 of metal gates through etching.

As an example, adopt cmp (CMP) method that interlayer dielectric layer 207 is carried out planarization.

As an example, adopt dry etch process to remove polysilicon gate 203.

Under preferred situation, just interlayer dielectric layer 207 is planarized to the top surface of polysilicon gate 203, and just polysilicon gate 203 is removed to fully the surface of gate oxide 202.But; Should be noted in the discussion above that because the size of semiconductor transistor is more and more littler particular location after being difficult to and there is no need too accurately confirm planarization and remove; Therefore; Can with interlayer dielectric layer 207 be planarized to below the top surface of polysilicon gate 203 or more than, also can polysilicon gate 203 be removed to below the top surface of gate oxide 202, this is conspicuous to those skilled in the art.

In addition; It should be noted that; For the ease of understanding accompanying drawing and making accompanying drawing can more clearly express different layer structures, no longer mark the Reference numeral in substrate 201, gate oxide 202, polysilicon gate 203, side wall 204 and source/drain region 205/206 among following Fig. 2 C～2G.

The 3rd, shown in Fig. 2 C, in groove 208, fill metal 209, to form metal gate structure;

As an example, the metal 209 of filling can be followed successively by gate dielectric layer 209a, work function setting metal level 209b and the grid electrode layer 209c of high-k (k) from bottom to top.

Further; For N type metal gates electrode structure; The metal that its work function is set metal level 209b is the metal that is applicable to nmos device, and material can comprise such as titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, for example comprises the metal carbides, nitride of these elements etc.The method that forms this N type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.

Under preferred situation, the work function of N type metal gates electrode structure is set metal level 209b and is followed successively by tantalum, titanium nitride layer and calorize titanium layer from bottom to top; Perhaps be tantalum nitride layer, titanium nitride layer and calorize titanium layer.

Again further; For P type metal gates electrode structure; The metal that its work function is set metal level 209b is the metal that is applicable to the PMOS device, and material can comprise such as ruthenium, palladium, platinum and metal nitride, for example the nitride of titanium, tungsten, tantalum, ruthenium and titanium aluminium.The method that forms this P type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.

Under preferred situation, the work function of P type metal gates electrode structure is set metal level 209b and is followed successively by titanium nitride layer, tantalum and calorize titanium layer from bottom to top; Perhaps be titanium nitride layer, tantalum nitride layer and calorize titanium layer.

Further, the material of grid electrode layer 209c is an aluminum or aluminum alloy.Under preferred situation, grid electrode layer 209c is followed successively by titanium aluminide and aluminium from bottom to top.

The 4th, shown in Fig. 2 D, the planarization material grid structure is to exposing side wall 204 to form metal gates 210.

As an example, adopt cmp (CMP) method that metal gate structure is carried out planarization.

Under preferred situation, the lucky top surface that metal gate structure is planarized to groove 208 is to expose side wall 204.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, be difficult to and there is no need too accurately to confirm the particular location after the planarization, therefore; Can metal gate structure be planarized to below the top surface of groove 208, this is conspicuous to those skilled in the art.

As an example, metal gates 210 can be the N type metal gates utmost point, also can be the P type metal gates utmost point.Wherein, the N type metal gates extremely can be positioned at N type trap core space or N type trap I/O area; The P type metal gates extremely can be positioned at P type trap core space or P type trap I/O area.Further, the metal of the N type metal gates utmost point is the metal that work function is applicable to nmos device, and the metal of the P type metal gates utmost point is the metal that work function is applicable to the PMOS device.

The 5th, shown in Fig. 2 E, remove the top and all interlayer dielectric layers 207 of side wall 204.

As an example, can remove the whole of side wall 204, for example use etching technics.But in order to save time and to optimize technical process, under preferred situation, the top of only removing side wall 204 shown in Fig. 2 E, keeps the side wall 204 ' of bottom.

The 6th, shown in Fig. 2 F, 205/206 surface forms self-aligned silicide layer 211 in source/drain region.

As an example; On the surface of remaining side wall 204 (side wall 204 ' of bottom), the surface deposition of the surface in source/drain region 205/206, metal gates 210 material of metallic nickel or platinum nickel for example, 205/206 surface forms self-aligned silicide layer 211 in source/drain region with final.

At last, shown in Fig. 2 G, form stressor layers 212 on the surface of remaining side wall 204 (side wall 204 ' of bottom), the surface of metal gates 210 and the surface of self-aligned silicide layer 211.

As shown in Figure 3, be the method flow diagram of the making semiconductor device structure of first execution mode according to the present invention.

In step S301, front end device layer structure is provided.

As an example, front end device layer structure comprises substrate, and the surface of substrate is formed with gate oxide and polysilicon gate from bottom to top successively, polysilicon gate by side wall around, the zone that substrate is positioned at the outside of side wall also forms active/drain region.Can have the p type impurity or the N type impurity that mix and form through modes such as ion injections in said source/drain region.

Further, the material that constitutes substrate can be unadulterated monocrystalline silicon, be doped with the monocrystalline silicon or the silicon-on-insulator (SOI) of impurity, can also comprise other material, for example indium antimonide, lead telluride, indium arsenide, GaAs or gallium antimonide etc.

In addition, should be noted that front end device layer structure as herein described is not to be restrictive, but can also have other structures.For example, the surface of substrate can also have the groove (not shown) that is formed with germanium silicon stressor layers; Source/drain region in the front end device layer structure can also be formed has lightly doped drain (LDD) structure; The surface of polysilicon gate can also have mask layer; Deng.

In step S302, form interlayer dielectric layer on the surface of polysilicon gate, the surface of side wall and the surface in source/drain region; Then, the planarization interlayer dielectric layer is to the surface that exposes polysilicon gate; Then, remove the polysilicon gate best through etching and expose gate oxide, to be formed for holding the groove of metal gates.

As an example, adopt cmp (CMP) method that interlayer dielectric layer is carried out planarization.

As an example, adopt dry etch process to remove polysilicon gate.

Under preferred situation, just with the top surface of interlayer dielectric layer flatening to polysilicon gate, and the lucky surface that polysilicon gate is removed to fully gate oxide.But; Should be noted in the discussion above that because the size of semiconductor transistor is more and more littler, be difficult to and there is no need too accurately to confirm the particular location after the planarization; Therefore; Can with interlayer dielectric layer flatening to below the top surface of polysilicon gate or more than, also can polysilicon gate be removed to below the top surface of gate oxide, this is conspicuous to those skilled in the art.

In step S303, in groove, fill metal, to form metal gate structure.

As an example, the metal of filling can be followed successively by gate dielectric layer, work function setting metal level and the grid electrode layer of high-k (k) from bottom to top.

Further; For N type metal gates electrode structure; The metal that its work function is set metal level is the metal that is applicable to nmos device, and material can comprise such as titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, for example comprises the metal carbides, nitride of these elements etc.The method that forms this N type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.

Under preferred situation, the work function of N type metal gates electrode structure is set metal level and is followed successively by tantalum, titanium nitride layer and calorize titanium layer from bottom to top; Perhaps be tantalum nitride layer, titanium nitride layer and calorize titanium layer.

Again further, for P type metal gates electrode structure, the metal that its work function is set metal level is the metal that is applicable to the PMOS device, and material can comprise such as ruthenium, palladium, platinum and metal nitride, for example the nitride of titanium, tungsten, tantalum, ruthenium and titanium aluminium.The method that forms this P type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.

Under preferred situation, the work function of P type metal gates electrode structure is set metal level and is followed successively by titanium nitride layer, tantalum and calorize titanium layer from bottom to top; Perhaps be titanium nitride layer, tantalum nitride layer and calorize titanium layer.

Further, the material of grid electrode layer is an aluminum or aluminum alloy.Under preferred situation, grid electrode layer is followed successively by titanium aluminide and aluminium from bottom to top.

In step S304, the planarization material grid structure is to form metal gates.

Under preferred situation, the lucky top surface that metal gate structure is planarized to groove is to expose side wall.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, be difficult to and there is no need too accurately to confirm the particular location after the planarization, therefore; Can metal gate structure be planarized to below the top surface of groove, this is conspicuous to those skilled in the art.

As an example, metal gates can be the N type metal gates utmost point, also can be the P type metal gates utmost point.Wherein, the N type metal gates extremely can be positioned at N type trap core space or N type trap I/O area; The P type metal gates extremely can be positioned at P type trap core space or P type trap I/O area.Further, the metal of the N type metal gates utmost point is the metal that work function is applicable to nmos device, and the metal of the P type metal gates utmost point is the metal that work function is applicable to the PMOS device.

In step S305, remove the top and all interlayer dielectric layers of side wall.

As an example, can remove the whole of side wall, for example use etching technics.But,, under preferred situation, only remove the top of side wall and keep the side wall of bottom in order to save time and to optimize technical process.

In step S306, form the self-aligned silicide layer on the surface in source/drain region.

As an example, on the surface of remaining side wall, the surface deposition of the surface in source/drain region, the metal gates material of metallic nickel or platinum nickel for example, finally to form the self-aligned silicide layer on the surface in source/drain region.

In step S307, form stressor layers on the surface of remaining side wall, the surface of metal gates and the surface of self-aligned silicide layer.

In sum; The method of making semiconductor device structure of the present invention just forms self-aligned silicide after metal gates forms; Therefore the situation that does not exist the high temperature in the subsequent technique that the performance of self-aligned silicide layer is exerted an influence, thus the performance of device guaranteed; The second, the method for making semiconductor device structure of the present invention, the close together between stressor layers and the source/drain region makes that the stress effect of stressor layers is apparent in view, thereby increases mobility of charge carrier speed, has improved the overall performance of semiconductor device; The 3rd, the method for making semiconductor device structure of the present invention makes full use of existing equipment and material, can not increase the complexity of production line, and manufacture method is simple, need not expend extra man power and material.

As shown in Figure 4, the sketch map of the semiconductor device structure of producing for first execution mode according to the present invention.As shown in the figure, semiconductor device structure comprises substrate 401, gate oxide 402, metal gates 403, side wall 404, source/drain region 405/406, self-aligned silicide layer 407 and stressor layers 408.

As an example, gate oxide 402 is formed on the surface of substrate 401;

As an example, metal gates 403 is formed on the surface of gate oxide 402;

As an example, side wall 404 is around metal gates 403;

As an example, source/drain region 405/406 is formed on the zone in the outside that is arranged in side wall 404 of substrate 401;

As an example, self-aligned silicide layer 407 is formed on the surface in source/drain region 405/406;

As an example, stressor layers 408 is formed on the surface of metal gates 403, the surface of side wall 404 and the surface of self-aligned silicide layer 407.

Further, according to the demand of different process, metal gates 403 can be the N type metal gates utmost point, also can be the P type metal gates utmost point.Wherein, the N type metal gates extremely can be positioned at N type trap core space or N type trap I/O area, and the P type metal gates extremely can be positioned at P type trap core space or P type trap I/O area.

Again further, according to the difference of metal gates polarity, the N type metal gates has the work function of the metal that is applicable to nmos device and sets metal level; The P type metal gates has the work function of the metal that is applicable to the PMOS device and sets metal level.

As an example, for N type metal gates electrode structure, the material that its work function is set metal level can comprise titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, for example comprises the metal carbides, nitride of these elements etc.

As an example, for P type metal gates electrode structure, the material that its work function is set metal level can comprise ruthenium, palladium, platinum and metal nitride, for example the nitride of titanium, tungsten, tantalum, ruthenium and titanium aluminium.

In sum; The method of making semiconductor device structure of the present invention just forms the self-aligned silicide layer after metal gates forms; Therefore the situation that does not exist the high temperature in the subsequent technique that the performance of self-aligned silicide layer is exerted an influence, thus the performance of device guaranteed; The second, the method for making semiconductor device structure of the present invention, the close together between stressor layers and the source/drain region makes that the stress effect of stressor layers is apparent in view, thereby has increased mobility of charge carrier speed, has improved the overall performance of semiconductor device; The 3rd, the method for making semiconductor device structure of the present invention makes full use of existing equipment, material and technology, can not increase the complexity of production line, and manufacture method is simple, need not expend extra man power and material; The 4th, the self-aligned silicide layer of semiconductor device structure of the present invention has preferable performance, higher resistance can not occur; The 5th, the stressor layers of semiconductor device structure of the present invention and the close together in source/drain region have stress effect preferably.

[second execution mode]

Method step below in conjunction with Fig. 5 A to 5I and Fig. 6 detailed description making semiconductor device structure of second execution mode according to the present invention.Fig. 5 A to 5I is depicted as the cross-sectional view of the making semiconductor device structure of second execution mode according to the present invention.

At first, shown in Fig. 5 A, front end device layer structure is provided.

As an example, front end device layer structure comprises substrate 501, said substrate 501 have at least above that first device 503 that forms and isolated by shallow trench 502 and with first device, 503 opposite polarity second devices 504.Wherein, The surface of said first device 503 is formed with the first grid oxide layer 505a and the first polysilicon gate 506a from bottom to top; The surface of said second device 504 is formed with the second gate oxide 505b and the second polysilicon gate 506b from bottom to top; The both sides of the both sides of the said first polysilicon gate 506a and the said second polysilicon gate 506b form active/drain region 508/509 by side wall 507 around the zone in, the outside that is arranged in said side wall 507 of substrate 501.Wherein, first device 503 can be nmos device, also can be the PMOS device.

Further, the material that constitutes substrate 501 can be unadulterated monocrystalline silicon, be doped with the monocrystalline silicon or the silicon-on-insulator (SOI) of impurity, can also comprise other material, for example indium antimonide, lead telluride, indium arsenide, GaAs or gallium antimonide etc.

In addition, it should be noted that front end device layer structure as herein described is not to be restrictive, but can also have other structures.For example, the surface of substrate 501 can also have the groove (not shown) that is formed with germanium silicon stressor layers; Source/drain region 508/509 can also be formed has lightly doped drain (LDD) structure; The surface of the first polysilicon gate 506a and the second polysilicon gate 506b can also have mask layer respectively; Deng.

The second, shown in Fig. 5 B, form interlayer dielectric layer 510 on the surface of the first polysilicon gate 506a, the surface of the second polysilicon gate 506b, the surface of side wall 507 and the surface in source/drain region 508/509; Then, the surface of planarization interlayer dielectric layer 510 to the surface that exposes the first polysilicon gate 506a and the second polysilicon gate 506b.

As an example, adopt cmp (CMP) method that interlayer dielectric layer 510 is carried out planarization.

Under preferred situation, just interlayer dielectric layer 510 is planarized to the top surface of the first polysilicon gate 506a and the second polysilicon gate 506b.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, be difficult to and there is no need too accurately to confirm the particular location after the planarization, therefore; Can with interlayer dielectric layer 510 be planarized to below the top surface of the first polysilicon gate 506a and the second polysilicon gate 506b or more than, this is conspicuous to those skilled in the art.

The 3rd, shown in Fig. 5 C, above second device 504, form the cover layer 511 that covers the second polysilicon gate 506b.

As an example, above second device 504, apply photoresist layer, and make public and technology such as development so that photoresist layer covers second device, 504 districts, and expose first device, 503 districts.

It should be noted that the characteristics of based semiconductor device, only need remove the polysilicon gate that forms metal gates.For the polysilicon gate that needs keep, if this polysilicon gate is the necessary element on the semiconductor device, then need not to handle especially, as an example, can stop it with photoresist; And if this polysilicon gate is not the necessary element on the semiconductor device, also can it be processed into high resistant, thereby have saved a mask plate owing to need not to form silicide barrier layer like this.Based on above-mentioned situation, method of the present invention can make polysilicon gate increase a kind of new purposes and save mask plate, thereby has strengthened the function of semiconductor device and reduced manufacturing cost.

The 4th, shown in Fig. 5 D, remove the first polysilicon gate 506a to exposing first grid oxide layer 505a, to be formed for holding the groove 512 of metal gates through etching; Then, remove cover layer 511.

As an example, adopt dry etch process to remove the first polysilicon gate 506a.

Under preferred situation, just the first polysilicon gate 506a is removed to fully the surface of first grid oxide layer 505a.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, the particular location after being difficult to and there is no need too accurately confirm to remove, therefore; Can polysilicon gate 506a be removed to below the top surface of gate oxide 505a, this is conspicuous to those skilled in the art.

It should be noted; For the ease of understanding accompanying drawing and making accompanying drawing can more clearly express different layer structures, no longer mark the Reference numeral in substrate 501, shallow trench 502, first grid oxide layer 505a, the second gate oxide 505b, the first polysilicon gate 506a, the second polysilicon gate 506b, side wall 507 and source/drain region 508/509 among following Fig. 5 E～2I.

The 5th, shown in Fig. 5 E, in groove 512, fill metal 513, to form metal gate structure;

As an example, the metal 513 of filling can be followed successively by gate dielectric layer 513a, work function setting metal level 513b and the grid electrode layer 513c of high-k (k) from bottom to top.

Further; For N type metal gates electrode structure; The metal that its work function is set metal level 513b is the metal that is applicable to nmos device, and material can comprise such as titanium, tantalum, aluminium, zirconium, hafnium and alloy thereof, for example comprises the metal carbides, nitride of these elements etc.The method that forms this N type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.

Under preferred situation, the work function of N type metal gates electrode structure is set metal level 513b and is followed successively by tantalum, titanium nitride layer and calorize titanium layer from bottom to top; Perhaps be tantalum nitride layer, titanium nitride layer and calorize titanium layer.

Again further; For P type metal gates electrode structure; The metal that its work function is set metal level 513b is the metal that is applicable to the PMOS device, and material can comprise such as ruthenium, palladium, platinum and metal nitride, for example the nitride of titanium, tungsten, tantalum, ruthenium and titanium aluminium.The method that forms this P type work function setting metal level can be PVD (physical vapour deposition (PVD)) or CVD (chemical vapour deposition (CVD)) method.

Under preferred situation, the work function of P type metal gates electrode structure is set metal level 513b and is followed successively by titanium nitride layer, tantalum and calorize titanium layer from bottom to top; Perhaps be titanium nitride layer, tantalum nitride layer and calorize titanium layer.

Further, the material of grid electrode layer 513c is an aluminum or aluminum alloy.Under preferred situation, grid electrode layer 513c is followed successively by titanium aluminide and aluminium from bottom to top.

The 6th, shown in Fig. 5 F, the planarization material grid structure is to exposing side wall 507 to form metal gates 514.

Under preferred situation, the lucky top surface that metal gate structure is planarized to groove 512 is to expose side wall 507.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, be difficult to and there is no need too accurately to confirm the particular location after the planarization, therefore; Can metal gate structure be planarized to below the top surface of groove 512, this is conspicuous to those skilled in the art.

As an example, metal gates 514 can be the N type metal gates utmost point, also can be the P type metal gates utmost point.Wherein, the N type metal gates extremely can be positioned at N type trap core space or N type trap I/O area; The P type metal gates extremely can be positioned at P type trap core space or P type trap I/O area.Further, the metal of the N type metal gates utmost point is the metal that work function is applicable to nmos device, and the metal of the P type metal gates utmost point is the metal that work function is applicable to the PMOS device.

The 7th, shown in Fig. 5 G, remove the top and all interlayer dielectric layers 510 of side wall 507.

As an example, can remove the whole of side wall 507, for example use etching technics.But in order to save time and to optimize technical process, under preferred situation, the top of only removing side wall 507 shown in Fig. 5 G, keeps the side wall 507 ' of bottom.

The 8th, shown in Fig. 5 H, 508/509 surface forms self-aligned silicide layer 515 in source/drain region.

As an example; On the surface of the second polysilicon gate 506b, the surface deposition of the surface in the surface of remaining side wall 507 (side wall 507 ' of bottom), source/drain region 508/509 and metal gates 514 material of metallic nickel or platinum nickel for example, 508/509 surface forms self-aligned silicide layer 515 in source/drain region with final.

At last, shown in Fig. 5 I, form stressor layers 516 on the surface of the second polysilicon gate 506b, the surface of remaining side wall 507 (side wall 507 ' of bottom), the surface of metal gates 514 and the surface of self-aligned silicide layer 515.

As shown in Figure 6, be the method flow diagram of the making semiconductor device structure of second execution mode according to the present invention.

In step S601, front end device layer structure is provided.

As an example, front end device layer structure comprises substrate, said substrate have at least above that first device that forms and left by shallow trench isolation and with opposite polarity second device of said first device.Wherein, The surface of said first device is formed with the first grid oxide layer and first polysilicon gate from bottom to top; The surface of said second device is formed with second gate oxide and second polysilicon gate from bottom to top; The both sides of the both sides of said first polysilicon gate and said second polysilicon gate form active/drain region by side wall is arranged in the outside of said side wall around, substrate zone.First device is nmos device or PMOS device.

In addition, it should be noted that front end device layer structure as herein described is not to be restrictive, but can also have other structures.For example, the surface of substrate can also have the groove (not shown) that is formed with germanium silicon stressor layers; Source/drain region can also be formed has lightly doped drain (LDD) structure; The surface of first polysilicon gate and second polysilicon gate can also have mask layer respectively; Deng.

In step S602, form interlayer dielectric layer on the surface of first polysilicon gate, the surface of second polysilicon gate, the surface of side wall and the surface in source/drain region; Then, the surface of planarization interlayer dielectric layer to the surface that exposes first polysilicon gate and second polysilicon gate.

Under preferred situation, just with the top surface of interlayer dielectric layer flatening to first polysilicon gate and second polysilicon gate.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, be difficult to and there is no need too accurately to confirm the particular location after the planarization, therefore; Can with interlayer dielectric layer flatening below the top surface of first polysilicon gate and second polysilicon gate or more than, this is conspicuous to those skilled in the art.

In step S603, above second device, form the cover layer that covers second polysilicon gate.

As an example, above second device, apply photoresist layer, and make public and technology such as development so that photoresist layer covers second device region, and expose first device region.

In step S604, remove the first polysilicon gate best through etching and expose first grid oxide layer, to be formed for holding the groove of metal gates; Then, remove cover layer.

As an example, adopt dry etch process to remove first polysilicon gate.

Under preferred situation, just first polysilicon gate is removed to fully the surface of first grid oxide layer.But; Should be noted that; Because the size of semiconductor transistor is more and more littler, the particular location after being difficult to and there is no need too accurately confirm to remove, therefore; Can first polysilicon gate be removed to below the top surface of first grid oxide layer, this is conspicuous to those skilled in the art.

In step S605, in groove, fill metal, to form metal gate structure;

In step S606, the planarization material grid structure is to exposing side wall to form metal gates.

In step S607, remove the top and all interlayer dielectric layers of side wall.

As an example, can remove the whole of side wall, for example use etching technics.But in order to save time and to optimize technical process, under preferred situation, the top of only removing side wall shown in Fig. 5 G, keeps the side wall of bottom.

In step S608, form the self-aligned silicide layer on the surface in source/drain region.

As an example; On the surface of second polysilicon gate, the surface deposition of the surface in the surface of remaining side wall (side wall of bottom), source/drain region and the metal gates material of metallic nickel or platinum nickel for example, finally to form the self-aligned silicide layer on the surface in source/drain region.

In step S609, on the surface of second polysilicon gate, the surface of remaining side wall (side wall of bottom), the surface of metal gates and the surface of self-aligned silicide layer form stressor layers.

As shown in Figure 7, the sketch map of the semiconductor device structure of producing for second execution mode according to the present invention.As shown in the figure, semiconductor device structure comprises substrate 701, at least one first device 703 and at least one second device 704.More specifically, said substrate 701 have at least above that first device 703 that forms and isolated by shallow trench 702 and with said first device, 703 opposite polarity second devices 704.Wherein, first device 703 can be nmos device, also can be the PMOS device.

Further, first device 703 has:

First grid oxide layer 705a, first grid oxide layer 705a is formed on the surface of first device 703 of substrate 701;

Metal gates 706a, metal gates 706a is formed on the surface of first grid oxide layer 705a;

Side wall 707a, side wall 707a is around metal gates 706a;

Source/drain region 708a/709a, source/drain region 708a/709a is formed on the zone in the outside that is arranged in side wall 707a of first device 703 of substrate 701;

Self-aligned silicide layer 710a, self-aligned silicide layer 710a is formed on the surface of source/drain region 708a/709a; And

Stressor layers 711a, stressor layers 711a are formed on the surface of metal gates 706a, the surface of side wall 707a and the surface of self-aligned silicide layer 710a.

Further, second device 704 has:

The second gate oxide 705b, the second gate oxide 705b is formed on the surface of second device 704 of substrate 701;

Polysilicon gate 706b, polysilicon gate 706b is formed on the surface of the second gate oxide 705b;

Side wall 707b, side wall 707b is around polysilicon gate 706b;

Source/drain region 708b/709b, source/drain region 708b/709b is formed on the zone in the outside that is arranged in side wall 707b of second device 704 of substrate 701;

Self-aligned silicide layer 710b, self-aligned silicide layer 710b is formed on the surface of source/drain region 708b/709b; And

Stressor layers 711b, stressor layers 711b are formed on the surface of polysilicon gate 706b, the surface of side wall 707b and the surface of self-aligned silicide layer 710b.

Further, according to the demand of different process, metal gates 706a can be the N type metal gates utmost point, also can be the P type metal gates utmost point; Wherein, N type metal gates utmost point 706a can be positioned at N type trap core space or N type trap I/O area, and P type metal gates utmost point 706a can be positioned at P type trap core space or P type trap I/O area; Polysilicon gate 706b can be formed on N type trap core space or N type trap I/O area.

As an example, for P type metal gates electrode structure, its work function is set metal level can comprise ruthenium, palladium, platinum and metal nitride, for example the nitride of titanium, tungsten, tantalum, ruthenium and titanium aluminium.

[beneficial effect of the present invention]

[industrial applicibility of the present invention]

Aforesaid semiconductor device structure and the semiconductor device structure that has according to aforesaid execution mode manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, like random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, like programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products; In various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.

The present invention is illustrated through the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by appended claims book and equivalent scope thereof.

Claims

1. a method of making semiconductor device structure is characterized in that, comprises the following steps:

E) in said groove, fill metal, to form metal gate structure;

2. method according to claim 1 is characterized in that, also comprises:

I) form stressor layers on the surface of the surface of said remaining side wall, said metal gates and the surface of said self-aligned silicide layer.

3. method according to claim 1 is characterized in that, said metal gates is the N type metal gates utmost point or the P type metal gates utmost point.

4. method according to claim 3 is characterized in that, the said N type metal gates utmost point is positioned at N type trap core space or N type trap I/O area.

5. method according to claim 3 is characterized in that, the said P type metal gates utmost point is positioned at P type trap core space or P type trap I/O area.

6. method according to claim 1 is characterized in that, said metal is that work function is applicable to the metal of nmos device or the metal that work function is applicable to the PMOS device.

7. a method of making semiconductor device structure is characterized in that, comprises the following steps:

F) remove said cover layer;

G) in said groove, fill metal, to form metal gate structure;

8. method according to claim 7 is characterized in that, also comprises:

K) form stressor layers on the surface of the surface of the surface of said second polysilicon gate, said remaining side wall, said metal gates and the surface of said self-aligned silicide layer.

9. method according to claim 7 is characterized in that, said first device is nmos device or PMOS device.

10. method according to claim 7 is characterized in that, said metal gates is the N type metal gates utmost point or the P type metal gates utmost point.

11. method according to claim 10 is characterized in that, the said N type metal gates utmost point is positioned at N type trap core space or N type trap I/O area.

12. method according to claim 10 is characterized in that, the said P type metal gates utmost point is positioned at P type trap core space or P type trap I/O area.

13. method according to claim 7 is characterized in that, said metal is that work function is applicable to the metal of nmos device or the metal that work function is applicable to the PMOS device.

14. a semiconductor device structure is characterized in that, comprising:

Substrate;

Gate oxide, said gate oxide is formed on the surface of said substrate;

Metal gates, said metal gates is formed on the surface of said gate oxide;

Side wall, said side wall is around said metal gates;

15. method according to claim 14 is characterized in that, said metal gates is the N type metal gates utmost point or the P type metal gates utmost point.

16. method according to claim 15 is characterized in that, the said N type metal gates utmost point is positioned at N type trap core space or N type trap I/O area.

17. method according to claim 15 is characterized in that, the said P type metal gates utmost point is positioned at P type trap core space or P type trap I/O area.

18. method according to claim 14 is characterized in that, said metal gates has the work function setting metal level of the metal that is applicable to nmos device or is applicable to the work function setting metal level of the metal of PMOS device.

19. a semiconductor device structure is characterized in that, comprising:

Side wall, said side wall is around said metal gates and said polysilicon gate;

20. method according to claim 19 is characterized in that, said first device is nmos device or PMOS device.

21. method according to claim 19 is characterized in that, said metal gates is the N type metal gates utmost point or the P type metal gates utmost point.

22. method according to claim 21 is characterized in that, the said N type metal gates utmost point is positioned at N type trap core space or N type trap I/O area.

23. method according to claim 21 is characterized in that, the said P type metal gates utmost point is positioned at P type trap core space or P type trap I/O area.

24. method according to claim 19 is characterized in that, said metal gates has the work function setting metal level of the metal that is applicable to nmos device or is applicable to the work function setting metal level of the metal of PMOS device.

25. an integrated circuit that comprises through the semiconductor device of making like claim 1 or 7 described methods, wherein said integrated circuit is selected from the wherein at least a of random access memory, dynamic random access memory, Synchronous Dynamic Random Access Memory, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type dynamic random access memory and radio circuit.

26. an electronic equipment that comprises through the semiconductor device of making like claim 1 or 7 described methods, wherein said electronic equipment is selected from the wherein at least a of personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera and mobile phone.

27. an integrated circuit that comprises claim 14 or 19 described semiconductor device structures, wherein said integrated circuit is selected from the wherein at least a of random access memory, dynamic random access memory, Synchronous Dynamic Random Access Memory, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type dynamic random access memory and radio circuit.

28. an electronic equipment that comprises claim 14 or 19 described semiconductor device structures, wherein said electronic equipment is selected from the wherein at least a of personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera and mobile phone.