CN102376239B - Pixel circuit of display device - Google Patents

Abstract

The present invention provides a pixel circuit of a display device, so that the voltage value transmitted to the display element is close to the received data voltage, so that the pixel circuit can faithfully transmit the data voltage to the display element. The pixel circuit of the display device includes a first write switch, a first write storage unit, a first voltage follower module and a display element. The first voltage follower module is used to detect the first data voltage stored in the first write storage unit, and according to the detection result, a corresponding first output voltage is generated at the display element end, and the output end of the first voltage follower module is controlled by a switch voltage.

Description

Pixel circuit of display device

technical field

The present invention relates to a pixel circuit, in particular to a pixel circuit of a display device.

Background technique

Flat panel displays, such as liquid crystal displays (Liquid Crystal Display, LCD), etc., have the advantages of high image quality, small size, light weight, low driving voltage, and low power consumption, so they are widely used in video recorders, personal Digital Assistant (Personal Digital Assistant, PDA), mobile phone, notebook computer, desktop computer display screen and thin digital TV and other consumer communications or electronic products, and gradually replace the cathode ray tube (Cathode Ray Tube, CRT) and Become the mainstream technology of the display.

In a general flat display device architecture, a flat display panel is composed of a pixel array, and the pixel array includes a plurality of pixel circuits. In the past, the pixel circuit was mainly composed of passive components such as capacitors and switches. Therefore, it inevitably had a charge sharing effect when transmitting image data signals, which caused a slight drop in the data signals received by the display elements in the pixel circuit. Causes the displayed pixels to produce unexpected conditions, such as: the grayscale displayed by the pixel is slightly deviated from the expected pixel grayscale on the data signal, distorted and inaccurate, etc. The charge redistribution effect often occurs in digital logic circuits. Due to the coupling capacitance inside the device, it will reduce the desired output voltage or voltage value of the signal in the circuit.

Contents of the invention

The present invention provides a pixel circuit of a display device, so that the pixel voltage value of the pixel circuit is close to the received image data voltage, so that the pixel circuit can faithfully transmit the voltage to the display element when transmitting the image data voltage, so as to reduce the internal coupling of the element Influence of capacitance and current redistribution effect.

The present invention provides a pixel circuit of a display device, which includes a first writing switch, a first writing storage unit, a first voltage follower module and a display element. The first end of the first write switch is coupled to a data line, and the first write switch is controlled by a first switch voltage. The first write-in memory unit is coupled to the second terminal of the first write-in switch, wherein the first write-in memory unit stores a first data voltage through the first write-in switch. The input terminal of the first voltage follower module is coupled to the first write-in memory unit for detecting the first data voltage stored in the first write-in memory unit, and generates a corresponding output terminal of the first voltage follower module according to the detection result. The voltage of the first output terminal of the first voltage follower module is controlled by a second switch voltage. The display element is coupled to the output terminal of the first voltage follower module for receiving the voltage of the first output terminal through the first voltage follower module during a frame period.

In an embodiment of the present invention, the above-mentioned first voltage follower module includes a first voltage follower and a first display switch. The input terminal of the first voltage follower becomes the input terminal of the first voltage follower module. The first terminal of the first display switch is coupled to the output terminal of the first voltage follower, and the second terminal thereof becomes the output terminal of the first voltage follower module, and the first display switch is controlled by the second switch voltage.

In an embodiment of the present invention, the above-mentioned first voltage follower includes an operational amplifier, the first input terminal of which becomes the input terminal of the first voltage follower, and the output terminal of the operational amplifier is coupled to the second input terminal of the operational amplifier. The terminal becomes the output terminal of the first voltage follower.

In an embodiment of the present invention, the above-mentioned first voltage follower includes a source follower, and the source follower includes a first transistor and a second transistor. The control terminal of the first transistor becomes the input terminal of the source follower, the first terminal of the first transistor receives a system voltage, and the second terminal thereof becomes the output terminal of the source follower. The control end of the second transistor receives a control voltage, the first end of the second transistor receives a common voltage, and the second end of the second transistor is coupled to the second end of the first transistor.

In an embodiment of the present invention, the above-mentioned first voltage follower module includes a first voltage follower and a first power control switch. The input end of the first voltage follower becomes the input end of the first voltage follower module, and the output end of the first voltage follower becomes the output end of the first voltage follower module. The first end of the first power control switch is coupled to the power input end of the first voltage follower, the second end of the first power control switch receives the system voltage, and the first power control switch is controlled by the second switch voltage.

In an embodiment of the present invention, a display storage unit is further included, which is coupled to the output end of the voltage follower module. Wherein, the display storage unit includes a second capacitor, the first terminal of which is coupled to the output terminal of the voltage follower module, and the second terminal of the second capacitor receives a second reference voltage.

In an embodiment of the present invention, it further includes a first conduction switch, the first end of which is coupled to the first writing memory unit, the second end of the first conduction switch is coupled to the display element, and the first conduction switch The ON switch is controlled by the first ON signal.

In an embodiment of the present invention, a second write switch, a second write memory unit and a second voltage follower module are also included. The first end of the second write switch is coupled to the data line, and the second write switch is controlled by the third switch voltage. The second write-in memory unit is coupled to the second end of the second write-in switch, wherein the second write-in memory unit stores a second data voltage through the second write-in switch. The input end of the second voltage follower module is coupled to the first end of the second write-in memory unit, and the output end of the second voltage follower module is coupled to the display element for detecting the first end stored in the second write-in memory unit. Two data voltages, and generate a corresponding second output terminal voltage at the output terminal of the second voltage follower module according to the detection result. Wherein, the output terminal of the second voltage following module is controlled by the fourth switch voltage.

In an embodiment of the present invention, the above-mentioned second voltage follower module includes a second voltage follower and a second display switch. The input terminal of the second voltage follower becomes the input terminal of the second voltage follower module. The first end of the second display switch is coupled to the output end of the second voltage follower, the second end of the second display switch becomes the output end of the second voltage follower module, and the second display switch is controlled by the fourth switch voltage.

Based on the above, the embodiment of the present invention utilizes a voltage follower composed of active components (such as operational amplifiers, source followers, etc.), so that the pixel circuit makes the voltage of the display element approximately equal to the image data voltage when transmitting the data voltage. It will not be affected by the coupling capacitance and current redistribution effect in the component.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram illustrating a pixel circuit of a display device according to a first embodiment of the pixel circuit.

FIG. 2 is a driving timing diagram illustrating a pixel circuit of a display device according to the first embodiment of the pixel circuit.

FIG. 3 is a schematic diagram illustrating a pixel circuit of a display device according to a second embodiment of the present invention.

FIG. 4 is a driving timing diagram illustrating a pixel circuit of a display device according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating a pixel circuit of a display device according to a third embodiment of the present invention.

FIG. 6 is a driving timing diagram illustrating a pixel circuit of a display device according to a third embodiment of the present invention.

FIG. 7 is a schematic circuit diagram illustrating a pixel circuit of a display device according to a fourth embodiment of the present invention.

FIG. 8 is a schematic circuit diagram illustrating a first voltage follower according to a fourth embodiment of the present invention.

FIG. 9 is a schematic circuit diagram illustrating a second display switch according to a fourth embodiment of the present invention.

FIG. 10 is a schematic circuit diagram illustrating a pixel circuit of a display device according to a fifth embodiment of the present invention.

FIG. 11 is a schematic circuit diagram illustrating a pixel circuit of a display device according to a sixth embodiment of the present invention.

FIG. 12 is a schematic diagram illustrating a pixel circuit of another display device according to the seventh embodiment of the pixel circuit.

FIG. 13 is a driving timing diagram illustrating another pixel circuit of a display device according to the seventh embodiment of the pixel circuit.

FIG. 14 is a schematic diagram illustrating a pixel circuit of another display device according to the eighth embodiment of the present invention.

FIG. 15 is a schematic diagram illustrating a pixel circuit of another display device according to the ninth embodiment of the present invention.

Description of reference symbols

100, 300, 500, 700, 1000, 1100, 1200, 1400, 1500: pixel circuit

110: First write switch T2: Waiting for display period

120: First write to storage unit T3: Display period

130: First display switch T4: Waiting for writing period

140: display storage unit T5: conduction period

150: display element T6: first write/second display period

330: The first display switch T7: The first latch period

360: The first voltage follows the module T8: The first display/second writing period

370: First voltage follower T9: Second latch period

580: First conduction switch Vcom: common voltage

1110, 1120: first power control switch Vlc: pixel voltage

1210: second write switch Vn, Vn1, Vn2: terminal voltage

1220: second write memory unit Vt: drop voltage

1230: The second display switch Vto1: The first conduction voltage

1430: Second display switch Vto2: Second conduction voltage

1460: second voltage follower module Vsw1: first switch voltage

1470: second voltage follower Vsw2: second reference voltage

1580: The second conduction switch Vref1: The first reference voltage

A, B, C: the first input terminal, the second input terminal and the output terminal of the operational amplifier

Cs1: the first capacitor Vref2: the second reference voltage

Cs2: second capacitor Vss: system voltage

Cs3: the third capacitor MN, MN1, MN2: NOMS transistors

DataLine: data line MP: PMOS transistor

OP: Operational amplifier M1～M4: Operational transistor

ΔV, ΔV1, ΔV2: voltage difference

Detailed ways

A first embodiment of a pixel circuit 100 for a display device is proposed here, please refer to FIG. 1 . FIG. 1 is a schematic diagram illustrating a pixel circuit 100 of a display device according to a first embodiment of the pixel circuit 100 . The pixel circuit 100 of the display device includes a first writing switch 110 , a first writing storage unit 120 , a first display switch 130 and a display element 150 . A first end of the first write switch 110 is coupled to a data line DataLine, and the first write switch 110 is controlled by a first switch voltage Vsw1. The first terminal of the first writing memory unit 120 is coupled to the second terminal of the first writing switch 110 , and the second terminal thereof receives a first reference voltage Vref1 . Wherein, the first writing memory unit 120 stores a first data voltage through the first writing switch 110 . A first end of the first display switch 130 is coupled to the first writing memory unit 120, wherein the first display switch 130 is controlled by a second switch voltage Vsw2. The display element 150 is coupled to the second end of the first display switch 130 , and the other end of the display element 150 receives the common voltage Vcom. The display element 150 receives the first data voltage stored by the first writing memory unit 120 through the second switch voltage Vsw2 during a frame period.

In this embodiment, the pixel circuit 100 further includes a display storage unit 140 , the first terminal of which is coupled to the second terminal of the first display switch 130 , and the second terminal of the display storage unit 140 receives the second reference voltage Vref2 . In this embodiment, the display element 150 is, for example, a liquid crystal capacitor 150 . The liquid crystal capacitor 150 drives and changes the liquid crystal angle in the liquid crystal capacitor 150 by the potential difference between the pixel voltage Vlc and the common voltage Vcom.

To describe the operation of this embodiment in detail, please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a driving timing diagram illustrating a pixel circuit 100 of a display device according to the first embodiment of the pixel circuit 100 . Hereinafter, the voltage at which the first writing memory unit 120 is coupled to the second terminal of the first writing switch 110 is referred to as a terminal voltage Vn. According to the present embodiment, each frame period of the driving sequence is mainly divided into four periods: writing period T1 , waiting display period T2 , displaying period T3 and waiting writing period T4 . The writing period T1 is a period when the first switch voltage Vsw1 is at a high level, and at this time the second switch voltage Vsw2 is at a low level. Therefore, the writing period T1 is also a period when the first writing switch 110 is in the on state and the first display switch 130 is in the off state. The first capacitor Cs1 in the first writing memory unit 120 receives the first data voltage V1 through the data line DataLine of the first writing switch 110, so the first capacitor Cs1 is convenient for storing charges at this time, so that the terminal voltage Vn is equal to The first data voltage V1. It is particularly noted here that "the terminal voltage Vn is equal to the first data voltage V1" is a circuit analysis result under ideal conditions. However, in an actual situation, if a circuit/device with non-ideal characteristics is considered, the terminal voltage Vn will be smaller than the first data voltage V1.

Then enter the waiting display period T2. The display waiting period T2 is when both the first switch voltage Vsw1 and the second switch voltage Vsw2 are at low level, and also is a period when both the first writing switch 110 and the first display switch 130 are in an off state. At this time, the first capacitor Cs1 in the first writing memory unit 120 maintains the voltage value of the terminal voltage Vn at the first data voltage V1.

Afterwards, the display period T3 is a period when the second switch voltage Vsw2 is at a high level, and the first switch voltage Vsw1 is at a low level. Accordingly, the display period T3 is also a period when the first display switch 130 is in the on state and the first writing switch 110 is in the off state. Ideally, the first data voltage V1 stored in the first capacitor Cs1 should be faithfully transmitted to the display element 150 . That is to say, after the first display switch 130 is turned on, the pixel voltage Vlc of the display element 150 should be equal to the first data voltage V1. However, due to the charge sharing effect, the charge stored in the first capacitor Cs1 is evenly distributed among the first capacitor Cs1, the second capacitor Cs2 in the display storage unit 140, and the liquid crystal capacitor 150, resulting in the display element 150 The pixel voltage Vlc is not equal to the first data voltage V1. That is to say, a voltage difference ΔV is generated between the pixel voltage Vlc and the first data voltage V1. In order to cause the pixel reduction of the display circuit 100 to cause unexpected situations, such as: the grayscale displayed by the pixel is slightly deviated from the expected pixel grayscale on the first data voltage V1, distorted and inaccurate, etc., the voltage difference ΔV must be as far as possible The land is small.

Next, it enters into the write-waiting period T4. The waiting writing period T4 is similar to the waiting display period T2. At this time, the first switch voltage Vsw1 and the second switching voltage Vsw2 are both at low level, and the first writing switch 110 and the first display switch 130 are both at the low level. Deadline. Therefore, the potential difference required to drive the liquid crystal capacitor 150 will continue to be provided by the display storage unit 140 and the liquid crystal capacitor 150 itself, and wait for the writing period T1 of the next frame to come. In other embodiments, the display storage unit 140 may be omitted due to design requirements, and the data voltage is stored by the liquid crystal capacitor 150 itself.

According to this embodiment, the pixel circuit 100 will cause the pixel voltage Vlc driving the liquid crystal capacitor 150 to have a voltage difference ΔV from the first data voltage V1, so that the liquid crystal capacitor 150 cannot correctly change the angle of its liquid crystal according to the first data voltage V1. . In order to reduce the voltage difference ΔV, the capacitance value of the first capacitor Cs1 can be increased when designing the circuit, and the first capacitor Cs1 can be designed to be much larger than the capacitance value of the second capacitor Cs2 plus the liquid crystal capacitor 150, so as to reduce the capacitance When the distribution effect occurs, the drop range of the voltage difference ΔV is reduced. However, due to the limitations of current technology and volume reduction, the capacitance values of the first capacitor Cs1 and the second capacitor Cs2 plus the liquid crystal capacitor 150 are getting closer, so the magnitude of the voltage difference ΔV gradually increases to the point where it cannot be ignored.

According to the foregoing, a second embodiment according to the present invention is proposed here to reduce the voltage difference ΔV and reduce the effect of charge redistribution, please refer to FIG. 3 . FIG. 3 is a schematic diagram illustrating a pixel circuit 300 of a display device according to a second embodiment of the present invention. The pixel circuit 300 includes a first writing switch 110 , a first writing storage unit 120 , a first voltage follower module 360 and a display element 150 . Wherein, this embodiment is similar to the pixel circuit 100 of the above-mentioned first embodiment, so the same coupling manner and operation description will not be repeated here. To clearly illustrate this embodiment, the voltage at the input terminal of the first voltage following module 360 is referred to as the terminal voltage Vn1, and the output terminal of the first voltage following module 360 is coupled to the liquid crystal capacitor 150, so the first voltage following module 360 The voltage at the first output terminal of is equal to the pixel voltage Vlc.

The difference between the pixel circuit 100 and the pixel circuit 300 is that the pixel circuit 300 includes a first voltage follower module 360, and the input end of the first voltage follower module 360 is coupled to the first writing memory unit 120 for detecting A first data voltage written into the storage unit 120, and a corresponding first output terminal voltage is generated at the output terminal of the first voltage following module 360 according to the detection result, wherein the output terminal of the first voltage following module 360 is controlled by the second Switching voltage Vsw2. According to this embodiment, the first voltage follower module 360 mainly uses active components (such as operational amplifiers, source followers, etc.) to faithfully generate the first output voltage (also known as the first output voltage) from the detected first input voltage Vn1 That is, the pixel voltage Vlc) is transmitted to the display element 150, thereby minimizing the voltage difference ΔV generated by the charge redistribution effect.

The display element 150 is coupled to the output end of the first voltage follower module 360 for receiving the first output end voltage through the first voltage follower module 360 during a frame period. In this embodiment, the first voltage follower module 360 includes a first voltage follower 370 and a first display switch 330 . The input terminal of the first voltage follower 370 becomes the input terminal of the first voltage follower module 360 . The first terminal of the first display switch 330 is coupled to the output terminal of the first voltage follower 370, the second terminal of the first display switch 330 becomes the output terminal of the first voltage follower module 360, and the first display switch 330 is controlled at the second switch voltage Vsw2. In this embodiment, the first writing storage unit 120 includes a first capacitor Cs1, and the display storage unit 140 includes a second capacitor Cs2.

In order to enable those skilled in the art to better understand the present invention, the difference between the operation modes of the pixel circuit 100 in FIG. 1 and the pixel circuit 300 in FIG. 3 will be described below, so the same operation modes will not be repeated here. Please refer to FIG. 4 . FIG. 4 is a driving timing diagram illustrating a pixel circuit 300 of a display device according to a second embodiment of the present invention. In the display period T3 of each frame period, the second switch voltage Vsw2 is at a high level, and the first switch voltage Vsw1 is at a low level. Accordingly, during the display period T3, the first display switch 130 is also in the on state, and the first writing switch 330 in the first voltage follower module 360 is in the off state. It can be known from the previous description that the voltage at the input terminal of the first voltage follower module 360 (that is, the terminal voltage Vn1) utilizes the first capacitor Cs1 in the first write storage element 120 to maintain the voltage value, and at this time the terminal voltage Vn1 The voltage value is equal to the first data voltage V1. It is particularly noted here that “the terminal voltage Vn1 is equal to the first data voltage V1” is a circuit analysis result under ideal conditions. In an actual situation, if a circuit/device with non-ideal characteristics is considered (for example, the voltage drop of the first writing switch 110 is considered), the terminal voltage Vn1 will be smaller than the first data voltage V1.

Ideally, the first voltage follower 370 in the first voltage follower module 360 will generate a corresponding first output terminal voltage (which is also the first data voltage V1) according to the terminal voltage Vn1 (the voltage value of which is the first data voltage V1). data voltage V1). However, if considering the non-ideal characteristics of the first voltage follower 370 , the voltage value of the first output terminal voltage may be different from the voltage value of the first data voltage V1 . Therefore, when the first display switch 330 is turned on, the output terminal of the first voltage follower 370 can be coupled to the display element 150, so that the pixel voltage Vlc is approximately equal to the voltage of the first output terminal of the first voltage follower 370 ( That is, the first data voltage V1). The display storage element 140 also stores charges during the display period T3 to maintain the first data voltage V1.

Then, during the waiting writing period T4, both the first writing switch 110 and the first display switch 330 are in the cut-off state. The display storage unit 140 uses the charge stored in the second capacitor Cs2 to maintain the pixel voltage Vlc approximately at the voltage value of the first data voltage V1, so as to continue to provide the potential difference required to drive the liquid crystal capacitor 150, and wait for the next screen During the writing period T1 comes.

In this embodiment, the first voltage follower module 360 is used to faithfully transmit the first data voltage V1 from the input terminal of the first voltage follower module 360 to the display element 150 , thereby reducing the voltage difference ΔV. Ideally, the voltage at the output terminal of the first voltage follower 370 can be set to be equal to the terminal voltage Vn1 (ie, the first data voltage V1 ). However, the actual first voltage follower 370 may have a slight output error (or offset). In other embodiments, the aforementioned two terminals can be turned on by adding a transmission switch, so as to improve the aforementioned output error (or offset), so that the pixel voltage Vlc is closer to the target voltage (ie, the first data voltage V1), that is, more The voltage difference ΔV is further reduced. Please refer to FIG. 5 and FIG. 6 . 5 is a schematic diagram illustrating a pixel circuit 500 of a display device according to a third embodiment of the present invention, and FIG. 6 is a driving timing diagram illustrating a pixel circuit 500 of a display device according to a third embodiment of the present invention. Wherein, this embodiment is similar to the pixel circuit 300 of the aforementioned second embodiment, so the same coupling manner and operation description will not be repeated here.

The difference between this embodiment and the second embodiment in FIG. 3 is that the pixel circuit 500 further includes a first conduction switch 580, the first end of which is coupled to the first writing storage unit 120, and the first conduction switch 580 The second end of the 580 is coupled to the display element 150, and the first conduction switch 580 is controlled by the first conduction voltage Vto1. In this embodiment, the output terminal of the first voltage follower module 360 and its input terminal have an offset voltage Vt. For example, during the display period T3, the voltage at the first output terminal of the first voltage follower module 360 (ie, the pixel voltage Vlc) should ideally be equal to the voltage at the first input terminal Vn1 (ie, the first data voltage V1 ), but actually The pixel voltage Vlc is equal to the first data voltage V1 minus the offset voltage Vt included in the first voltage follower module 360 . If the voltage difference ΔV between the first data voltage V1 and the pixel voltage Vlc (ΔV=Vt during the display period T3) is too large to ignore its influence, this embodiment uses the first conduction switch 580 to further reduce the voltage difference ΔV , detailed below.

According to the above, in the present embodiment, the conduction period T5 is added in the write waiting period T4 of the driving sequence, and the first conduction voltage Vto1 is at a high potential at this time. Thus, the first conduction switch 580 is in the on state, and the first writing switch 110 and the first display switch 330 are both in the off state. At this time, the two ends of the first conduction switch 580 are connected to cause a charge redistribution effect, so that the pixel voltage Vlc is closer to the first data voltage V1, and the voltage difference ΔV is further reduced.

The following is a more detailed description of the embodiment of the present invention. Here, the circuit structure of the first voltage follower module 360 is described in detail, please refer to FIG. 7 . FIG. 7 is a schematic circuit diagram illustrating a pixel circuit 700 of a display device according to a fourth embodiment of the present invention. This embodiment is similar to the pixel circuit 500 of the aforementioned third embodiment, so the same coupling manner and operation description will not be repeated here.

The difference is that the first voltage follower 370 includes an operational amplifier OP, and its first input terminal A (such as a non-inverting input terminal) becomes the input terminal of the voltage follower 370, and the output terminal C of the operational amplifier OP is coupled to the operational amplifier OP. The second input terminal B (for example, the inverting input terminal) of the amplifier OP becomes the output terminal of the first voltage follower 370 . In this way, the operational amplifier OP detects the voltage value on the first input terminal A (ie, the terminal voltage Vn1 ), and generates a corresponding voltage value at the output terminal C, so as to achieve the purpose of this embodiment. Those who apply this embodiment can realize the circuit design of the operational amplifier OP according to their requirements to realize the same function as mentioned above.

In this embodiment, a detailed circuit diagram of the operational amplifier OP is shown in FIG. 8 . FIG. 8 is a schematic circuit diagram illustrating a first voltage follower 370 according to a fourth embodiment of the present invention. The operational amplifier OP includes a first operational transistor M1 , a second operational transistor M2 , a third operational transistor M3 and a fourth operational transistor M4 . Wherein, the first operational transistor M1 and the second operational transistor M2 are P-channel metal oxide semiconductor (PMOS) transistors in this embodiment, and the third operational transistor M3 and the fourth operational transistor M4 are It is an N-channel metal oxide semiconductor (NMOS) transistor.

A first terminal (eg, source terminal) of the first operational transistor M1 receives the system voltage Vss, and a second terminal (eg, drain terminal) thereof is coupled to a control terminal (eg, gate terminal) of the first operational transistor M1 . A first terminal (eg, a source terminal) of the second operational transistor M2 receives the system voltage Vss, and a control terminal (eg, a gate terminal) thereof is coupled to the control terminal of the first operational transistor M1 . A first terminal (such as a drain terminal) of the third operational transistor M3 is coupled to a control terminal (such as a gate terminal) of the first operational transistor, and a second terminal (such as a source terminal) thereof receives a common voltage Vcom. The control terminal (eg gate terminal) of the third operational transistor M3 becomes the input terminal of the operational amplifier OP. The first terminal (for example, the drain terminal) of the fourth operational transistor M4 is coupled to the control terminal (for example, the gate terminal) of the fourth operational transistor M4 and the second terminal (for example, the drain terminal) of the second operational transistor M2 to form an operational amplifier. The output terminal of OP, the second terminal (for example, the source terminal) of the fourth operational transistor M4 receives the common voltage Vcom. Other unexplained operation modes of the operational amplifier OP can be easily understood and implemented by those skilled in the art, and will not be repeated here. The person applying this embodiment can replace the above-mentioned operational amplifier OP with an operational amplifier circuit with the same function according to his needs, so as to achieve the purpose of this embodiment.

In addition, those who apply this embodiment can also design the first writing switch 110 , the first display switch 330 , and the first conduction switch 580 according to their needs, so as to realize the above functions. Taking the first display switch 330 as an example here, please refer to FIG. 9 , which is a schematic circuit diagram illustrating the first display switch 330 according to a fourth embodiment of the present invention. In this embodiment, the first display switch 330 is composed of, for example, an NMOS transistor MN and a PMOS transistor MP, which is controlled by the first conduction voltage Vsw2. Other unexplained operation modes of the first display switch 330 can be easily understood and implemented by those skilled in the art, and in other embodiments, the first display switch 330 can also be realized by a single transistor, so no further details are given here.

In other embodiments, the first voltage follower 370 can also be implemented by a source follower, please refer to FIG. 10 . FIG. 10 is a schematic circuit diagram illustrating a pixel circuit of another display device according to a fifth embodiment of the present invention. This embodiment is similar to the aforementioned third embodiment, so the same coupling manner and operation instructions will not be repeated here. The source follower of the first voltage follower 370 in the pixel circuit 1000 includes a first transistor MN1 and a second transistor MN2 .

In this embodiment, the first transistor MN1 and the second transistor MN2 are, for example, NOMS transistors. The control terminal of the first transistor MN1 becomes the input terminal of the source follower 370 , the first terminal of the first transistor MN1 receives a system voltage Vss, and the second terminal of the first transistor MN1 becomes the output terminal of the source follower 370 . The control terminal of the second transistor MN2 receives a control voltage VB, and the first terminal thereof receives the common voltage Vcom. The second terminal of the second transistor MN2 is coupled to the second terminal of the first transistor MN1. Thereby, the output terminal of the source follower in the first voltage follower module 360 and its input terminal have an offset voltage Vth, so its driving sequence can use the first conduction signal Vto1 to control the first conduction as shown in FIG. The switch 580 is used to reduce the voltage difference ΔV between the first data voltage V1 and the pixel voltage Vlc, and achieve the purpose of this embodiment.

In addition, in addition to the aforementioned implementation methods, the implementation method of the output terminal of the first voltage follower module 360 being controlled by the second switch voltage Vsw2 can also use the second switch voltage Vsw2 to control the power supply of the operational amplifier OP to achieve the above purpose. Refer to Figure 11. FIG. 11 is a schematic circuit diagram illustrating a pixel circuit of a display device according to a sixth embodiment of the present invention.

The first voltage follower module 360 of the pixel circuit 1100 includes a first voltage follower 370 , a first power control switch 1110 and a first power control switch 1120 . The input terminal of the first voltage follower 370 becomes the input terminal of the first voltage follower module 360 , and the output terminal of the first voltage follower 370 becomes the output terminal of the first voltage follower module 360 . The first terminal of the first power control switch 1110 is coupled to the power input terminal of the first voltage follower 370 , and the second terminal of the first power control switch 1110 receives the system voltage Vss. The first terminal of the first power control switch 1120 is coupled to the ground input terminal of the first voltage follower 370 , and the second terminal of the first power control switch 1110 receives the common voltage Vcom.

Wherein, both the first power control switch 1110 and the first power control switch 1120 are controlled by the second switch voltage Vsw2. Since the first voltage follower 370 is composed of active components (such as: operational amplifier OP, source follower, etc.) in this embodiment, the power of the first voltage follower 370 can be controlled by controlling the power supply of the active components first output voltage. Therefore, when the second switch voltage Vsw2 is at a low level, the first power control switch 1110 and the first power control switch 1120 are turned off, and the first voltage follower 370 cannot generate the first output terminal voltage. Correspondingly, when the second switch voltage Vsw2 is at a high level, the first power control switch 1110 and the first power control switch 1120 are thus turned into a conduction state, and the first voltage follower 370 can start to operate with the power supply, so as to further The function of this embodiment is realized by controlling the pixel voltage Vlc on the display element 150 in a low level.

The first voltage follower 370 includes an operational amplifier OP in this embodiment, and its first input terminal A (for example, a non-inverting input terminal) becomes the input terminal of the first voltage follower 370, and the output terminal C of the operational amplifier OP is coupled to The second input terminal B (for example, the inverting input terminal) of the operational amplifier OP becomes the output terminal of the first voltage follower 370 . Other detailed processes of this embodiment have been included in the above-mentioned embodiments, so details are not repeated here.

From another point of view, another seventh embodiment of a pixel circuit 1200 suitable for a display device is proposed here, please refer to FIG. 12 and FIG. 13 . FIG. 12 is a schematic diagram illustrating another pixel circuit 1200 of a display device according to the seventh embodiment of the pixel circuit 1200 . FIG. 13 is a driving timing diagram illustrating another pixel circuit 1200 of a display device according to the seventh embodiment of the pixel circuit 1200 . In addition to the first writing switch 110, the first writing storage unit 120, the first display switch 130 and the display element 150, the pixel circuit 1200 also includes a second writing switch 1210, a second writing storage unit 1220 and a second A switch 1230 is displayed.

The first end of the second write switch 1210 is coupled to the data line DataLine, and the second write switch 1210 is controlled by a third switch voltage, which is equal to the second switch voltage Vsw2 in this embodiment. The second write-in storage unit 1220 is coupled to the second end of the second write-in switch 1210 , wherein the second write-in storage unit 122 stores the second data voltage via the second write-in switch 1210 . The first terminal of the second display switch 1230 is coupled to the second writing memory unit 1220, wherein the first display switch 1230 is controlled by the fourth switch voltage, which is equal to the first switch voltage Vsw1 in this embodiment. In addition, the pixel circuit 1200 also includes a display storage unit 140, which includes a second capacitor Cs2, and other details of this embodiment have been included in the above-mentioned embodiments, so they will not be repeated here.

The operation method and process of the pixel circuit 1200 are described here. To clearly illustrate this embodiment, the voltage at the first end of the first write-in memory unit 120 is referred to as the first terminal voltage Vn1, and the voltage at the first end of the second write-in memory unit 1220 is referred to as the second end point. Voltage Vn2. In the driving sequence described in this embodiment, every two frames is a cycle, so each cycle has four periods: the first writing/second display period T6, the first latch period T7, the first display period /The second writing period T8 and the second latching period T9.

During the first write/second display period T6, the first switch voltage Vsw1 is at a high level, and the second switch voltage Vsw2 is at a low level. Therefore, the first writing switch 110 and the second display switch 1230 are in the on state, while the first display switch 130 and the first writing switch 1210 are in the off state. The first capacitor Cs1 in the first writing memory unit 120 receives the first data voltage V1 through the data line DataLine of the first writing switch 110 , so that the first terminal voltage Vn1 is equal to the first data voltage V1 .

The third capacitor Cs3 in the second writing storage unit 1220 transmits the second data voltage V2 (ie, the second terminal voltage Vn2 ) stored in the previous first display/second writing period T8 to the liquid crystal capacitor 150 . Ideally, the first data voltage V1 stored in the first capacitor Cs1 should be faithfully transmitted to the display element 150 . However, due to the charge redistribution effect, actually a voltage difference ΔV2 is generated between the pixel voltage Vlc (or the second terminal voltage Vn2 ) of the display element 150 and the second data voltage V2 . At this time, the liquid crystal capacitor 150 displays the pixels of the first frame by the pixel voltage Vlc.

Then enter the first latch period T7, at this time the first switch voltage Vsw1 and the second switch voltage Vsw2 are both at low level. Therefore, the first writing switch 110 , the second writing switch 1210 , the first display switch 130 and the second display switch 1230 are all in the cut-off state. At this time, the first capacitor Cs1 in the first writing memory unit 120 maintains the voltage value of the first terminal voltage Vn1 at the first data voltage V1. The coupling capacitance between the display storage unit 140 and the liquid crystal capacitor 150 continues to maintain the potential difference required to drive the liquid crystal capacitor 150, so that the liquid crystal capacitor 150 continues to display the pixels of the first frame. In other embodiments, the display storage unit 140 may be omitted due to design requirements, and the data voltage is stored by the liquid crystal capacitor 150 itself.

After that, it enters the first display/second writing period T8. At this time, the second switch voltage Vsw2 is at a high level, while the first switch voltage Vsw1 is at a low level. Accordingly, during the first display/second writing period T8, the first display switch 130 and the second writing switch 1210 are in the on state, while the first writing switch 110 and the second display switch 1230 are in the off state. . At this time, due to the capacitive redistribution effect, a voltage difference ΔV1 is generated between the pixel voltage Vlc (ie, the first terminal voltage Vn1 ) and the first data voltage V1 of the display element 150 . At this time, the liquid crystal capacitor 150 displays the pixels of the second frame by the pixel voltage Vlc.

Then enter the second latch period T9. The state of the second latch period T9 is similar to that of the first latch period T7, and the first writing switch 110 , the second writing switch 1210 , the first display switch 130 and the second display switch 1230 are all in an off state. Therefore, the third capacitor Cs3 in the second writing memory unit 1220 maintains the voltage value of the terminal voltage Vn2 at the second data voltage V2. The coupling capacitance in the display storage unit 140 and the liquid crystal capacitor 150 continues to maintain the potential difference required to drive the liquid crystal capacitor 150, so that the liquid crystal capacitor 150 continues to display the pixels of the second picture, and waits for the next first write/second display During the arrival of T6.

According to the above, in order to reduce the voltage difference ΔV1 and the voltage difference ΔV2 as much as possible, and reduce the impact of the charge redistribution effect, the eighth embodiment of the present invention is proposed here, so that the pixel circuit transmits the data voltage The voltage can be faithfully transmitted to the liquid crystal capacitor 150 , please refer to FIG. 14 and FIG. 15 . FIG. 14 is a schematic diagram illustrating a pixel circuit of another display device according to the eighth embodiment of the present invention. FIG. 15 is a schematic diagram illustrating a pixel circuit of another display device according to the ninth embodiment of the present invention.

The difference between the eighth embodiment and the ninth embodiment and the seventh embodiment is that the eighth embodiment and the ninth embodiment use the first voltage follower module 360 and the second voltage follower module 1430 to faithfully transmit the data voltage to the liquid crystal The capacitor 150 makes the pixel voltage value of the pixel circuit close to the received data voltage. An input terminal of the first voltage follower module 360 is coupled to the first writing memory unit 120 , and an output terminal thereof is coupled to the display element 150 . The input end of the second voltage follower module 1460 is coupled to the second writing memory unit 1220 , and the output end thereof is also coupled to the display element 150 .

In addition, in order to solve the actual output error or offset voltage in the first voltage follower module 360 and the second voltage follower module 1430, the ninth embodiment further adds a first conduction switch 580 and a second conduction switch 1580 , to improve the aforementioned output error (or offset voltage), so that the pixel voltage Vlc is closer to the target voltage (ie, the first data voltage V1 or the second data voltage V2), that is, to further reduce the voltage difference ΔV1 and the voltage difference ΔV2. The first end of the second conduction switch 1580 is coupled to the second writing memory unit 1220, the second end of the second conduction switch 1580 is coupled to the display element 150, and the second conduction switch 1580 is controlled by the second guide signal. Wherein, the same or similar detailed processes of the eighth embodiment and the ninth embodiment have been included in the above-mentioned embodiments, so they will not be repeated here.

In summary, the embodiment of the present invention utilizes a voltage follower module composed of active components (such as operational amplifiers, source followers, etc.), so that the pixel circuit will not be affected by the coupling capacitance and current in the component when transmitting the data voltage. Due to the influence of the redistribution effect, the voltage of the display element is approximately equal to the image data voltage. If the voltage follower module slightly reduces the pixel voltage value due to its voltage drop during the transmission process, a conduction switch can also be added to make the pixel voltage closer to the data voltage value.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is based on the claims of the present invention.

Claims (14)

1. the image element circuit of a display device comprises:

One first write switch, its first end is coupled to a data line, and this first write switch is controlled by one first switching voltage;

One first write storage unit, it is coupled to the second end of this first write switch, and wherein this first write storage unit stores one first data voltage via this first write switch;

One first voltage follow module, its input end is coupled to this first write storage unit, be stored in this first data voltage of this first write storage unit in order to detection, and produce one first corresponding output end voltage according to testing result in the output terminal of this first voltage follow module, wherein the output terminal of this first voltage follow module is controlled by a second switch voltage, and this first switching voltage is high level from this second switch voltage during different sequential; And

One display element, couple the output terminal of this first voltage follow module, in order to during a picture, via this first voltage follow module, to receive this first output end voltage.

2. the image element circuit of display device as claimed in claim 1, wherein this first voltage follow module comprises:

One first voltage follower, its input end becomes the input end of this first voltage follow module; And

One first display switch, its first end is coupled to the output terminal of this first voltage follower, and the second end of this first display switch becomes the output terminal of this first voltage follow module, and this first display switch is controlled by this second switch voltage.

3. the image element circuit of display device as claimed in claim 2, wherein this first voltage follower comprises an operational amplifier, its first input end becomes the input end of this first voltage follower, and the output terminal of this operational amplifier is coupled to the second input end of this operational amplifier and becomes the output terminal of this first voltage follower.

4. the image element circuit of display device as claimed in claim 2, wherein this first voltage follower comprises the one source pole follower.

5. the image element circuit of display device as claimed in claim 1, wherein this first voltage follow module comprises:

One first voltage follower, its input end becomes the input end of this first voltage follow module, and the output terminal of this first voltage follower becomes the output terminal of this first voltage follow module; And

One first power control switch, its first end is coupled to the power input of this first voltage follower, and the second termination of this first power control switch is received a system voltage, and this first power control switch is controlled by this second switch voltage.

6. the image element circuit of display device as claimed in claim 5, wherein this first voltage follower comprises an operational amplifier, its first input end becomes the input end of this first voltage follower, and the output terminal of this operational amplifier is coupled to the second input end of this operational amplifier and becomes the output terminal of this first voltage follower.

7. the image element circuit of display device as claimed in claim 1, wherein this first write storage unit comprises one first electric capacity, and its first end is coupled to the second end of this first write switch, and the second termination of this first electric capacity is received one first reference voltage.

8. the image element circuit of display device as claimed in claim 1, also comprise a demonstration storage unit, and it is coupled to the output terminal of this first voltage follow module.

9. the image element circuit of display device as claimed in claim 8, wherein this demonstration storage unit comprises one second electric capacity, and its first end is coupled to the output terminal of this voltage follow module, and the second termination of this second electric capacity is received one second reference voltage.

10. the image element circuit of display device as claimed in claim 1, also comprise one first actuating switch, its first end is coupled to this first write storage unit, and the second end of this first actuating switch is coupled to this display element, and this first actuating switch is controlled by one first forward voltage.

11. the image element circuit of display device as claimed in claim 1 also comprises:

One second write switch, its first end is coupled to this data line, and this second write switch is controlled by one the 3rd switching voltage;

One second write storage unit, it is coupled to the second end of this second write switch, and wherein this second write storage unit stores one second data voltage via this second write switch;

One second voltage is followed module, its input end is coupled to this second write storage unit, the output terminal that this second voltage is followed module is coupled to this display element, be stored in this second data voltage of this second write storage unit in order to detection, and the output terminal of according to testing result, in this second voltage, following module produces one second corresponding output end voltage, the output terminal that wherein this second voltage is followed module is controlled by one the 4th switching voltage.

12. the image element circuit of display device as claimed in claim 11, wherein this second voltage is followed module and is comprised:

One second voltage follower, its input end becomes the input end that this second voltage is followed module; And

One second display switch, its first end is coupled to the output terminal of this second voltage follower, and the second end of this second display switch becomes the output terminal that this second voltage is followed module, and this second display switch is controlled by the 4th switching voltage.

13. the image element circuit of display device as claimed in claim 11, wherein this second voltage is followed module and is comprised:

One second voltage follower, its input end becomes the input end that this second voltage is followed module, and the output terminal of this second voltage follower becomes the output terminal that this second voltage is followed module; And

One second source gauge tap, its first end is coupled to the power input of this second voltage follower, and the second termination of this second source gauge tap is received a system voltage, and this second source gauge tap is controlled by the 4th switching voltage.

14. the image element circuit of display device as claimed in claim 11, also comprise one second actuating switch, its first end is coupled to this second write storage unit, and the second end of this second actuating switch is coupled to this display element, and this second actuating switch is controlled by one second forward voltage.

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