CN102364688A - A Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor - Google Patents
A Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor Download PDFInfo
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Abstract
本发明公开了一种垂直双扩散金属氧化物半导体场效应管，包括金属化漏极1、N+衬底2、N-漂移区3、深P体区5、N型重掺杂源区6、P型重掺杂区7、N型埋层沟道8、P型外延层9、栅氧化层10、多晶硅栅电极11和金属化源极12。该垂直双扩散金属氧化物半导体场效应管在导通时通过两个沟道的共同导电机制，大大减小器件的导通电阻；在阻断时通过P+N结势垒对沟道的电场屏蔽，实现较高的耐压水平，达到1000V以上。
The invention discloses a vertical double-diffused metal oxide semiconductor field effect transistor, comprising a metallized drain 1, an N + substrate 2, an N - drift region 3, a deep P body region 5, and an N-type heavily doped source region 6 , P-type heavily doped region 7 , N-type buried channel 8 , P-type epitaxial layer 9 , gate oxide layer 10 , polysilicon gate electrode 11 and metallized source 12 . When the vertical double-diffused metal oxide semiconductor field effect transistor is turned on, the on-resistance of the device is greatly reduced through the common conduction mechanism of the two channels; when it is blocked, the electric field of the channel is passed through the P + N junction barrier Shielded to achieve a higher withstand voltage level, reaching above 1000V.
Description
Technical field
The present invention relates to technical field of semiconductor device, be specifically related to a kind of vertical double-diffusion metal-oxide-semiconductor field effect transistor.
Background technology
In recent years, along with the fast development of microelectric technique, and the active demand of association areas such as automotive electronics, Aero-Space, Industry Control, electric power transportation, development novel high-power semiconductor device is increasing to receive people's concern.Power MOSFET (mos field effect transistor) is the power electronic device of new generation that on MOS integrated circuit technology basis, grows up.And VDMOS (vertical double-diffusion metal-oxide-semiconductor field effect transistor; Concrete structure sees Fig. 1 for details) have advantages such as input impedance is big, switching speed is fast, operating frequency is high, Heat stability is good, obtained extensive use at aspects such as switching power supply, power amplifiers at present.
In addition, in power device, introduce semiconductor material with wide forbidden band and become an important developing direction.Semiconductor material with wide forbidden band SiC material is compared with materials such as Si, GaAs; Have high energy gap, high saturated electron drift velocity, high critical breakdown electric field and high thermal conductivity, make it become highly desirable semi-conducting material under high frequency, high temperature and high-power applications occasion.Because SiC is present only a kind of compound semiconductor that can generate high-quality native oxide with thermal oxidation method, therefore be very suitable for making MOSFET (mos field effect transistor), IGBT high frequency power devices such as (insulated gate bipolar transistors) again.
For the VDMOS device, how to reduce its on state resistance, thereby reduce on-state loss, be the problem that the researcher pays close attention to all the time.Wherein drift zone resistance reduce to depend on reducing of drift region thickness and doping content, contradict with of the requirement of device blocking voltage the drift region parameter, therefore how to reduce the emphasis that channel resistance is research always.Especially for SiC VDMOS device; Owing to adopt the high energy ion injection technology; Aggravate the scattering of channel surface roughness, under high gate voltage, presented tangible channel carrier mobil-ity degradation, made turn resistance account for the sizable ratio of the total conducting resistance of device.In addition, there are a large amount of interfacial states in gate oxide and interface place that the heat growth forms, and accurate measurement result shows, n type SiC/SiO
2The density of states at interface is generally 7 * 10
11～5 * 10
12Cm
-2EV
-1These interfacial states are introduced electron trap on the top, forbidden band of SiC near the place on conduction band limit, and trap density raises and the index rising with grid voltage.Electron trap has not only reduced the density of electronics in the inversion layer, thereby through increasing threshold voltage the conducting electric current is reduced, and channel electrons is played the effect of scattering center, greatly reduces the mobility of channel electrons, has increased turn resistance.
In order to improve the on state characteristic of SiC MOSFET; Baliga once proposed the notion of accumulation layer channel mosfet, and promptly ACCUFET is shown in The Planar 6H-SiC ACCUFET:A New High-Voltage Power MOSFET Structure; IEEE ELECTRON DEVICE LETTERS; VOL. 18, NO. 12, and DECEMBER 1997.The characteristics of this structure are to produce a depletion region (concrete structure sees Fig. 2 for details) as thin as a wafer with P type heavy doping buried layer in the N type light dope epi-layer surface of gate oxidation under layer by layer.The impurity concentration of the degree of depth of buried regions and N type light doping section is through well-designed, to such an extent as to can make N type light doping section between oxide layer and the buried regions fully by P
+Build electromotive force in the N knot and exhaust, thereby form a normal device that closes.When opening, convert N type light dope depletion layer to electron accumulation layer, form the conductive channel of source electrode to drain electrode with positive grid voltage.Have the device of this kind structure, threshold voltage is low, and forward current is big, and conducting resistance is low, and because P
+The become a partner electric field shielding of gate oxide lower semiconductor layer of N has limited the electric field strength in the oxide layer effectively, has guaranteed the reliability of gate oxide.At document Development of High-Current 4H – SiC ACCUFET, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50; NO. 2; Among the FEBRUARY 2003, the plane buried regions MOSFET structure after having proposed to optimize, conducting resistance is 22 m Ω cm
2, withstand voltage is 550V.But as normal pass type device, what the buried regions channel mosfet just utilized the pn knot exhausts the blocking-up of keeping raceway groove certainly, so leakage current is bigger, is difficult to obtain high withstand voltage level, has limited its application in the high voltage occasion.
Summary of the invention
Problem to be solved by this invention is: how a kind of vertical double-diffusion metal-oxide-semiconductor field effect transistor is provided, and this semiconductor field has overcome the boundary defect of being mentioned in the background technology, has realized lower conducting resistance.
Technical problem proposed by the invention is to solve like this: a kind of vertical double-diffusion metal-oxide-semiconductor field effect transistor is provided, comprises metallization drain electrode 1, N
+Substrate 2, N
-Drift region 3, dark P tagma 5, N type heavy doping source region 6, P type heavily doped region 7, n type buried layer raceway groove 8, P type epitaxial loayer 9, gate oxide 10, polygate electrodes 11 and metallizing source 12, metallization drain electrode 1 is positioned at N
+Substrate 2 back sides, N
-Drift region 3 is positioned at N
+Substrate 2 fronts, N
-The top of drift region 3 is junction field effect transistor district 4 (or being called the JFET district), it is characterized in that:
Dark P tagma 5 is positioned at N
-Both sides, 3 top, drift region; Link to each other with N type heavy doping source region 6 through P type heavily doped region 7, metallizing source 12; The parasitic triode effect of suppression device; Gate oxide 10 grows on P epitaxial loayer 9 and the junction field effect transistor district 4, and the surface of gate oxide 10 is polygate electrodes 11, is provided with spacer medium between said polygate electrodes 11 and the metallizing source 12;
According to vertical double-diffusion metal-oxide-semiconductor field effect transistor provided by the present invention, it is characterized in that P type epitaxial loayer 9 is epitaxially grown layer with n type buried layer raceway groove 8, wherein P type epitaxial loayer 9 thickness are 0.1 μ m, the thickness of n type buried layer raceway groove 8 is 0.2 μ m.
According to vertical double-diffusion metal-oxide-semiconductor field effect transistor provided by the present invention, it is characterized in that P type epitaxial loayer 9 forms inversion channel when conducting, n type buried layer raceway groove 8 provides the extra electron source, produces conductivity modulation effect.
According to vertical double-diffusion metal-oxide-semiconductor field effect transistor provided by the present invention, it is characterized in that the ion injection has been carried out on the surface in junction field effect transistor district 4, make its surface doping concentration be higher than the drift region of below.
The invention provides the VDMOS structure that a kind of inversion-layer channel and buried regions raceway groove combine, this structure through the common conductive mechanism of two raceway grooves, reduces the conducting resistance of device greatly when conducting; When blocking-up, pass through P
+The N junction barrier is realized higher withstand voltage level to the electric field shielding of raceway groove, reaches more than the 1000V.Semi-conducting material of the present invention is carborundum, silicon, GaAs or gallium nitride.
Description of drawings
Fig. 1 is basic VDMOSFET (vertical DMOS field-effect transistor) device architecture.Wherein, 101 is the back face metalization drain electrode, and 102 is N type heavy doping substrate, and 103 is N type drift region; 104 is P type tagma, and 105 is N type heavy doping source region, and 106 is P type heavy doping contact zone; 107 is gate oxide, and 108 is polygate electrodes, and 109 are metallization source electrode;
Fig. 2 is the ACCUFET (accumulation type NMOS N-channel MOS N field-effect transistor) that people such as Baliga proposes, and wherein, 201 is the back face metalization drain electrode; 202 is N type heavy doping substrate, and 203 is N type drift region, and 204 is P type heavy doping tagma; 205 is N type heavy doping source region, and 206 is the accumulation layer channel region, and 207 is gate oxide; 208 is polygate electrodes, and 209 are metallization source electrode.
Fig. 3 is planar gate device architecture figure of the present invention, the VDMOS device that a kind of buried regions raceway groove combines with surperficial inversion channel.Wherein, 1 is the metallization drain electrode, and 2 is N
+Substrate, 3 is N
-The drift region, 4 is the junction field effect transistor district, and 5 is dark P tagma, and 6 is N type heavy doping source region, and 7 is P type heavily doped region, and 8 is the n type buried layer raceway groove, and 9 is P type epitaxial loayer, and 10 is gate oxide, and 11 is polygate electrodes, and 12 is metallizing source.
Fig. 4 is a trench-gate device structure chart of the present invention.Wherein, 1 is the metallization drain electrode, and 2 is N
+Substrate, 3 is N
-The drift region, 4 is P type tagma, and 5 is N type heavy doping source region, and 6 is P type heavily doped region, and 7 is the n type buried layer raceway groove, and 8 is P type epitaxial loayer, and 9 is gate oxide, and 10 is polygate electrodes, and 11 is N type heavily doped region, and 12 is metallizing source.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is elaborated:
Technical scheme of the present invention is following, and its basic structure is as shown in Figure 3, comprises metallization drain electrode 1, N
+Substrate 2, N
-Drift region 3, junction field effect transistor district 4, dark P tagma 5, N type heavy doping source region 6, P type heavily doped region 7, n type buried layer raceway groove 8, P type epitaxial loayer 9, gate oxide 10, polygate electrodes 11, metallizing source 12.Metallization drain electrode 1 is positioned at N
+Substrate 2 back sides, N
-Drift region 3 is positioned at N
+Substrate 2 fronts; Dark P tagma 5 is positioned at N
-Both sides, 3 top, drift region link to each other the parasitic triode effect of suppression device through P type heavily doped region 7, metallizing source 12 with N type heavy doping source region 6; N
-The top of drift region 3 is called the JFET district of VDMOS traditionally, between N type heavy doping source region 6 and JFET district 4, has two-layer conductive structure, and the below is a n type buried layer raceway groove 8, and the top is a P type epitaxial loayer 9, is used to form inversion channel; Gate oxide 10 grows on P epitaxial loayer 9 and the JFET district 4, and the surface of gate oxide 10 is polygate electrodes 11, is spacer medium between polygate electrodes 11 and the metallizing source 12.In this technical scheme, P type epitaxial loayer 9 is very thin epitaxial loayer with n type buried layer raceway groove 8, and thickness is respectively 0.1 μ m and 0.2 μ m.
In the VDMOS device provided by the present invention, have a MIS structure that is made up of polysilicon gate 11, gate oxide 10 and P type epitaxial loayer 9, there are two PN junction structures that are made up of P type epitaxial loayer 9, buried regions raceway groove 8 and dark P tagma 5 again in its below.Two dark P tagmas 5 constitute JFET (junction field effect transistor) structure with the N type drift region that is clipped in wherein.In design, the thickness of N type drift region 3 and concentration directly influence the blocking voltage of device, and in general, thicker, concentration are low more, and blocking voltage is high more, but drift zone resistance is big more simultaneously.Therefore must consider compromise to the design of drift region parameter.
When each electrode of device did not add any voltage, the very thin n type buried layer raceway groove 8 that is clipped between P type epitaxial loayer 9 and the JFET district 4 was not had the current path of drain-to-source by two PN junctions up and down from the common pinch off of depletion region.When gate electrode and source ground, drain electrode is when adding high pressure, and device is operated in blocking state, this moment two dark P tagmas 5 and N
-The PN junction depletion region that drift region 3 forms combines; With the complete pinch off of the conductive path of drain-to-source, leakage current is very little, and the while produces the electric field shielding effect to the channel region of top again; Prevent channel punchthrough and oxide layer breakdown phenomenon, avalanche breakdown takes place up to the PN junction place.
When polygate electrodes 11 added positive bias and reaches threshold voltage, P type epitaxial loayer 9 surperficial transoids produced a large amount of electronics.Gate oxide thickness is very thin; Have only tens nanometers, the grid-control of device is very capable, simultaneously because P type epitaxial loayer 9 very thin thickness; Be merely 0.1 μ m; If choose suitable doping content, then this layer thickness can be less than the maximum depletion width of the MOS structure of Theoretical Calculation, especially for forbidden band broad, material that intrinsic carrier concentration is lower.At this moment; Gate potential continues to increase, and just can have influence on P type epitaxial loayer 9 and the PN junction potential barrier that n type buried layer raceway groove 8 forms, and makes its reduction; Electronics in the n type buried layer raceway groove 8 just can be injected in the P type epitaxial loayer 9 in a large number; Improve carrier concentration greatly, form conductivity modulation effect, thereby reduce break-over of device resistance.Because gate oxide 10 is that growth obtains on P type epitaxial loayer 9, so the roughness of oxide layer and semiconductor material interface is lower, surface scattering is less to the influence of carrier mobility.Adopt the annealing process behind the new growth of gate oxide layer again, make interface trap density lower, further improved the channel carrier mobility.In addition, the JFET district is carried out once follow-up ion inject, increased the doping content in JFET district, when conducting, expanded the migration path of electronics, reduced JFET district resistance.
The high pressure VDMOS device that this surface inversion channel combines with the buried regions raceway groove, the employing ion injects the technology with outer layer growth, is satisfying under the prerequisite of high withstand voltage level, realizes lower conducting resistance.
As an embodiment, the present invention---the VDMOS device that surperficial inversion channel combines with buried channel, as shown in Figure 3 with the SiC material manufacture, can prepare through following method, processing step is:
One, the SiC substrate is prepared, and adopts N type heavy doping 4H-SiC substrate, and doping content is 1 * 10
19Cm
-3, its crystal orientation is (0001), thickness is 5 μ m.
Two, vapour phase epitaxy method is adopted in N drift region growth, utilizes monotectic axle technology, the N epitaxial loayer of the 7 μ m that under 1600 ℃, on substrate, grow, and doping content is 1.2 * 10
16Cm
-3
Three, with P buried regions mask, to inject aluminium and form dark P tagma, doping content is 3 * 10
18Cm
-3
Four, epitaxial growth n buried regions, doping content are 2 * 10
17Cm
-3, thickness is 0.2 μ m.
Five, growth p epitaxial loayer, doping content is 3 * 10
17Cm
-3, thickness is 0.1 μ m.
Six, use the source region mask, inject phosphorus and form N type heavy doping source region, peak doping concentration is 1 * 10
19Cm
-3
Seven, with heavy doping P contact mask, to inject aluminium and form P type heavily doped region, peak doping concentration is 1 * 10
19Cm
-3
Eight, use the JFET region mask board, inject aluminium on surface, JFET district, peak concentration is 2 * 10
16Cm
-3
Nine, in argon atmosphere, 1600 ℃ of following rapid thermal annealings 5 minutes activate and inject ion.
Ten, adopt pyrogenic technique of oxidation down at 1150 ℃,, in the nitric oxide atmosphere, annealed 2 hours down for 1175 ℃ subsequently with 2.5 hours thick thin oxide layers of generation 50nm.The polysilicon of vapor deposition 0.6 μ m injects phosphorus and forms the heavy doping of N type, and peak concentration is 1 * 10
20Cm
-3Form gate oxide and polygate electrodes with photoetching of polysilicon gate mask and etching.
11, silicon dioxide layer is isolated in deposit, forms the source region contact hole with contact mask photoetching and etching, and depositing metal source electrode, electrode material are nickel.
12, deposit nickel in the back side forms the metallization drain electrode.
In addition, the double channel structure among the present invention also can be applicable to trench gate mosfet, as shown in Figure 4.Its operation principle is similar with planar gate VDMOS device, and groove structure utilizes RIE (reactive ion etching) to form, and thin P layer under the trench gate and the epitaxial growth all capable of using of thin N layer obtain.Than planar gate VDMOS device, there is not the JFET district in the trench gate mosfet, electronics directly flows into the drift region from the source region through raceway groove during conducting, has shortened circulation path, and conducting resistance is littler; The PN junction barrier region of N thin layer under the trench gate and the formation of P thin layer has been weakened the electric field of groove grid bottom sharp corner to a certain extent and has been concentrated simultaneously, has improved the reliability of gate oxide.
As an embodiment, trench gate mosfet can prepare through following method, and processing step is:
One, the SiC substrate is prepared, and adopts N type heavy doping 4H-SiC substrate, and doping content is 1 * 10
19Cm
-3, its crystal orientation is (0001).
Two, vapour phase epitaxy method is adopted in N drift region growth, utilizes monotectic axle technology, the N epitaxial loayer of the 9 μ m that under 1600 ℃, on substrate, grow, and doping content is 1.0 * 10
16Cm
-3
Three, adopt the grow P type epitaxial loayer of 1.5 μ m of vapour phase epitaxy method, in order to generate P type tagma, doping content is 3 * 10
18Cm
-3
Four, use the source region mask, inject phosphorus and form N type heavy doping source region, peak doping concentration is 1 * 10
19Cm
-3, junction depth is controlled to be 0.5 μ m.
Five, with heavy doping P contact mask, to inject aluminium and form P type heavily doped region, peak doping concentration is 1 * 10
19Cm
-3, junction depth is controlled to be 0.5 μ m.
Six, in argon atmosphere, 1600 ℃ of following rapid thermal annealings 5 minutes activate and inject ion.
Seven, use nickel metal mask version, utilize reactive ion etching (RIE), carve the dark gate trench of 2 μ m with SF6.
Eight, under 950 ℃, utilize wet-oxygen oxidation to wafer heat treatment 15 minutes, and remove oxide layer, to improve the flute surfaces roughness.
Nine, epitaxial growth N type epitaxial loayer, doping content is 2 * 10
17Cm
-3, thickness is 0.2 μ m.
Ten, epitaxial growth P type epitaxial loayer, doping content is 3 * 10
17Cm
-3, thickness is 0.1 μ m.
11, adopt pyrogenic technique of oxidation down at 1150 ℃,, in the nitric oxide atmosphere, annealed 2 hours down for 1175 ℃ subsequently with 2.5 hours thick thin oxide layers of generation 50nm.The polysilicon of vapor deposition 0.6 μ m.Form gate oxide and polygate electrodes with photoetching of polysilicon gate mask and etching.
12, inject phosphorus and form N type contact zone, and polygate electrodes is mixed, peak concentration is 1 * 10
20Cm
-3
13, the outer unnecessary thin-film epitaxy structure of etching groove, the depositing metal source electrode is also graphical, and electrode material is a nickel.
14, in wafer surface deposit silicon dioxide passivation layer.
15, deposit nickel in the back side forms the metallization drain electrode.
Claims (4)
1. a vertical double-diffusion metal-oxide-semiconductor field effect transistor comprises metallization drain electrode (1), N
+Substrate (2), N
-Drift region (3), dark P tagma (5), N type heavy doping source region (6), P type heavily doped region (7), gate oxide (10), polygate electrodes (11) and metallizing source (12), metallization drain electrode (1) is positioned at N
+Substrate (2) back side, N
-Drift region (3) is positioned at N
+Substrate (2) front, N
-The top of drift region (3) is junction field effect transistor district (4), it is characterized in that: 1. dark P tagma (5) is positioned at N
-Both sides, top, drift region (3); Link to each other with N type heavy doping source region (6) through P type heavily doped region (7), metallizing source (12); The parasitic triode effect of suppression device; Gate oxide (10) grows on P epitaxial loayer (9) and junction field effect transistor district (4), and the surface of gate oxide (10) is polygate electrodes (11), is provided with spacer medium between said polygate electrodes (11) and the metallizing source (12);
2. between N type heavy doping source region (6) and junction field area under control (4), be provided with two-layer conducting channel structure: n type buried layer raceway groove (8) and P type epitaxial loayer (9); Said n type buried layer raceway groove (8) is arranged on the below; Said P type epitaxial loayer (9) is placed on the top, is used to form inversion channel.
2. vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1; It is characterized in that; P type epitaxial loayer (9) and n type buried layer raceway groove (8) are epitaxially grown layer, and wherein P type epitaxial loayer (9) thickness is 0.1 μ m, and the thickness of n type buried layer raceway groove (8) is 0.2 μ m.
3. vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1 is characterized in that, P type epitaxial loayer (9) forms inversion channel when conducting, and n type buried layer raceway groove (8) provides the extra electron source, produces conductivity modulation effect.
4. vertical double-diffusion metal-oxide-semiconductor field effect transistor according to claim 1 is characterized in that, the ion injection has been carried out on the surface of junction field effect transistor district (4), makes its surface doping concentration be higher than the drift region of below.
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103940885A (en) * | 2014-03-18 | 2014-07-23 | 复旦大学 | Ion sensitive field effect transistor and preparation process thereof |
| CN104319292A (en) * | 2014-11-06 | 2015-01-28 | 株洲南车时代电气股份有限公司 | Novel silicon carbide MOSFET and manufacturing method thereof |
| CN106409915A (en) * | 2016-11-25 | 2017-02-15 | 东莞市联洲知识产权运营管理有限公司 | Vertical double-diffusion metal oxide semiconductor field effect transistor |
| CN107895738A (en) * | 2017-11-03 | 2018-04-10 | 中国电子科技集团公司第五十五研究所 | A kind of trap locally highly doped MOS type device and preparation method |
| CN109728097A (en) * | 2018-12-29 | 2019-05-07 | 中山汉臣电子科技有限公司 | A kind of power semiconductor MOS device and preparation method thereof |
| CN110021660A (en) * | 2019-04-16 | 2019-07-16 | 西安电子科技大学 | AlGaN/GaN hetero-junctions vertical-type field effect transistor and preparation method thereof |
| CN110047931A (en) * | 2019-04-16 | 2019-07-23 | 西安电子科技大学 | Silicon carbide plane vertical-type field effect transistor and preparation method thereof |
| CN111081759A (en) * | 2019-12-10 | 2020-04-28 | 深圳第三代半导体研究院 | Enhanced silicon carbide MOSFET device and manufacturing method thereof |
| CN112466755A (en) * | 2020-11-17 | 2021-03-09 | 深圳宝铭微电子有限公司 | MOS transistor and manufacturing process thereof |
| CN112466936A (en) * | 2020-12-21 | 2021-03-09 | 厦门芯一代集成电路有限公司 | High-voltage IGBT device and preparation method thereof |
| CN114975602A (en) * | 2022-07-29 | 2022-08-30 | 深圳芯能半导体技术有限公司 | High-reliability IGBT chip and manufacturing method thereof |
| CN116613215A (en) * | 2023-06-26 | 2023-08-18 | 陕西亚成微电子股份有限公司 | Linear planar power VDMOS structure and preparation method thereof |
| CN116759461A (en) * | 2023-08-18 | 2023-09-15 | 深圳市冠禹半导体有限公司 | High-temperature-stability power MOSFET device and preparation method thereof |
| CN118538613A (en) * | 2024-07-15 | 2024-08-23 | 扬州扬杰电子科技股份有限公司 | Planar gate MOSFET capable of reducing on-resistance and preparation method thereof |
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Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103940885B (en) * | 2014-03-18 | 2017-11-28 | 复旦大学 | Ion-sensitive field effect transistor and its preparation technology |
| CN103940885A (en) * | 2014-03-18 | 2014-07-23 | 复旦大学 | Ion sensitive field effect transistor and preparation process thereof |
| CN104319292A (en) * | 2014-11-06 | 2015-01-28 | 株洲南车时代电气股份有限公司 | Novel silicon carbide MOSFET and manufacturing method thereof |
| CN106409915A (en) * | 2016-11-25 | 2017-02-15 | 东莞市联洲知识产权运营管理有限公司 | Vertical double-diffusion metal oxide semiconductor field effect transistor |
| CN107895738B (en) * | 2017-11-03 | 2020-02-18 | 中国电子科技集团公司第五十五研究所 | A kind of MOS device with high local doping of well and preparation method thereof |
| CN107895738A (en) * | 2017-11-03 | 2018-04-10 | 中国电子科技集团公司第五十五研究所 | A kind of trap locally highly doped MOS type device and preparation method |
| CN109728097A (en) * | 2018-12-29 | 2019-05-07 | 中山汉臣电子科技有限公司 | A kind of power semiconductor MOS device and preparation method thereof |
| CN109728097B (en) * | 2018-12-29 | 2022-01-11 | 安建科技(深圳)有限公司 | Power semiconductor MOS device and preparation method thereof |
| CN110021660A (en) * | 2019-04-16 | 2019-07-16 | 西安电子科技大学 | AlGaN/GaN hetero-junctions vertical-type field effect transistor and preparation method thereof |
| CN110047931A (en) * | 2019-04-16 | 2019-07-23 | 西安电子科技大学 | Silicon carbide plane vertical-type field effect transistor and preparation method thereof |
| CN110021660B (en) * | 2019-04-16 | 2022-04-01 | 西安电子科技大学 | AlGaN/GaN heterojunction vertical field effect transistor and manufacturing method thereof |
| CN111081759A (en) * | 2019-12-10 | 2020-04-28 | 深圳第三代半导体研究院 | Enhanced silicon carbide MOSFET device and manufacturing method thereof |
| CN111081759B (en) * | 2019-12-10 | 2022-07-15 | 深圳第三代半导体研究院 | Enhanced silicon carbide MOSFET device and manufacturing method thereof |
| CN112466755A (en) * | 2020-11-17 | 2021-03-09 | 深圳宝铭微电子有限公司 | MOS transistor and manufacturing process thereof |
| CN112466936A (en) * | 2020-12-21 | 2021-03-09 | 厦门芯一代集成电路有限公司 | High-voltage IGBT device and preparation method thereof |
| CN114975602A (en) * | 2022-07-29 | 2022-08-30 | 深圳芯能半导体技术有限公司 | High-reliability IGBT chip and manufacturing method thereof |
| CN114975602B (en) * | 2022-07-29 | 2022-11-08 | 深圳芯能半导体技术有限公司 | High-reliability IGBT chip and manufacturing method thereof |
| CN116613215A (en) * | 2023-06-26 | 2023-08-18 | 陕西亚成微电子股份有限公司 | Linear planar power VDMOS structure and preparation method thereof |
| CN116759461A (en) * | 2023-08-18 | 2023-09-15 | 深圳市冠禹半导体有限公司 | High-temperature-stability power MOSFET device and preparation method thereof |
| CN118538613A (en) * | 2024-07-15 | 2024-08-23 | 扬州扬杰电子科技股份有限公司 | Planar gate MOSFET capable of reducing on-resistance and preparation method thereof |
| CN118538613B (en) * | 2024-07-15 | 2025-01-28 | 扬州扬杰电子科技股份有限公司 | A planar gate MOSFET with reduced on-resistance and a method for manufacturing the same |
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