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CN102361443B - Single-event-upset resistant resettable scan structure D trigger - Google Patents

Single-event-upset resistant resettable scan structure D trigger Download PDF

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CN102361443B
CN102361443B CN 201110323927 CN201110323927A CN102361443B CN 102361443 B CN102361443 B CN 102361443B CN 201110323927 CN201110323927 CN 201110323927 CN 201110323927 A CN201110323927 A CN 201110323927A CN 102361443 B CN102361443 B CN 102361443B
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nmos transistor
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CN102361443A (en
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池雅庆
孙永节
李鹏
梁斌
杜延康
刘祥远
陈建军
何益百
秦军瑞
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National University of Defense Technology
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Abstract

本发明公开了一种抗单粒子翻转可复位的扫描结构D触发器，目的是提高抗单粒子翻转可复位的扫描结构D触发器的抗单粒子翻转能力。它由时钟电路、扫描控制缓冲电路、复位缓冲电路、主锁存器、从锁存器、输出缓冲电路组成；主锁存器由十八个PMOS管和十八个NMOS管组成，从锁存器由十二个PMOS管和十二个NMOS管组成，主锁存器和从锁存器均进行了双模冗余加固，且主锁存器和从锁存器中C2MOS电路结构均进行了改进，即分离互为冗余的C2MOS电路中的上拉电路和下拉电路。本发明抗单粒子翻转的扫描结构D触发器的抗单粒子翻转能力强，适合用于抗单粒子翻转加固集成电路的标准单元库，应用于航空、航天等领域。

Figure 201110323927

The invention discloses a resettable anti-single-event flip-flop scanning structure D flip-flop, aiming at improving the anti-single-event flip-flop of the anti-single-event flip-flop resettable scanning structure D flip-flop. It consists of a clock circuit, a scan control buffer circuit, a reset buffer circuit, a master latch, a slave latch, and an output buffer circuit; the master latch consists of eighteen PMOS transistors and eighteen NMOS transistors, and the slave latch The device is composed of twelve PMOS transistors and twelve NMOS transistors. Both the master latch and the slave latch have been reinforced with dual-mode redundancy, and the C 2 MOS circuit structure of the master latch and the slave latch are both An improvement is made to separate the pull-up circuit and the pull-down circuit in the mutually redundant C 2 MOS circuit. The anti-single-event flip-flop scanning structure D flip-flop of the present invention has strong anti-single-event flip-flop ability, is suitable for standard cell libraries of anti-single-event flip-reinforced integrated circuits, and is applied in aviation, aerospace and other fields.

Figure 201110323927

Description

The reducible Scan Architecture d type flip flop of anti-single particle overturn
Technical field
The present invention relates to a kind of D master-slave flip-flop with resetting structure and Scan Architecture, particularly the reducible Scan Architecture d type flip flop of a kind of anti-single particle overturn (signal event upset).
Background technology
In cosmic space, there are a large amount of high energy particles (proton, electronics, heavy ion) and charged particle.After integrated circuit is subject to the bombardment of these high energy particles and charged particle, in integrated circuit, can produce electronic impulse, may make the original level of IC interior node overturn, this effect is called single-particle inversion (SEU).The LET(linear energy transfer of single-particle bombardment integrated circuit) value is higher, and the electronic impulse of generation is stronger.The integrated circuit used in the Aeronautics and Astronautics field all can be subject to the threat of single-particle inversion, makes the integrated circuit job insecurity, even produces fatal mistake, therefore develops advanced integrated circuit anti-single particle overturn reinforcement technique particularly important.
The anti-single particle overturn reinforcement technique of integrated circuit can be divided into system-level reinforcing, the circuit level is reinforced and device level is reinforced.The IC reliability of system-level reinforcing is high, but chip area is large, power consumption is large, the speed of service is slow.The integrated circuit speed of service that device level is reinforced is fast, and chip area is little, low in energy consumption, but the device level reinforcing realizes that difficulty is large, and cost is high.The IC reliability that the circuit level is reinforced is high, chip area, power consumption and the speed of service are better than the integrated circuit of system-level reinforcing, and realizing that difficulty and cost are less than the integrated circuit that device level is reinforced, is very important integrated circuit anti-single particle overturn reinforcement means.
D type flip flop is to use one of maximum unit in sequential logical circuit, and its anti-single particle overturn ability has directly determined the anti-single particle overturn ability of integrated circuit.D type flip flop is carried out to the circuit level and reinforce the anti-single particle overturn ability that can under less chip area, power consumption and cost, effectively improve integrated circuit.
Traditional d type flip flop is D master-slave flip-flop, generally by the main latch with from the level series of latches, forms, and it is the effective ways of realizing that the d type flip flop anti-single particle is reinforced that the anti-single particle overturn of latch is reinforced.The people such as T.Clain are at IEEE Transaction on Nuclear Science(IEEE atomic energy science journal) on " Upset Hardened Memory Design for Submicron CMOS Technology " (the memory cell design is reinforced in upset under the submicron CMOS technology) (December in 1996 the 6th phases 43 volume of delivering, 2874th ~ 2878 pages) latch that a kind of redundancy is reinforced proposed, this latch has increased an inverter and a feedback loop on the basis of classical latch structure, with original inverter and feedback loop redundant circuit each other.In inverter, the input of N pipe separates with the input of P pipe, connects respectively two feedback loops, C in feedback loop 2the input of the N of MOS circuit pipe and P pipe is respectively from the output of two inverters.Signal input and the signal of this latch are preserved by C 2the MOS clock circuit is controlled.The latch advantage that this redundancy is reinforced is: the trigging signal produced while bombarding a node can return to original state by the correct level of corresponding node in its redundant circuit.The deficiency of the latch that this redundancy is reinforced is: two of inputs are the C of redundancy each other 2the MOS circuit draws PMOS pipe and a pull-down NMOS pipe on sharing one, make C in feedback loop 2there is an indirect pathway between the output node of MOS circuit and redundant circuit corresponding node, when the single-particle bombardment makes this C 2the level upset of MOS circuit output node, this trigging signal can propagate into along indirect pathway the corresponding node of redundant circuit, if the LET value of single-particle bombardment is higher, two each other the circuit of redundancy level all can occur overturns, finally make the output of latch also overturn.The d type flip flop that traditional redundancy that the series of latches of being reinforced by two this kind of redundancies forms is reinforced, the LET value of bombarding when single-particle is higher, two each other the circuit of redundancy level upset also all can occur, finally make the output of the d type flip flop that traditional redundancy reinforces also overturn.The people such as R.Naseer are in the 48th IEEE International Midwest Symposium on Circuits the 48th IEEE circuit of and Systems(and the international conference of system Midwest) on " The DF-DICE Storage Element for Immunity to Soft Errors " (to the DF-DICE memory cell of soft error immunity) delivered the latch that the similar redundancy of a kind of and above-mentioned latch structure is reinforced has also been proposed.Two C of this latch input 2the MOS circuit is fully independently, two each other in the circuit of redundancy corresponding node do not have indirect pathway, overcome the weak point of the latch that redundancy that the people such as T.Clain propose reinforces.But the latch that the redundancy that the people such as R.Naseer propose is reinforced has used passgate structures in feedback loop, when a node is subject to the single-particle bombardment that upset occurs, its redundant circuit feeds back to this node by correct level by transmission gate.Because the noise margin of passgate structures is lower, the signal feedback ability of feedback loop a little less than, when the LET value of single-particle bombardment is higher, feedback loop can not make this node recover correct level, has had a strong impact on this latch anti-single particle overturn ability.The d type flip flop that traditional redundancy that the series of latches of being reinforced by two this kind of redundancies forms is reinforced, when the LET value of single-particle bombardment is higher, also can be because of the passgate structures in feedback loop, can not make this node recover correct level, affect the d type flip flop anti-single particle overturn ability that this tradition redundancy is reinforced.
The Chinese patent that the patent No. is CN101499788A discloses the d type flip flop of a kind of anti-single particle overturn and single event transient pulse.This invention is the d type flip flop that a kind of structure is similar to the time sampling structure, comprises two variable connectors, two delay circuits, two shutter circuit and three inverters, has realized that the anti-single particle overturn of d type flip flop is reinforced.Owing to adopting delay circuit and shutter circuit to shield the electronic impulse that bombardment produces; when the LET value of single-particle bombardment is higher; the electronic impulse width can be greater than the time of delay of delay circuit; the output level of shutter circuit is overturn, greatly reduce the anti-single particle overturn ability of this d type flip flop.
Common D master-slave flip-flop is unfavorable at test phase, circuit being detected, and makes test job become very loaded down with trivial details, complicated.Add Scan Architecture on common D master-slave flip-flop architecture basics, can effectively simplify circuit test work, at test phase, can control by sweep signal the input of D master-slave flip-flop and then control circuit state.
Some integrated circuit needs the state of d type flip flop in the control integration circuit, forces the d type flip flop output low level and the data of wherein storage are set to logical zero.Increase reset circuit and reset signal input on the original architecture basics of Scan Architecture d type flip flop, can realize the resetting structure of d type flip flop, and control the reset function of d type flip flop by reset signal.But current reducible Scan Architecture d type flip flop anti-single particle overturn ability is all not high, is unfavorable for using in the integrated circuit (IC) chip in the fields such as Aeronautics and Astronautics.
Summary of the invention
The technical problem to be solved in the present invention is, for the not high problem of the reducible Scan Architecture d type flip flop of current anti-single particle overturn anti-single particle overturn ability, propose the reducible Scan Architecture d type flip flop of a kind of anti-single particle overturn, it can work and not produce single-particle inversion under the single-particle bombardment of higher LET value.
The reducible Scan Architecture d type flip flop of anti-single particle overturn that the present invention proposes is by clock circuit, scan control buffer circuit, the buffer circuit that resets, main latch, form from latch, output buffer.
The reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention has five inputs and two outputs.Five inputs are respectively that CK is that clock signal input part, D are that data-signal input, SE are that scan control signal input, SI are that scan data input terminal and RN are reseting input signal; Two outputs are respectively Q and QN, Q and a pair of contrary data-signal of QN output.
Clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, first order inverter and second level inverter, consists of; First order inverter is comprised of a PMOS pipe and a NMOS pipe, and the grid Pg1 of a PMOS pipe connects CK, the drain electrode Nd1 of drain electrode Pd1 connection the one NMOS pipe, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is comprised of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, the drain electrode Nd2 of drain electrode Pd2 connection the 2nd NMOS pipe, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.
The scan control buffer circuit has an input and an output, and input is SE, and output is SEN.The scan control buffer circuit is comprised of the 3rd PMOS pipe and the 3rd NMOS pipe.The substrate of the 3rd PMOS pipe all is connected power vd D with source electrode Ps3, the equal ground connection VSS of the substrate of the 3rd NMOS pipe and source electrode Ns3.The grid Pg3 of the 3rd PMOS pipe connects SE, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and as the output SEN of scan control buffer circuit; The grid Ng3 of the 3rd NMOS pipe connects SE, and drain electrode Nd3 connects Pd3.
The buffer circuit that resets has an input and an output, and input is RN, and output is R.The buffer circuit that resets is an one-level inverter, and wherein the grid Pg37 of the 37 PMOS pipe connects RN, and drain electrode Pd37 connects the drain electrode Nd37 of the 37 NMOS pipe also as the output R of the buffer circuit that resets, and source electrode Ps37 connects power vd D; The 37 NMOS tube grid Ng37 connects RN, and drain electrode Nd37 connects Pd37, source electrode Ns37 ground connection VSS.
Main latch and be the latch that redundancy is reinforced from latch, and also comprise Scan Architecture in main latch.Main latch and from series connection before and after latch, and all with clock circuit, with the buffer circuit that resets, be connected.Main latch is connected with the scan control buffer circuit again, from latch, with output buffer, is connected.
Main latch has seven inputs and an output, and seven inputs are D, C, CN, SE, SEN, SI, R, and an output is MO.Main latch is comprised of 18 PMOS pipes and 18 NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg4 of the 4th PMOS pipe connects SI, and drain electrode Pd4 connects the source electrode Ps5 of the 5th PMOS pipe, and source electrode Ps4 connects power vd D; The grid Pg5 of the 5th PMOS pipe connects SEN, and drain electrode Pd5 connects the source electrode Ps8 of the 8th PMOS pipe, and source electrode Ps5 connects Pd4; The grid Pg6 of the 6th PMOS pipe connects SE, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects D, and drain electrode Pd7 connects Ps8, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects C, and drain electrode Pd8 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps8 connects Pd5; The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects C, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects R, and drain electrode Pd14 connects the source electrode Ps15 of the 15 PMOS pipe, and source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects Pd8, and drain electrode Pd15 connects the drain electrode Nd14 of the 14 NMOS pipe and, as the output MO of main latch, source electrode Ps15 connects Pd14; The grid Pg16 of the 16 PMOS pipe connects R, and drain electrode Pd16 connects the source electrode Ps17 of the 17 PMOS pipe, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects Pd13, and drain electrode Pd17 connects the drain electrode Nd16 of the 16 NMOS pipe, and source electrode Ps17 connects Pd16; The grid Pg18 of the 18 PMOS pipe connects Pd17, and drain electrode Pd18 connects the source electrode Ps19 of the 19 PMOS pipe, and source electrode Ps18 connects power vd D; The grid Pg19 of the 19 PMOS pipe connects CN, and drain electrode Pd19 connects the drain electrode Nd18 of the 18 NMOS pipe, and source electrode Ps19 connects Pd18; The grid Pg20 of the 20 PMOS pipe connects Pd15, and drain electrode Pd20 connects the source electrode Ps21 of the 21 PMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects CN, and drain electrode Pd21 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps21 connects Pd20; The grid Ng4 of the 4th NMOS pipe connects CN, and drain electrode Nd4 connects Pd8, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects SE, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects SI, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects D, and drain electrode Nd7 connects Ns4, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects SEN, and drain electrode Nd8 connects Ns7, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects CN, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects Pd13, and drain electrode Nd14 connects Pd15, source electrode Ns14 ground connection VSS; The grid Ng15 of the 15 NMOS pipe connects R, and drain electrode Nd15 connects Pd15, source electrode Ns15 ground connection VSS; The grid Ng16 of the 16 NMOS pipe connects Pd8, and drain electrode Nd16 connects Pd17, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects R, and drain electrode Nd17 connects Pd17, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18 NMOS pipe connects C, and drain electrode Nd18 connects Pd19, and source electrode Ns18 connects the drain electrode Nd19 of the 19 NMOS pipe; The grid Ng19 of the 19 NMOS pipe connects Pd15, and drain electrode Nd19 connects Ns18, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects C, and drain electrode Nd20 connects Pd21, and source electrode Ns20 connects the drain electrode Nd21 of the 21 NMOS pipe; The grid Ng21 of the 21 NMOS pipe connects Pd17, and drain electrode Nd21 connects Ns20, source electrode Ns21 ground connection VSS.The 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe, the 6th NMOS pipe, the 8th NMOS pipe form the Scan Architecture in main latch.
From latch, four inputs and an output are arranged, four inputs are MO, C, CN, R, and an output is SO.From latch, 12 PMOS pipes and 12 NMOS pipes, consist of, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg22 of the 22 PMOS pipe connects MO, and drain electrode Pd22 connects the source electrode Ps23 of the 23 PMOS pipe, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects CN, and drain electrode Pd23 connects the drain electrode Nd22 of the 22 NMOS pipe, and source electrode Ps23 connects Pd22; The grid Pg24 of the 24 PMOS pipe connects MO, and drain electrode Pd24 connects the source electrode Ps25 of the 25 PMOS pipe, and source electrode Ps24 connects power vd D; The grid Pg25 of the 25 PMOS pipe connects CN, and drain electrode Pd25 connects the drain electrode Nd24 of the 24 NMOS pipe, and source electrode Ps25 connects Pd24; The grid Pg26 of the 26 PMOS pipe connects R, and drain electrode Pd26 connects the source electrode Ps27 of the 27 PMOS pipe, and source electrode Ps26 connects power vd D; The grid Pg27 of the 27 PMOS pipe connects Pd25, and drain electrode Pd27 connects the drain electrode Nd26 of the 26 NMOS pipe and, as the output SO from latch, source electrode Ps27 connects power supply Pd26; The grid Pg28 of the 28 PMOS pipe connects R, and drain electrode Pd28 connects the source electrode Ps29 of the 29 PMOS pipe, and source electrode Ps28 connects power vd D; The grid Pg29 of the 29 PMOS pipe connects Pd23, and drain electrode Pd29 connects the drain electrode Nd28 of the 28 NMOS pipe, and source electrode Ps29 connects Pd28; The grid Pg30 of the 30 PMOS pipe connects Pd29, and drain electrode Pd30 connects the source electrode Ps31 of the 31 PMOS pipe, and source electrode Ps30 connects power vd D; The grid Pg31 of the 31 PMOS pipe connects C, and drain electrode Pd31 connects the drain electrode Nd30 of the 30 NMOS pipe, and source electrode Ps31 connects Pd30; The grid Pg32 of the 32 PMOS pipe connects Pd27, and drain electrode Pd32 connects the source electrode Ps33 of the 33 PMOS pipe, and source electrode Ps32 connects power vd D; The grid Pg33 of the 33 PMOS pipe connects C, and drain electrode Pd33 connects the drain electrode Nd32 of the 32 NMOS pipe, and source electrode Ps33 connects Pd32; The grid Ng22 of the 22 NMOS pipe connects C, and drain electrode Nd22 connects Pd23, and source electrode Ns22 connects the drain electrode Nd23 of the 23 NMOS pipe; The grid Ng23 of the 23 NMOS pipe connects MO, and drain electrode Nd23 connects Ns22, source electrode Ns23 ground connection VSS; The grid Ng24 of the 24 NMOS pipe connects C, and drain electrode Nd24 connects Pd25, and source electrode Ns24 connects the drain electrode Nd25 of the 25 NMOS pipe; The grid Ng25 of the 25 NMOS pipe connects MO, and drain electrode Nd25 connects Ns24, source electrode Ns25 ground connection VSS; The grid Ng26 of the 26 NMOS pipe connects Pd23, and drain electrode Nd26 connects Pd27, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27 NMOS pipe connects R, and drain electrode Nd27 connects Pd27, source electrode Ns27 ground connection VSS; The grid Ng28 of the 28 NMOS pipe connects Pd25, and drain electrode Nd28 connects Pd29, source electrode Ns28 ground connection VSS; The grid Ng29 of the 29 NMOS pipe connects R, and drain electrode Nd29 connects Pd29, source electrode Ns29 ground connection VSS; The grid Ng30 of the 30 NMOS pipe connects CN, and drain electrode Nd30 connects Pd31, and source electrode Ns30 connects the drain electrode Nd31 of the 31 NMOS pipe; The grid Ng31 of the 31 NMOS pipe connects Pd27, and drain electrode Nd31 connects Ns30, source electrode Ns31 ground connection VSS; The grid Ng32 of the 32 NMOS pipe connects CN, and drain electrode Nd32 connects Pd33, and source electrode Ns32 connects the drain electrode Nd33 of the 33 NMOS pipe; The grid Ng33 of the 33 NMOS pipe connects Pd29, and drain electrode Nd33 connects Ns32, source electrode Ns33 ground connection VSS.
Output buffer has an input and two outputs, and an input is SO, and two outputs are QN, Q.Output buffer is comprised of three PMOS pipes and three NMOS pipes, and in output buffer, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg34 of the 34 PMOS pipe connects SO, and drain electrode Pd34 connects the drain electrode Nd34 of the 34 NMOS pipe, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects SO, and drain electrode Pd35 connects the drain electrode Nd35 of the 35 NMOS pipe and, as an output QN of output buffer, source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects Pd34, and drain electrode Pd36 connects the drain electrode Nd36 of the 36 NMOS pipe and, as an output Q of output buffer, source electrode Ps36 connects power vd D; The grid Ng34 of the 34 NMOS pipe connects SO, and drain electrode Nd34 connects Pd34, source electrode Ns34 ground connection VSS; The grid Ng35 of the 35 NMOS pipe connects SO, and drain electrode Nd35 connects Pd35, source electrode Ns35 ground connection VSS; The grid Ng36 of the 36 NMOS pipe connects Pd34, and drain electrode Nd36 connects Pd36, source electrode Ns36 ground connection VSS.
The reducible Scan Architecture d type flip flop of the anti-single particle overturn of the present invention course of work is as follows:
The reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention also can enter reset mode the time marquis in scanning mode, and scanning mode and reset mode can exist simultaneously.The reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention can be resetted at any time, and reset function is that the asserts signal input is controlled by RN.
When RN is that low level, SE are while being any level, the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention all enters reset mode, be main latch and from latch all by latching logic " 0 " by force, output Q and the QN of output buffer are respectively low level and high level;
When RN is that high level, SE are while being low level, the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention is in normal operating conditions, be that the clock circuit receives CK, after CK is cushioned, produce respectively the CN anti-phase with CK and with the C of CK homophase, and CN with C is passed to main latch and from latch.At CK, be between low period, CN is that high level, C are low level, and main latch is opened, and receives D and it is carried out to the MO of output and D homophase after buffered,, do not receive the MO of main latch output but preserve the MO that a CK trailing edge samples in preservation state from latch; At CK, be between high period, CN is that low level, C are high level, and main latch is in preservation state, preserves the MO of D that previous CK rising edge samples output and D homophase, open and receive the output MO of main latch from latch, MO is carried out to the SO of buffered output and MO homophase.Output buffer all will receive the output SO from latch at any time, to SO buffering output and the anti-phase QN of SO and with the Q of SO homophase.
When RN is that high level, SE are while being high level, the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention is in scanning mode, be that the clock circuit receives CK, after CK is cushioned, produce respectively the CN anti-phase with CK and with the C of CK homophase, and CN with C is passed to main latch and from latch.At CK, be between low period, CN is that high level, C are low level, and main latch is opened, and receives SI and it is carried out to the MO of output and SI homophase after buffered,, do not receive the MO of main latch output but preserve the MO that a CK trailing edge samples in preservation state from latch; At CK, be between high period, CN is that low level, C are high level, and main latch is in preservation state, preserves the MO of SI that previous CK rising edge samples output and SI homophase, open and receive the output MO of main latch from latch, MO is carried out to the SO of buffered output and MO homophase.Output buffer all will receive the output SO from latch at any time, to SO buffering output and the anti-phase QN of SO and with the Q of SO homophase.
Adopt the present invention can reach following technique effect:
The anti-single particle overturn ability of the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention is better than the unguyed reducible Scan Architecture d type flip flop of tradition, reducible Scan Architecture d type flip flop is reinforced in time sampling and traditional redundancy is reinforced reducible Scan Architecture d type flip flop.Because the present invention is transformed the unguyed reducible Scan Architecture d type flip flop structure of tradition, all carried out the duplication redundancy reinforcing to main latch with from latch, and for main latch and from latch C 2the MOS circuit structure improves, and separates the C of redundancy each other 2pull-up circuit in the MOS circuit and pull-down circuit, further improved the anti-single particle overturn ability of the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention.The reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention is suitable for the standard cell lib that anti-single particle overturn is reinforced integrated circuit, is applied to the fields such as Aeronautics and Astronautics.
The accompanying drawing explanation
Fig. 1 is the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention logical construction schematic diagram.
Fig. 2 is clock circuit structural representation in the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Fig. 3 is scan control buffer circuit structural representation in the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Fig. 4 is the buffer circuit structural representation that resets in the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Fig. 5 is main latch structural representation in the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Fig. 6 is from the latch structure schematic diagram in the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Fig. 7 is output buffer structural representation in the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention.
Embodiment
Fig. 1 is the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention logical construction schematic diagram.The present invention is by clock circuit (as shown in Figure 2), scan control buffer circuit (as shown in Figure 3), the buffer circuit that resets (as shown in Figure 4), main latch (as shown in Figure 5), form from latch (as shown in Figure 6) and output buffer (as shown in Figure 7).The present invention has five inputs and two outputs.Two inputs are respectively that CK is that clock signal input part, D are that data-signal input, SE are that scan control signal input, SI are that scan data input terminal and RN are reseting input signal; Two outputs are respectively Q and QN, Q and a pair of contrary data-signal of QN output.Clock circuit receives CK, and CK is carried out exporting respectively C and CN after buffered.The scan control buffer circuit is cushioned SE, the SEN that input is anti-phase with SE, and SEN is imported in main latch.The buffer circuit that resets is cushioned RN, input and the anti-phase R of RN, and R is imported into to main latch and from latch.Main latch receives D, C, CN, SE, SEN, SI, R, main latch under the control of C, CN, SE, SE and R to D or SI latched etc. process after output MO.Receive MO, C, CN and R from latch, from latch, under the control of C, N and R, the processing such as MO is latched are exported to SO afterwards.Output buffer receives SO, and it is carried out exporting Q and QN after buffered.RN is high level, SE while being low level, and the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention is in normal operating conditions; RN is high level, SE while being high level, and the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention is in the scanning work state; When RN is low level, the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention enters reset mode.
As shown in Figure 2, clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, and first order inverter is comprised of a PMOS pipe and a NMOS pipe, and the grid Pg1 of a PMOS pipe connects CK, the drain electrode Nd1 of drain electrode Pd1 connection the one NMOS pipe, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is comprised of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, the drain electrode Nd2 of drain electrode Pd2 connection the 2nd NMOS pipe, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.
As shown in Figure 3, the scan control buffer circuit has an input and an output, and input is SE, and output is SEN.The scan control buffer circuit is comprised of the 3rd PMOS pipe and the 3rd NMOS pipe.The substrate of the 3rd PMOS pipe all is connected power vd D with source electrode Ps3, the equal ground connection VSS of the substrate of the 3rd NMOS pipe and source electrode Ns3.The grid Pg3 of the 3rd PMOS pipe connects SE, and drain electrode Pd3 connects the drain electrode Nd3 of the 3rd NMOS pipe, and as the output SEN of scan control buffer circuit; The grid Ng3 of the 3rd NMOS pipe connects SE, and drain electrode Nd3 connects Pd3.
As shown in Figure 4, the buffer circuit that resets has an input and an output, and input is RN, and output is R.The buffer circuit that resets is an one-level inverter, and wherein the grid Pg37 of the 37 PMOS pipe connects RN, and drain electrode Pd37 connects the drain electrode Nd37 of the 37 NMOS pipe also as the output R of the buffer circuit that resets, and source electrode Ps37 connects power vd D; The 37 NMOS tube grid Ng37 connects RN, and drain electrode Nd37 connects Pd37, source electrode Ns37 ground connection VSS.
As shown in Figure 5, main latch has seven inputs and an output, and seven inputs are D, C, CN, SE, SEN, SI, R, and an output is MO.Main latch is comprised of 18 PMOS pipes and 18 NMOS pipes, and in main latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg4 of the 4th PMOS pipe connects SI, and drain electrode Pd4 connects the source electrode Ps5 of the 5th PMOS pipe, and source electrode Ps4 connects power vd D; The grid Pg5 of the 5th PMOS pipe connects SEN, and drain electrode Pd5 connects the source electrode Ps8 of the 8th PMOS pipe, and source electrode Ps5 connects Pd4; The grid Pg6 of the 6th PMOS pipe connects SE, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects D, and drain electrode Pd7 connects Ps8, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects C, and drain electrode Pd8 connects the drain electrode Nd4 of the 4th NMOS pipe, and source electrode Ps8 connects Pd5; The grid Pg9 of the 9th PMOS pipe connects SI, and drain electrode Pd9 connects the source electrode Ps10 of the tenth PMOS pipe, and source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects SEN, and drain electrode Pd10 connects the source electrode Ps13 of the 13 PMOS pipe, and source electrode Ps10 connects Pd9; The grid Pg11 of the 11 PMOS pipe connects SE, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects D, and drain electrode Pd12 connects Ps13, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects C, and drain electrode Pd13 connects the drain electrode Nd9 of the 9th NMOS pipe, and source electrode Ps13 connects Pd10; The grid Pg14 of the 14 PMOS pipe connects R, and drain electrode Pd14 connects the source electrode Ps15 of the 15 PMOS pipe, and source electrode Ps14 connects power vd D; The grid Pg15 of the 15 PMOS pipe connects Pd8, and drain electrode Pd15 connects the drain electrode Nd14 of the 14 NMOS pipe and, as the output MO of main latch, source electrode Ps15 connects Pd14; The grid Pg16 of the 16 PMOS pipe connects R, and drain electrode Pd16 connects the source electrode Ps17 of the 17 PMOS pipe, and source electrode Ps16 connects power vd D; The grid Pg17 of the 17 PMOS pipe connects Pd13, and drain electrode Pd17 connects the drain electrode Nd16 of the 16 NMOS pipe, and source electrode Ps17 connects Pd16; The grid Pg18 of the 18 PMOS pipe connects Pd17, and drain electrode Pd18 connects the source electrode Ps19 of the 19 PMOS pipe, and source electrode Ps18 connects power vd D; The grid Pg19 of the 19 PMOS pipe connects CN, and drain electrode Pd19 connects the drain electrode Nd18 of the 18 NMOS pipe, and source electrode Ps19 connects Pd18; The grid Pg20 of the 20 PMOS pipe connects Pd15, and drain electrode Pd20 connects the source electrode Ps21 of the 21 PMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects CN, and drain electrode Pd21 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps21 connects Pd20; The grid Ng4 of the 4th NMOS pipe connects CN, and drain electrode Nd4 connects Pd8, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects SE, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects the drain electrode Nd6 of the 6th NMOS pipe; The grid Ng6 of the 6th NMOS pipe connects SI, and drain electrode Nd6 connects Ns5, source electrode Ns6 ground connection VSS; The grid Ng7 of the 7th NMOS pipe connects D, and drain electrode Nd7 connects Ns4, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects SEN, and drain electrode Nd8 connects Ns7, source electrode Ns8 ground connection VSS; The grid Ng9 of the 9th NMOS pipe connects CN, and drain electrode Nd9 connects Pd13, and source electrode Ns9 connects the drain electrode Nd10 of the tenth NMOS pipe; The grid Ng10 of the tenth NMOS pipe connects SE, and drain electrode Nd10 connects Ns9, and source electrode Ns10 connects the drain electrode Nd11 of the 11 NMOS pipe; The grid Ng11 of the 11 NMOS pipe connects SI, and drain electrode Nd11 connects Ns10, source electrode Ns11 ground connection VSS; The grid Ng12 of the 12 NMOS pipe connects D, and drain electrode Nd12 connects Ns9, and source electrode Ns12 connects the drain electrode Nd13 of the 13 NMOS pipe; The grid Ng13 of the 13 NMOS pipe connects SEN, and drain electrode Nd13 connects Ns12, source electrode Ns13 ground connection VSS; The grid Ng14 of the 14 NMOS pipe connects Pd13, and drain electrode Nd14 connects Pd15, source electrode Ns14 ground connection VSS; The grid Ng15 of the 15 NMOS pipe connects R, and drain electrode Nd15 connects Pd15, source electrode Ns15 ground connection VSS; The grid Ng16 of the 16 NMOS pipe connects Pd8, and drain electrode Nd16 connects Pd17, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects R, and drain electrode Nd17 connects Pd17, source electrode Ns17 ground connection VSS; The grid Ng18 of the 18 NMOS pipe connects C, and drain electrode Nd18 connects Pd19, and source electrode Ns18 connects the drain electrode Nd19 of the 19 NMOS pipe; The grid Ng19 of the 19 NMOS pipe connects Pd15, and drain electrode Nd19 connects Ns18, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects C, and drain electrode Nd20 connects Pd21, and source electrode Ns20 connects the drain electrode Nd21 of the 21 NMOS pipe; The grid Ng21 of the 21 NMOS pipe connects Pd17, and drain electrode Nd21 connects Ns20, source electrode Ns21 ground connection VSS.The 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe and the 5th NMOS pipe, the 6th NMOS pipe, the 8th NMOS pipe form the Scan Architecture in main latch.
As shown in Figure 6, from latch, four inputs and an output are arranged, four inputs are MO, C, CN, R, and an output is SO.From latch, 12 PMOS pipes and 12 NMOS pipes, consist of, from latch, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg22 of the 22 PMOS pipe connects MO, and drain electrode Pd22 connects the source electrode Ps23 of the 23 PMOS pipe, and source electrode Ps22 connects power vd D; The grid Pg23 of the 23 PMOS pipe connects CN, and drain electrode Pd23 connects the drain electrode Nd22 of the 22 NMOS pipe, and source electrode Ps23 connects Pd22; The grid Pg24 of the 24 PMOS pipe connects MO, and drain electrode Pd24 connects the source electrode Ps25 of the 25 PMOS pipe, and source electrode Ps24 connects power vd D; The grid Pg25 of the 25 PMOS pipe connects CN, and drain electrode Pd25 connects the drain electrode Nd24 of the 24 NMOS pipe, and source electrode Ps25 connects Pd24; The grid Pg26 of the 26 PMOS pipe connects R, and drain electrode Pd26 connects the source electrode Ps27 of the 27 PMOS pipe, and source electrode Ps26 connects power vd D; The grid Pg27 of the 27 PMOS pipe connects Pd25, and drain electrode Pd27 connects the drain electrode Nd26 of the 26 NMOS pipe and, as the output SO from latch, source electrode Ps27 connects power supply Pd26; The grid Pg28 of the 28 PMOS pipe connects R, and drain electrode Pd28 connects the source electrode Ps29 of the 29 PMOS pipe, and source electrode Ps28 connects power vd D; The grid Pg29 of the 29 PMOS pipe connects Pd23, and drain electrode Pd29 connects the drain electrode Nd28 of the 28 NMOS pipe, and source electrode Ps29 connects Pd28; The grid Pg30 of the 30 PMOS pipe connects Pd29, and drain electrode Pd30 connects the source electrode Ps31 of the 31 PMOS pipe, and source electrode Ps30 connects power vd D; The grid Pg31 of the 31 PMOS pipe connects C, and drain electrode Pd31 connects the drain electrode Nd30 of the 30 NMOS pipe, and source electrode Ps31 connects Pd30; The grid Pg32 of the 32 PMOS pipe connects Pd27, and drain electrode Pd32 connects the source electrode Ps33 of the 33 PMOS pipe, and source electrode Ps32 connects power vd D; The grid Pg33 of the 33 PMOS pipe connects C, and drain electrode Pd33 connects the drain electrode Nd32 of the 32 NMOS pipe, and source electrode Ps33 connects Pd32; The grid Ng22 of the 22 NMOS pipe connects C, and drain electrode Nd22 connects Pd23, and source electrode Ns22 connects the drain electrode Nd23 of the 23 NMOS pipe; The grid Ng23 of the 23 NMOS pipe connects MO, and drain electrode Nd23 connects Ns22, source electrode Ns23 ground connection VSS; The grid Ng24 of the 24 NMOS pipe connects C, and drain electrode Nd24 connects Pd25, and source electrode Ns24 connects the drain electrode Nd25 of the 25 NMOS pipe; The grid Ng25 of the 25 NMOS pipe connects MO, and drain electrode Nd25 connects Ns24, source electrode Ns25 ground connection VSS; The grid Ng26 of the 26 NMOS pipe connects Pd23, and drain electrode Nd26 connects Pd27, source electrode Ns26 ground connection VSS; The grid Ng27 of the 27 NMOS pipe connects R, and drain electrode Nd27 connects Pd27, source electrode Ns27 ground connection VSS; The grid Ng28 of the 28 NMOS pipe connects Pd25, and drain electrode Nd28 connects Pd29, source electrode Ns28 ground connection VSS; The grid Ng29 of the 29 NMOS pipe connects R, and drain electrode Nd29 connects Pd29, source electrode Ns29 ground connection VSS; The grid Ng30 of the 30 NMOS pipe connects CN, and drain electrode Nd30 connects Pd31, and source electrode Ns30 connects the drain electrode Nd31 of the 31 NMOS pipe; The grid Ng31 of the 31 NMOS pipe connects Pd27, and drain electrode Nd31 connects Ns30, source electrode Ns31 ground connection VSS; The grid Ng32 of the 32 NMOS pipe connects CN, and drain electrode Nd32 connects Pd33, and source electrode Ns32 connects the drain electrode Nd33 of the 33 NMOS pipe; The grid Ng33 of the 33 NMOS pipe connects Pd29, and drain electrode Nd33 connects Ns32, source electrode Ns33 ground connection VSS.
As shown in Figure 7, output buffer has an input and two outputs, and an input is SO, and two outputs are QN, Q.Output buffer is comprised of three PMOS pipes and three NMOS pipes, and in output buffer, the substrate of all PMOS pipes connects power vd D, the substrate ground connection VSS of all NMOS pipes.The grid Pg34 of the 34 PMOS pipe connects SO, and drain electrode Pd34 connects the drain electrode Nd34 of the 34 NMOS pipe, and source electrode Ps34 connects power vd D; The grid Pg35 of the 35 PMOS pipe connects SO, and drain electrode Pd35 connects the drain electrode Nd35 of the 35 NMOS pipe and, as an output QN of output buffer, source electrode Ps35 connects power vd D; The grid Pg36 of the 36 PMOS pipe connects Pd34, and drain electrode Pd36 connects the drain electrode Nd36 of the 36 NMOS pipe and, as an output Q of output buffer, source electrode Ps36 connects power vd D; The grid Ng34 of the 34 NMOS pipe connects SO, and drain electrode Nd34 connects Pd34, source electrode Ns34 ground connection VSS; The grid Ng35 of the 35 NMOS pipe connects SO, and drain electrode Nd35 connects Pd35, source electrode Ns35 ground connection VSS; The grid Ng36 of the 36 NMOS pipe connects Pd34, and drain electrode Nd36 connects Pd36, source electrode Ns36 ground connection VSS.
The H-13 of Beijing Institute of Atomic Energy tandem accelerator can produce the LET value and be respectively 2.88MeVcm 2/ mg, 8.62MeVcm 2/ mg, 12.6MeVcm 2/ mg and 17.0MeVcm 2four kinds of ground heavy ion irradiation test environments of/mg.To reinforce reducible Scan Architecture d type flip flop, time sampling in the unguyed reducible Scan Architecture d type flip flop of the tradition of normal operating conditions, traditional redundancy reinforces reducible Scan Architecture d type flip flop and the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention and is placed in the LET value that the H-13 of Beijing Institute of Atomic Energy tandem accelerator produces and is respectively 2.88MeVcm 2/ mg, 8.62MeVcm 2/ mg, 12.6MeVcm 2/ mg and 17.0MeVcm 2in the ground heavy ion irradiation test environment of/mg, observe each d type flip flop whether single-particle inversion occurs, obtain the minimum LET Value Data that each d type flip flop generation single-particle inversion needs.The unguyed reducible Scan Architecture d type flip flop of tradition, the traditional redundancy that table 1 obtains for the ground heavy particle irradiation test of using the H-13 of Beijing Institute of Atomic Energy tandem accelerator and carrying out reinforced reducible Scan Architecture d type flip flop, time sampling and reinforced the minimum LET Value Data that reducible Scan Architecture d type flip flop and the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention generation single-particle inversion need.The unguyed reducible Scan Architecture d type flip flop of tradition is 2.88MeVcm in the LET value 2/ mg, 8.62MeVcm 2/ mg, 12.6MeVcm 2/ mg and 17.0MeVcm 2single-particle inversion all occurs in the ground heavy ion irradiation test environment of/mg while working, it is 12.6MeVcm in the LET value that traditional redundancy is reinforced reducible Scan Architecture d type flip flop 2/ mg and 17.0MeVcm 2single-particle inversion occurs in the ground heavy ion irradiation test environment of/mg while working, it is 8.62MeVcm in the LET value that reducible Scan Architecture d type flip flop is reinforced in time sampling 2/ mg, 12.6MeVcm 2/ mg and 17.0MeVcm 2single-particle inversion occurs while working in the ground heavy ion irradiation test environment of/mg, and the reducible Scan Architecture d type flip flop of anti-single particle overturn of the present invention is only 17.0MeVcm in the LET value 2single-particle inversion occurs in the ground heavy ion irradiation test environment of/mg while working.From then on table can be found out, the minimum LET value that generation single-particle inversion of the present invention needs improves 343% than the unguyed reducible Scan Architecture d type flip flop of tradition, reinforce reducible Scan Architecture d type flip flop than traditional redundancy and improve 35%, reinforce reducible Scan Architecture d type flip flop than time sampling and improve 97%, therefore anti-single particle overturn ability of the present invention is better than the unguyed reducible Scan Architecture d type flip flop of tradition, reducible Scan Architecture d type flip flop is reinforced in time sampling and traditional redundancy is reinforced reducible Scan Architecture d type flip flop, be suitable for anti-single particle overturn and reinforce the standard cell lib of integrated circuit, be applied to aviation, the fields such as space flight.
Table 1
Figure GDA00002110657000201

Claims (1)

1.一种抗单粒子翻转可复位的扫描结构D触发器，抗单粒子翻转可复位的扫描结构D触发器由时钟电路、扫描控制缓冲电路、复位缓冲电路、主锁存器、从锁存器、输出缓冲电路组成，有五个输入端和两个输出端，五个输入端分别是CK即时钟信号输入端、D即数据信号输入端、SE即扫描控制信号输入端、SI即扫描数据输入端和RN即复位输入信号；两个输出端分别是Q和QN，Q和QN输出一对相反的数据信号；时钟电路有一个输入端和两个输出端，输入端为CK，输出端为C、CN；时钟电路为一个两级反相器，由第一级反相器和第二级反相器组成；第一级反相器由第一PMOS管和第一NMOS管组成，第一PMOS管的栅极Pg1连接CK，漏极Pd1连接第一NMOS管的漏极Nd1，并作为时钟电路的一个输出端CN；第一NMOS管的栅极Ng1连接CK，漏极Nd1连接Pd1；第二级反相器由第二PMOS管和第二NMOS管组成，第二PMOS管的栅极Pg2连接CN，漏极Pd2连接第二NMOS管的漏极Nd2，并作为时钟电路的另一个输出端C；第二NMOS管的栅极Ng2连接CN，漏极Nd2连接Pd2；第一PMOS管和第二PMOS管的衬底连接电源VDD，源极Ps1、Ps2连接电源VDD；第一NMOS管和第二NMOS管的衬底接地VSS，源极Ns1、Ns2也接地VSS；扫描控制缓冲电路有一个输入端和一个输出端，输入端为SE，输出端为SEN；扫描控制缓冲电路由第三PMOS管和第三NMOS管组成；第三PMOS管的衬底和源极Ps3均连接电源VDD，第三NMOS管的衬底和源极Ns3均接地VSS；第三PMOS管的栅极Pg3连接SE，漏极Pd3连接第三NMOS管的漏极Nd3，并作为扫描控制缓冲电路的输出端SEN；第三NMOS管的栅极Ng3连接SE，漏极Nd3连接Pd3；复位缓冲电路有一个输入端和一个输出端，输入端为RN，输出端为R；复位缓冲电路为一个一级反相器，其中第三十七PMOS管的栅极Pg37连接RN，漏极Pd37连接第三十七NMOS管的漏极Nd37并作为复位缓冲电路的输出R，源极Ps37连接电源VDD；第三十七NMOS管栅极Ng37连接RN，漏极Nd37连接Pd37，源极Ns37接地VSS；输出缓冲电路有一个输入端和两个输出端，一个输入端为SO，两个输出端为QN、Q；输出缓冲电路由三个PMOS管和三个NMOS管组成，输出缓冲电路中所有PMOS管的衬底连接电源VDD，所有NMOS管的衬底接地VSS；第三十四PMOS管的栅极Pg34连接SO，漏极Pd34连接第三十四NMOS管的漏极Nd34，源极Ps34连接电源VDD；第三十五PMOS管的栅极Pg35连接SO，漏极Pd35连接第三十五NMOS管的漏极Nd35并作为输出缓冲电路的一个输出QN，源极Ps35连接电源VDD；第三十六PMOS管的栅极Pg36连接Pd34，漏极Pd36连接第三十六NMOS管的漏极Nd36并作为输出缓冲电路的一个输出Q，源极Ps36连接电源VDD；第三十四NMOS管的栅极Ng34连接SO，漏极Nd34连接Pd34，源极Ns34接地VSS；第三十五NMOS管的栅极Ng35连接SO，漏极Nd35连接Pd35，源极Ns35接地VSS；第三十六NMOS管的栅极Ng36连接Pd34，漏极Nd36连接Pd36，源极Ns36接地VSS；主锁存器和从锁存器均为冗余加固的锁存器，且主锁存器中还包括扫描结构，主锁存器和从锁存器前后串联，并均与时钟电路和复位缓冲电路连接，主锁存器又与扫描控制缓冲电路连接，从锁存器与输出缓冲电路连接；其特征在于主锁存器有七个输入端和一个输出端，七个输入端为D、C、CN、SE、SEN、SI、R，一个输出端为MO；主锁存器由十八个PMOS管和十八个NMOS管组成，主锁存器中所有PMOS管的衬底连接电源VDD，所有NMOS管的衬底接地VSS；第四PMOS管的栅极Pg4连接SI，漏极Pd4连接第五PMOS管的源极Ps5，源极Ps4连接电源VDD；第五PMOS管的栅极Pg5连接SEN，漏极Pd5连接第八PMOS管的源极Ps8，源极Ps5连接Pd4；第六PMOS管的栅极Pg6连接SE，漏极Pd6连接第七PMOS管的源极Ps7，源极Ps6连接电源VDD；第七PMOS管的栅极Pg7连接D，漏极Pd7连接Ps8，源极Ps7连接Pd6；第八PMOS管的栅极Pg8连接C，漏极Pd8连接第四NMOS管的漏极Nd4，源极Ps8连接Pd5；第九PMOS管的栅极Pg9连接SI，漏极Pd9连接第十PMOS管的源极Ps10，源极Ps9连接电源VDD；第十PMOS管的栅极Pg10连接SEN，漏极Pd10连接第十三PMOS管的源极Ps13，源极Ps10连接Pd9；第十一PMOS管的栅极Pg11连接SE，漏极Pd11连接第十二PMOS管的源极Ps12，源极Ps11连接电源VDD；第十二PMOS管的栅极Pg12连接D，漏极Pd12连接Ps13，源极Ps12连接Pd11；第十三PMOS管的栅极Pg13连接C，漏极Pd13连接第九NMOS管的漏极Nd9，源极Ps13连接Pd10；第十四PMOS管的栅极Pg14连接R，漏极Pd14连接第十五PMOS管的源极Ps15，源极Ps14连接电源VDD；第十五PMOS管的栅极Pg15连接Pd8，漏极Pd15连接第十四NMOS管的漏极Nd14并作为主锁存器的输出MO，源极Ps15连接Pd14；第十六PMOS管的栅极Pg16连接R，漏极Pd16连接第十七PMOS管的源极Ps17，源极Ps16连接电源VDD；第十七PMOS管的栅极Pg17连接Pd13，漏极Pd17连接第十六NMOS管的漏极Nd16，源极Ps17连接Pd16；第十八PMOS管的栅极Pg18连接Pd17，漏极Pd18连接第十九PMOS管的源极Ps19，源极Ps18连接电源VDD；第十九PMOS管的栅极Pg19连接CN，漏极Pd19连接第十八NMOS管的漏极Nd18，源极Ps19连接Pd18；第二十PMOS管的栅极Pg20连接Pd15，漏极Pd20连接第二十一PMOS管的源极Ps21，源极Ps20连接电源VDD；第二十一PMOS管的栅极Pg21连接CN，漏极Pd21连接第二十NMOS管的漏极Nd20，源极Ps21连接Pd20；第四NMOS管的栅极Ng4连接CN，漏极Nd4连接Pd8，源极Ns4连接第五NMOS管的漏极Nd5；第五NMOS管的栅极Ng5连接SE，漏极Nd5连接Ns4，源极Ns5连接第六NMOS管的漏极Nd6；第六NMOS管的栅极Ng6连接SI，漏极Nd6连接Ns5，源极Ns6接地VSS；第七NMOS管的栅极Ng7连接D，漏极Nd7连接Ns4，源极Ns7连接第八NMOS管的漏极Nd8；第八NMOS管的栅极Ng8连接SEN，漏极Nd8连接Ns7，源极Ns8接地VSS；第九NMOS管的栅极Ng9连接CN，漏极Nd9连接Pd13，源极Ns9连接第十NMOS管的漏极Nd10；第十NMOS管的栅极Ng10连接SE，漏极Nd10连接Ns9，源极Ns10连接第十一NMOS管的漏极Nd11；第十一NMOS管的栅极Ng11连接SI，漏极Nd11连接Ns10，源极Ns11接地VSS；第十二NMOS管的栅极Ng12连接D，漏极Nd12连接Ns9，源极Ns12连接第十三NMOS管的漏极Nd13；第十三NMOS管的栅极Ng13连接SEN，漏极Nd13连接Ns12，源极Ns13接地VSS；第十四NMOS管的栅极Ng14连接Pd13，漏极Nd14连接Pd15，源极Ns14接地VSS；第十五NMOS管的栅极Ng15连接R，漏极Nd15连接Pd15，源极Ns15接地VSS；第十六NMOS管的栅极Ng16连接Pd8，漏极Nd16连接Pd17，源极Ns16接地VSS；第十七NMOS管的栅极Ng17连接R，漏极Nd17连接Pd17，源极Ns17接地VSS；第十八NMOS管的栅极Ng18连接C，漏极Nd18连接Pd19，源极Ns18连接第十九NMOS管的漏极Nd19；第十九NMOS管的栅极Ng19连接Pd15，漏极Nd19连接Ns18，源极Ns19接地VSS；第二十NMOS管的栅极Ng20连接C，漏极Nd20连接Pd21，源极Ns20连接第二十一NMOS管的漏极Nd21；第二十一NMOS管的栅极Ng21连接Pd17，漏极Nd21连接Ns20，源极Ns21接地VSS；第四PMOS管、第五PMOS管、第六PMOS管以及第五NMOS管、第六NMOS管、第八NMOS管组成主锁存器中的扫描结构；从锁存器有四个输入端和一个输出端，四个输入端为MO、C、CN、R，一个输出端为SO；从锁存器由十二个PMOS管和十二个NMOS管组成，从锁存器中所有PMOS管的衬底连接电源VDD，所有NMOS管的衬底接地VSS；第二十二PMOS管的栅极Pg22连接MO，漏极Pd22连接第二十三PMOS管的源极Ps23，源极Ps22连接电源VDD；第二十三PMOS管的栅极Pg23连接CN，漏极Pd23连接第二十二NMOS管的漏极Nd22，源极Ps23连接Pd22；第二十四PMOS管的栅极Pg24连接MO，漏极Pd24连接第二十五PMOS管的源极Ps25，源极Ps24连接电源VDD；第二十五PMOS管的栅极Pg25连接CN，漏极Pd25连接第二十四NMOS管的漏极Nd24，源极Ps25连接Pd24；第二十六PMOS管的栅极Pg26连接R，漏极Pd26连接第二十七PMOS管的源极Ps27，源极Ps26连接电源VDD；第二十七PMOS管的栅极Pg27连接Pd25，漏极Pd27连接第二十六NMOS管的漏极Nd26并作为从锁存器的输出端SO，源极Ps27连接电源Pd26；第二十八PMOS管的栅极Pg28连接R，漏极Pd28连接第二十九PMOS管的源极Ps29，源极Ps28连接电源VDD；第二十九PMOS管的栅极Pg29连接Pd23，漏极Pd29连接第二十八NMOS管的漏极Nd28，源极Ps29连接Pd28；第三十PMOS管的栅极Pg30连接Pd29，漏极Pd30连接第三十一PMOS管的源极Ps31，源极Ps30连接电源VDD；第三十一PMOS管的栅极Pg31连接C，漏极Pd31连接第三十NMOS管的漏极Nd30，源极Ps31连接Pd30；第三十二PMOS管的栅极Pg32连接Pd27，漏极Pd32连接第三十三PMOS管的源极Ps33，源极Ps32连接电源VDD；第三十三PMOS管的栅极Pg33连接C，漏极Pd33连接第三十二NMOS管的漏极Nd32，源极Ps33连接Pd32；第二十二NMOS管的栅极Ng22连接C，漏极Nd22连接Pd23，源极Ns22连接第二十三NMOS管的漏极Nd23；第二十三NMOS管的栅极Ng23连接MO，漏极Nd23连接Ns22，源极Ns23接地VSS；第二十四NMOS管的栅极Ng24连接C，漏极Nd24连接Pd25，源极Ns24连接第二十五NMOS管的漏极Nd25；第二十五NMOS管的栅极Ng25连接MO，漏极Nd25连接Ns24，源极Ns25接地VSS；第二十六NMOS管的栅极Ng26连接Pd23，漏极Nd26连接Pd27，源极Ns26接地VSS；第二十七NMOS管的栅极Ng27连接R，漏极Nd27连接Pd27，源极Ns27接地VSS；第二十八NMOS管的栅极Ng28连接Pd25，漏极Nd28连接Pd29，源极Ns28接地VSS；第二十九NMOS管的栅极Ng29连接R，漏极Nd29连接Pd29，源极Ns29接地VSS；第三十NMOS管的栅极Ng30连接CN，漏极Nd30连接Pd31，源极Ns30连接第三十一NMOS管的漏极Nd31；第三十一NMOS管的栅极Ng31连接Pd27，漏极Nd31连接Ns30，源极Ns31接地VSS；第三十二NMOS管的栅极Ng32连接CN，漏极Nd32连接Pd33，源极Ns32连接第三十三NMOS管的漏极Nd33；第三十三NMOS管的栅极Ng33连接Pd29，漏极Nd33连接Ns32，源极Ns33接地VSS。1. A resettable scanning structure D flip-flop against single event reversal, the resettable scanning structure D flip-flop of anti-single event reversal consists of a clock circuit, a scan control buffer circuit, a reset buffer circuit, a master latch, and a slave latch There are five input terminals and two output terminals. The five input terminals are CK, the clock signal input, D, the data signal input, SE, the scan control signal input, and SI, the scan data. The input terminal and RN are reset input signals; the two output terminals are Q and QN respectively, Q and QN output a pair of opposite data signals; the clock circuit has one input terminal and two output terminals, the input terminal is CK, and the output terminal is C, CN; the clock circuit is a two-stage inverter, which is composed of a first-stage inverter and a second-stage inverter; the first-stage inverter is composed of a first PMOS transistor and a first NMOS transistor, and the first The gate Pg1 of the PMOS transistor is connected to CK, the drain Pd1 is connected to the drain Nd1 of the first NMOS transistor, and serves as an output terminal CN of the clock circuit; the gate Ng1 of the first NMOS transistor is connected to CK, and the drain Nd1 is connected to Pd1; The secondary inverter is composed of a second PMOS transistor and a second NMOS transistor, the gate Pg2 of the second PMOS transistor is connected to CN, and the drain Pd2 is connected to the drain Nd2 of the second NMOS transistor, and is used as another output terminal of the clock circuit C; the gate Ng2 of the second NMOS transistor is connected to CN, and the drain Nd2 is connected to Pd2; the substrates of the first PMOS transistor and the second PMOS transistor are connected to the power supply VDD, and the sources Ps1 and Ps2 are connected to the power supply VDD; the first NMOS transistor and the second PMOS transistor are connected to the power supply VDD; The substrate of the two NMOS tubes is grounded to VSS, and the source electrodes Ns1 and Ns2 are also grounded to VSS; the scan control buffer circuit has an input terminal and an output terminal, the input terminal is SE, and the output terminal is SEN; the scan control buffer circuit is composed of the third PMOS tube and the third NMOS transistor; the substrate and source Ps3 of the third PMOS transistor are both connected to the power supply VDD, and the substrate and source Ns3 of the third NMOS transistor are both grounded to VSS; the gate Pg3 of the third PMOS transistor is connected to SE, and the drain The pole Pd3 is connected to the drain Nd3 of the third NMOS transistor, and is used as the output terminal SEN of the scan control buffer circuit; the gate Ng3 of the third NMOS transistor is connected to SE, and the drain Nd3 is connected to Pd3; the reset buffer circuit has an input terminal and an output terminal terminal, the input terminal is RN, and the output terminal is R; the reset buffer circuit is a first-stage inverter, wherein the gate Pg37 of the thirty-seventh PMOS transistor is connected to RN, and the drain Pd37 is connected to the drain of the thirty-seventh NMOS transistor Nd37 is also used as the output R of the reset buffer circuit, the source Ps37 is connected to the power supply VDD; the gate Ng37 of the thirty-seventh NMOS transistor is connected to RN, the drain Nd37 is connected to Pd37, and the source Ns37 is grounded to VSS; the output buffer circuit has an input terminal and two One output terminal is SO, and two output terminals are QN and Q; the output buffer circuit is composed of three PMOS transistors and three NMOS transistors, and the substrate connection circuits of all PMOS transistors in the output buffer circuit The source VDD, the substrates of all NMOS transistors are grounded VSS; the gate Pg34 of the thirty-fourth PMOS transistor is connected to SO, the drain Pd34 is connected to the drain Nd34 of the thirty-fourth NMOS transistor, and the source Ps34 is connected to the power supply VDD; The gate Pg35 of the fifth PMOS transistor is connected to SO, the drain Pd35 is connected to the drain Nd35 of the thirty-fifth NMOS transistor as an output QN of the output buffer circuit, and the source Ps35 is connected to the power supply VDD; the gate of the thirty-sixth PMOS transistor Pg36 is connected to Pd34, the drain Pd36 is connected to the drain Nd36 of the thirty-sixth NMOS transistor and used as an output Q of the output buffer circuit, the source Ps36 is connected to the power supply VDD; the gate Ng34 of the thirty-fourth NMOS transistor is connected to SO, and the drain Nd34 is connected to Pd34, the source Ns34 is grounded to VSS; the gate Ng35 of the thirty-fifth NMOS transistor is connected to SO, the drain Nd35 is connected to Pd35, the source Ns35 is grounded to VSS; the gate Ng36 of the thirty-sixth NMOS transistor is connected to Pd34, and the drain Nd36 is connected to Pd36, and the source Ns36 is grounded to VSS; both the master latch and the slave latch are redundancy-hardened latches, and the master latch also includes a scanning structure, the front and rear of the master latch and the slave latch connected in series, and connected with the clock circuit and the reset buffer circuit, the master latch is connected with the scan control buffer circuit, and the slave latch is connected with the output buffer circuit; it is characterized in that the master latch has seven input terminals and one output The seven input terminals are D, C, CN, SE, SEN, SI, R, and one output terminal is MO; the main latch is composed of eighteen PMOS transistors and eighteen NMOS transistors. The substrates of all PMOS transistors are connected to the power supply VDD, and the substrates of all NMOS transistors are grounded to VSS; the gate Pg4 of the fourth PMOS transistor is connected to SI, the drain Pd4 is connected to the source Ps5 of the fifth PMOS transistor, and the source Ps4 is connected to the power supply VDD; The gate Pg5 of the fifth PMOS transistor is connected to SEN, the drain Pd5 is connected to the source Ps8 of the eighth PMOS transistor, and the source Ps5 is connected to Pd4; the gate Pg6 of the sixth PMOS transistor is connected to SE, and the drain Pd6 is connected to the seventh PMOS transistor. The source Ps7 and the source Ps6 are connected to the power supply VDD; the gate Pg7 of the seventh PMOS transistor is connected to D, the drain Pd7 is connected to Ps8, and the source Ps7 is connected to Pd6; the gate Pg8 of the eighth PMOS transistor is connected to C, and the drain Pd8 is connected to the The drain Nd4 of the four NMOS transistors, the source Ps8 are connected to Pd5; the gate Pg9 of the ninth PMOS transistor is connected to SI, the drain Pd9 is connected to the source Ps10 of the tenth PMOS transistor, and the source Ps9 is connected to the power supply VDD; the tenth PMOS transistor The gate Pg10 is connected to SEN, the drain Pd10 is connected to the source Ps13 of the thirteenth PMOS transistor, and the source Ps10 is connected to Pd9; the gate Pg11 of the eleventh PMOS transistor is connected to SE, and the drain Pd11 is connected to the source of the twelfth PMOS transistor Ps12, the source Ps11 is connected to the power supply VDD; The gate Pg12 of the twelfth PMOS transistor is connected to D, the drain Pd12 is connected to Ps13, the source Ps12 is connected to Pd11; the gate Pg13 of the thirteenth PMOS transistor is connected to C, the drain Pd13 is connected to the drain Nd9 of the ninth NMOS transistor, and the source The pole Ps13 is connected to Pd10; the gate Pg14 of the fourteenth PMOS transistor is connected to R, the drain Pd14 is connected to the source Ps15 of the fifteenth PMOS transistor, and the source Ps14 is connected to the power supply VDD; the gate Pg15 of the fifteenth PMOS transistor is connected to Pd8, The drain Pd15 is connected to the drain Nd14 of the fourteenth NMOS transistor as the output MO of the main latch, the source Ps15 is connected to Pd14; the gate Pg16 of the sixteenth PMOS transistor is connected to R, and the drain Pd16 is connected to the seventeenth PMOS transistor The source Ps17 of the source Ps16 is connected to the power supply VDD; the gate Pg17 of the seventeenth PMOS transistor is connected to Pd13, the drain Pd17 is connected to the drain Nd16 of the sixteenth NMOS transistor, and the source Ps17 is connected to Pd16; the eighteenth PMOS transistor The gate Pg18 is connected to Pd17, the drain Pd18 is connected to the source Ps19 of the nineteenth PMOS transistor, and the source Ps18 is connected to the power supply VDD; the gate Pg19 of the nineteenth PMOS transistor is connected to CN, and the drain Pd19 is connected to the drain of the eighteenth NMOS transistor. Pole Nd18, source Ps19 connected to Pd18; gate Pg20 of the twentieth PMOS tube connected to Pd15, drain Pd20 connected to source Ps21 of the twenty-first PMOS tube, source Ps20 connected to power supply VDD; The gate Pg21 is connected to CN, the drain Pd21 is connected to the drain Nd20 of the twentieth NMOS transistor, the source Ps21 is connected to Pd20; the gate Ng4 of the fourth NMOS transistor is connected to CN, the drain Nd4 is connected to Pd8, and the source Ns4 is connected to the fifth NMOS The drain Nd5 of the transistor; the gate Ng5 of the fifth NMOS transistor is connected to SE, the drain Nd5 is connected to Ns4, and the source Ns5 is connected to the drain Nd6 of the sixth NMOS transistor; the gate Ng6 of the sixth NMOS transistor is connected to SI, and the drain Nd6 Connect Ns5, the source Ns6 is grounded to VSS; the gate Ng7 of the seventh NMOS transistor is connected to D, the drain Nd7 is connected to Ns4, the source Ns7 is connected to the drain Nd8 of the eighth NMOS transistor; the gate Ng8 of the eighth NMOS transistor is connected to SEN, The drain Nd8 is connected to Ns7, the source Ns8 is grounded to VSS; the gate Ng9 of the ninth NMOS transistor is connected to CN, the drain Nd9 is connected to Pd13, and the source Ns9 is connected to the drain Nd10 of the tenth NMOS transistor; the gate Ng10 of the tenth NMOS transistor Connect to SE, drain Nd10 to Ns9, source Ns10 to drain Nd11 of the eleventh NMOS transistor; gate Ng11 of the eleventh NMOS transistor to SI, drain Nd11 to Ns10, source Ns11 to ground VSS; twelfth The gate Ng12 of the NMOS transistor is connected to D, the drain Nd12 is connected to Ns9, and the source Ns12 is connected to the The drain Nd13 of the thirteenth NMOS transistor; the gate Ng13 of the thirteenth NMOS transistor is connected to SEN, the drain Nd13 is connected to Ns12, and the source Ns13 is grounded to VSS; the gate Ng14 of the fourteenth NMOS transistor is connected to Pd13, and the drain Nd14 is connected to Pd15 , the source Ns14 is grounded to VSS; the gate Ng15 of the fifteenth NMOS transistor is connected to R, the drain Nd15 is connected to Pd15, the source Ns15 is grounded to VSS; the gate Ng16 of the sixteenth NMOS transistor is connected to Pd8, the drain Nd16 is connected to Pd17, and the source The pole Ns16 is grounded to VSS; the gate Ng17 of the seventeenth NMOS transistor is connected to R, the drain Nd17 is connected to Pd17, and the source Ns17 is grounded to VSS; the gate Ng18 of the eighteenth NMOS transistor is connected to C, the drain Nd18 is connected to Pd19, and the source Ns18 Connect the drain Nd19 of the nineteenth NMOS transistor; the gate Ng19 of the nineteenth NMOS transistor is connected to Pd15, the drain Nd19 is connected to Ns18, the source Ns19 is grounded to VSS; the gate Ng20 of the twentieth NMOS transistor is connected to C, and the drain Nd20 Connect Pd21, the source Ns20 is connected to the drain Nd21 of the twenty-first NMOS transistor; the gate Ng21 of the twenty-first NMOS transistor is connected to Pd17, the drain Nd21 is connected to Ns20, and the source Ns21 is grounded to VSS; the fourth PMOS transistor, the fifth The PMOS transistor, the sixth PMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, and the eighth NMOS transistor form the scanning structure in the master latch; the slave latch has four input terminals and one output terminal, and the four input terminals are MO, C, CN, R, and one output terminal is SO; the slave latch is composed of twelve PMOS transistors and twelve NMOS transistors, and the substrate of all PMOS transistors in the slave latch is connected to the power supply VDD, and all NMOS transistors The substrate of the tube is grounded VSS; the gate Pg22 of the twenty-second PMOS tube is connected to MO, the drain Pd22 is connected to the source Ps23 of the twenty-third PMOS tube, and the source Ps22 is connected to the power supply VDD; the gate of the twenty-third PMOS tube The pole Pg23 is connected to CN, the drain Pd23 is connected to the drain Nd22 of the twenty-second NMOS transistor, the source Ps23 is connected to Pd22; the gate Pg24 of the twenty-fourth PMOS transistor is connected to MO, and the drain Pd24 is connected to the drain of the twenty-fifth PMOS transistor. The source Ps25 and the source Ps24 are connected to the power supply VDD; the gate Pg25 of the twenty-fifth PMOS transistor is connected to CN, the drain Pd25 is connected to the drain Nd24 of the twenty-fourth NMOS transistor, and the source Ps25 is connected to Pd24; the twenty-sixth PMOS The gate Pg26 of the tube is connected to R, the drain Pd26 is connected to the source Ps27 of the twenty-seventh PMOS tube, and the source Ps26 is connected to the power supply VDD; the gate Pg27 of the twenty-seventh PMOS tube is connected to Pd25, and the drain Pd27 is connected to the twenty-seventh PMOS tube. The drain Nd26 of the six NMOS transistors is used as the output terminal SO of the slave latch, and the source Ps27 is connected to the power supply Pd26; the twenty-eighth PMOS transistor The gate Pg28 is connected to R, the drain Pd28 is connected to the source Ps29 of the twenty-ninth PMOS transistor, and the source Ps28 is connected to the power supply VDD; the gate Pg29 of the twenty-ninth PMOS transistor is connected to Pd23, and the drain Pd29 is connected to the twenty-eighth NMOS The drain Nd28 of the tube, the source Ps29 are connected to Pd28; the grid Pg30 of the thirtieth PMOS tube is connected to Pd29, the drain Pd30 is connected to the source Ps31 of the thirty-first PMOS tube, and the source Ps30 is connected to the power supply VDD; The gate Pg31 of the PMOS transistor is connected to C, the drain Pd31 is connected to the drain Nd30 of the 30th NMOS transistor, and the source Ps31 is connected to Pd30; the gate Pg32 of the thirty-second PMOS transistor is connected to Pd27, and the drain Pd32 is connected to the thirty-third NMOS transistor. The source Ps33 of the PMOS tube, the source Ps32 is connected to the power supply VDD; the gate Pg33 of the thirty-third PMOS tube is connected to C, the drain Pd33 is connected to the drain Nd32 of the thirty-second NMOS tube, and the source Ps33 is connected to Pd32; The gate Ng22 of the twelve NMOS transistor is connected to C, the drain Nd22 is connected to Pd23, the source Ns22 is connected to the drain Nd23 of the twenty-third NMOS transistor; the gate Ng23 of the twenty-third NMOS transistor is connected to MO, and the drain Nd23 is connected to Ns22 , the source Ns23 is grounded to VSS; the gate Ng24 of the twenty-fourth NMOS transistor is connected to C, the drain Nd24 is connected to Pd25, and the source Ns24 is connected to the drain Nd25 of the twenty-fifth NMOS transistor; the gate of the twenty-fifth NMOS transistor Ng25 is connected to MO, the drain Nd25 is connected to Ns24, the source Ns25 is grounded to VSS; the gate Ng26 of the twenty-sixth NMOS transistor is connected to Pd23, the drain Nd26 is connected to Pd27, and the source Ns26 is grounded to VSS; the gate of the twenty-seventh NMOS transistor Ng27 is connected to R, the drain Nd27 is connected to Pd27, the source Ns27 is grounded to VSS; the gate Ng28 of the twenty-eighth NMOS transistor is connected to Pd25, the drain Nd28 is connected to Pd29, and the source Ns28 is grounded to VSS; the gate of the twenty-ninth NMOS transistor Ng29 is connected to R, the drain Nd29 is connected to Pd29, and the source Ns29 is grounded to VSS; the gate Ng30 of the 30th NMOS transistor is connected to CN, the drain Nd30 is connected to Pd31, and the source Ns30 is connected to the drain Nd31 of the 31st NMOS transistor; The gate Ng31 of the thirty-first NMOS transistor is connected to Pd27, the drain Nd31 is connected to Ns30, the source Ns31 is grounded to VSS; the gate Ng32 of the thirty-second NMOS transistor is connected to CN, the drain Nd32 is connected to Pd33, and the source Ns32 is connected to the thirty-second The drain Nd33 of the third NMOS transistor; the gate Ng33 of the thirty-third NMOS transistor is connected to Pd29, the drain Nd33 is connected to Ns32, and the source Ns33 is grounded to VSS.
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CN104821804B (en) * 2015-05-27 2017-07-07 中国电子科技集团公司第四十七研究所 A kind of d type flip flop with clear terminal
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CN101499788A (en) * 2009-02-19 2009-08-05 上海交通大学 Single particle upset and single particle transient pulse resisiting D trigger
CN101686040A (en) * 2008-09-26 2010-03-31 辉达公司 Scannable d trigger

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CN101686040A (en) * 2008-09-26 2010-03-31 辉达公司 Scannable d trigger
CN101499788A (en) * 2009-02-19 2009-08-05 上海交通大学 Single particle upset and single particle transient pulse resisiting D trigger

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