CN102354526B

CN102354526B - CAM storage unit, word circuit and memory with interval matching function

Info

Publication number: CN102354526B
Application number: CN201110152857.1A
Authority: CN
Inventors: 张建伟; 吴国强; 吴志刚; 沙建军
Original assignee: DALIAN HENGLONG SCIENCE AND TECHNOLOGY DEVELOPMENT CO LTD
Current assignee: Xiamen EOchip Semiconductor Co Ltd
Priority date: 2011-06-08
Filing date: 2011-06-08
Publication date: 2014-03-19
Anticipated expiration: 2031-06-08
Also published as: CN102354526A

Abstract

The invention provides a CAM memory cell with an interval matching function, a CAM word circuit and a CAM memory. The CAM memory unit with the interval matching function comprises a read-write and memory unit 100, a first MOS transistor MN1, a second MOS transistor MN2, a third MOS transistor MN3, a fourth MOS transistor MN4, a fifth MOS transistor MN5 and a sixth MOS transistor MN6 which are mutually connected in series, and a seventh MOS transistor MN7 and an eighth MOS transistor MN8 which are mutually connected in series. The embodiment of the invention can effectively improve the leakage power consumption of the circuit. Meanwhile, the embodiment of the invention can effectively accelerate the writing time of the operation control word on the basis of not increasing the number of transistors, thereby greatly improving the performance of the CAM memory.

Description

CAM storage unit, word circuit and the storer with interval matching feature

Technical field

The present invention relates to ic manufacturing technology field, particularly a kind of CAM (content addressable memories) storage unit, CAM word circuit and CAM storer with interval matching feature.

Background technology

Content addressable memories (CAM) has very important application, extensive market in host node router.The CAM (referred to herein as RCAM) with interval matching feature can accelerate storage and the search efficiency of CAM greatly.

2009, the people such as J-W Zhang proposed a kind of interval match circuit fast, and speed is greatly improved.Particular content can be referring to: J.-W.Zhang, M.-Y.Yu, B.-D.Liu, et al.A High-Speed andEDP-Efficient Range-Matching Scheme for Packet Classification.IEEE Trans.Circuits Syst.II.2009,56:(9): 729-733.

As shown in Figure 1, be the structural drawing of the CAM storage unit of prior art.As shown in Figure 2, be circuit working state schematic diagram in prior art.With reference to Fig. 1, CAM storage unit is mainly comprised of a sram cell, an EQ passage and a GE passage.EQ passage is mainly used for treatment S L and D and " equates " situation, and GE passage is mainly used for treatment S L, is more than or equal to D situation.Search data SK sends into by scounting line SL, and storage data SD deposits D point by bit line BL/BL# (BL# is the logic " non-" of BL) here.OPGE is operating control signal (OPGE# is logic " non-" signal of OPGE).When OPGE=1, represent " being more than or equal to " operation, whether meet SL >=D.When OPGE=0, represent " being less than or equal to " operation, whether meet SL≤D.As seen from the figure, circuit is only comprised of 18 transistors.Sram cell is used for storing data.When word line WL is high level, data deposit D point in by bit line BL/BL#.EQ and GE passage are used for realizing interval matching feature.When SL=D, node P is high level, and transfer tube MN1 and MN2 open.Otherwise if during SL ≠ D, node P is low level, transfer tube MN1 and MN2 close, and MN3 opens.Now, if when SL > D and OPGE=1, MN4 opens.Otherwise, if SL < D and OPGE=1, or SL > D and OPGE=0, MN4 closes.Fig. 2 has provided the truth table of RMC.

The shortcoming of existing this CAM storage unit is that circuit electricity leakage power dissipation is very high.Main cause is that the P point in Fig. 1 does not reach the full voltage amplitude of oscillation, thereby causes the electricity leakage power dissipation of phase inverter INV higher.Specifically, because the high level of P electricity is that two NMOS pipes (MN5, MN6) transmit from left and right, and the transmission of NMOS pipe maximum level be V _dD-V _th, wherein.V _dDfor supply voltage, V _thfor the threshold voltage of NMOS pipe, P point voltage does not reach the full voltage amplitude of oscillation.Therefore when P point voltage is V _dD-V _thtime, the P pipe in phase inverter INV is not well closed, and N pipe is in open mode, referring to Fig. 3.Fig. 3 is phase inverter INV circuit structure diagram in prior art.Therefore, at phase inverter INV, have electric current I _sreveal I _sbe called leakage current.The leakage current of phase inverter can cause very large leakage power consumption, especially under deep submicron process, because RCAM is comprised of the RCAM unit of a large amount of repetitive structures, it has accounted for most areas of RCAM, thus the electric leakage of phase inverter INV on RCAM, overall electric leakage causes very important impact.Particularly under deep submicron process.Electricity leakage power dissipation has become a serious problem.

As shown in Figure 4, the unit module for being formed by multidigit CAM storage unit in prior art.As shown in Figure 5, the word circuit structure for being formed by multidigit CAM storage unit in prior art.As can be seen from the figure, if suppose total M bit location, the control bit OPGE of existing CAM storer has connected 2M NMOS pipe, OPGE# has also connected 2M NMOS pipe, therefore increased the write time of control bit OPGE, wherein, MSB-MostSignificant Bit is called a high position, and LSB-Least Significant Bit is called low level.In addition, for the word circuit shown in Fig. 5, it comprises 4 EQ links (EQ_chain) and 4 GE links (GE_chain), wherein each EQ link and GE link form by four CAM storage unit of mutually connecting, output module (OR5_gate) is connected with the transmission of last EQ link with 4 Ge links respectively, wherein, between EQ link, series connection mutually, parallel with one another between GE link.This word circuit also comprises the selection module of being controlled by OPEQ.From can find out among Fig. 5 be connected with OPEQ comprise 4 NMOS pipes and 4 PMOS pipes, and need to produce OPEQ# (logic NOT of OPEQ), and OPEQ# is also connected with 4 PMOS pipes, so also increased the write time of control bit OPEQ.

Summary of the invention

Object of the present invention is intended at least solve above-mentioned technological deficiency, particularly solves the TV university of current CAM memory drain, the defect that writing speed is slow.

For achieving the above object, one aspect of the present invention has proposed a kind of CAM storage unit with interval matching feature, comprise: read-write and storage unit, described read-write and storage unit are connected with word line WL and bit line BL respectively, and described read-write and storage unit have first end D and the second end D#, wherein, the second end D# is the logic NOT of described first end D; The first metal-oxide-semiconductor MN1 and the second metal-oxide-semiconductor MN2, the first end of described the first metal-oxide-semiconductor MN1 and the second metal-oxide-semiconductor MN2 is connected with the second input GE path with the first input EQ path respectively, and the second end of described the first metal-oxide-semiconductor MN1 and the second metal-oxide-semiconductor MN2 is respectively as the first output and the second output; The 5th metal-oxide-semiconductor MN5 and the 6th metal-oxide-semiconductor MN6 that mutually connect, the grid of described the 5th metal-oxide-semiconductor MN5 and the 6th metal-oxide-semiconductor MN6 is connected with the second end D# with the first end D of described read-write and storage unit respectively, and the first end of described the 5th metal-oxide-semiconductor MN5 is connected with the 3rd input SL, the first end of described the 6th metal-oxide-semiconductor MN6 is connected with the 4th input SL#, and the node between described the 5th metal-oxide-semiconductor MN5 and the 6th metal-oxide-semiconductor MN6 is all connected with the grid of the second metal-oxide-semiconductor MN2 with described the first metal-oxide-semiconductor MN1; The 7th metal-oxide-semiconductor MN7 and the 8th metal-oxide-semiconductor MN8 that mutually connect, the grid of described the 7th metal-oxide-semiconductor MN7 and the 8th metal-oxide-semiconductor MN8 is connected with first end D with the second end D# of described read-write and storage unit respectively, and the first end of described the 7th metal-oxide-semiconductor MN7 is connected with the 3rd input SL, the first end of described the 8th metal-oxide-semiconductor MN8 is connected with the 4th input SL#, wherein, described the 4th input SL# is the logic NOT of described the 3rd input SL; The 3rd metal-oxide-semiconductor MN3, the grid of described the 3rd metal-oxide-semiconductor MN3 is connected with the node between described the 7th metal-oxide-semiconductor MN7 and the 8th metal-oxide-semiconductor MN8, and the first end of described the 3rd metal-oxide-semiconductor MN3 is connected with described the second input GE path; With the 4th metal-oxide-semiconductor MN4, the grid of described the 4th metal-oxide-semiconductor MN4 is connected with described the 3rd input SL, and the first end of described the 4th metal-oxide-semiconductor MN4 is connected with the second end of described the 3rd metal-oxide-semiconductor MN3, and the second end ground connection of described the 4th metal-oxide-semiconductor MN4.

In one embodiment of the invention, described the first metal-oxide-semiconductor MN1 is NMOS pipe to described the 8th metal-oxide-semiconductor MN8.

In one embodiment of the invention, described read-write and storage unit further comprise: the first phase inverter and second phase inverter of mutual reverse parallel connection, and two nodes between described the first phase inverter and described the second phase inverter are respectively first end D and the second end D#; With the 9th metal-oxide-semiconductor MN9 and the tenth metal-oxide-semiconductor MN10, the grid of described the 9th metal-oxide-semiconductor MN9 and the tenth metal-oxide-semiconductor MN10 is connected with described word line WL respectively, and the first end of described the 9th metal-oxide-semiconductor MN9 and the tenth metal-oxide-semiconductor MN10 is connected with the second end D# with described first end D respectively, and the second end of described the 9th metal-oxide-semiconductor MN9 is connected with the first bit line BL, the second end of described the tenth metal-oxide-semiconductor MN10 is connected with the second bit line BL#.

In one embodiment of the invention, described the 9th metal-oxide-semiconductor MN9 and the tenth metal-oxide-semiconductor MN10 are NMOS pipe.

The embodiment of the present invention has also proposed a kind of CAM unit module with interval matching feature more on the one hand, comprise: M CAM storage unit as above of mutually connecting, wherein, the first output of described N-1 CAM storage unit is connected with the first input EQ path of described N CAM storage unit, and the first output ground connection of described M CAM storage unit is to form EQ link, the second output of described N-1 CAM storage unit is connected to form GE link with the second input EQ path of described N CAM storage unit, described M and N are integer, and N is less than or equal to M.

The embodiment of the present invention has also proposed a kind of word circuit with interval matching feature more on the one hand, comprising: the first precharge unit and the second precharge unit; Four groups of interconnective CAM unit modules as above, described in every group, CAM unit module comprises four CAM storage unit of series connection mutually, wherein, described in every group, CAM unit module includes a described EQ link and a described GE link; Select module for four first, described in each, the first selection module is all connected with a described EQ link, selects modules mutually to connect for described four first, and described in first, the first selection module is connected with described the first precharge unit; Select module for four second, described in each, second selects module to be all connected with a described GE link, and described in first, second selects module to be connected with described the second precharge unit, wherein, described four second controls of selecting module to be all subject to the 5th input OPEQ, and the input end of described Q the second selection module is connected with the output terminal of Q-1 the first selection module, 1 < Q≤4; Output module, the input end of described output module is connected with the output terminal of the first selection module described in last, and selects the output terminal of modules to be all connected with described four second; And logic processing module, described logic processing module is processed the Output rusults of described output module with the Output rusults of the first selection module described in last according to the 6th input OPGE.

In one embodiment of the invention, described logic processing module further comprises: the 3rd phase inverter, and the input of described the 3rd phase inverter is connected with the output of the first selection module described in last; First with non-selection device, described first is connected with described the 3rd output terminal of phase inverter and the output terminal of described output module respectively with the input end of non-selection device; The first transmission gate and the second transmission gate, the input end of described the first transmission gate is connected with the output terminal of non-selection device with described first, the input end of described the second transmission gate is connected with the output terminal of described output module, and described the first transmission gate and the second transmission gate are controlled by the 6th input OPGE; With the 4th phase inverter, the input end of described the 4th phase inverter is all connected with the output terminal of the second transmission gate with described the first transmission gate.

In one embodiment of the invention, described second selects module further to comprise: a PMOS pipe MP1, and the grid of a described PMOS pipe MP1 is connected with described the 5th input OPEQ, and the first end of a described PMOS pipe MP1 is connected with power supply; The 2nd PMOS pipe MP2 of series connection and the 11 NMOS pipe MN11, the grid of described the 2nd PMOS pipe MP2 and the 11 NMOS pipe MN11 is connected with the output terminal of described the second precharge unit or Q-1 the first selection module, and the second end of described the 11 NMOS pipe MN11 is connected with described GE link, and the first end of described the 2nd PMOS pipe MP2 is connected with the second end of a described PMOS pipe MP1; The 3rd PMOS pipe MP3 of series connection and the 12 NMOS pipe MN12, the grid of described the 3rd PMOS pipe MP3 and the 12 NMOS pipe MN12 is all connected with the output terminal of the 11 NMOS pipe MN11 with described the 2nd PMOS pipe MP2, and the second end ground connection of described the 2nd PMOS pipe MP2, and the first end of described the 3rd PMOS pipe MP3 is connected with the second end of a described PMOS pipe MP1; The 13 NMOS pipe MN13, the grid of described the 13 NMOS pipe MN13 is connected with described the 5th input OPEQ, and the second end ground connection of described the 13 NMOS pipe MN13, the first end of described the 13 NMOS pipe MN13 is connected with the output terminal of the 12 NMOS pipe MN12 with described the 3rd PMOS pipe MP3; With the 14 NMOS pipe MN14, the grid of described the 14 NMOS pipe MN14 is connected with the output terminal of the 12 NMOS pipe MN12 with described the 3rd PMOS pipe MP3, and described the 14 NMOS pipe first end of MN14 and the input end of described output circuit are connected.

The embodiment of the present invention has also proposed a kind of CAM storer with interval matching feature more on the one hand, comprising: a plurality of word circuit as above.

The embodiment of the present invention can be improved the electricity leakage power dissipation of circuit effectively.Meanwhile, the embodiment of the present invention can also effectively be speeded operations the write time of control word on the basis that does not increase transistor number, thereby can greatly improve the performance of CAM storer.

The aspect that the present invention is additional and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.

Accompanying drawing explanation

Above-mentioned and/or the additional aspect of the present invention and advantage will become from the following description of the accompanying drawings of embodiments and obviously and easily understand, wherein:

Fig. 1 is the structural drawing of the CAM storage unit of prior art;

Fig. 2 is circuit working state schematic diagram in prior art;

Fig. 3 is phase inverter INV circuit structure diagram in prior art;

Fig. 4 is the unit module consisting of multidigit CAM storage unit in prior art;

Fig. 5 is the word circuit structure consisting of multidigit CAM storage unit in prior art;

Fig. 6 is the CAM memory cell structure figure with interval matching feature of the embodiment of the present invention;

Fig. 7 is the CAM unit module structural drawing with interval matching feature of the embodiment of the present invention;

Fig. 8 is the working state figure of 3 CAM storage unit of the embodiment of the present invention;

Fig. 9 is the word circuit structure diagram with interval matching feature of the embodiment of the present invention;

Figure 10 is the work wave schematic diagram of the embodiment of the present invention;

Figure 11 is the logic processing module structural drawing of the embodiment of the present invention;

Figure 12 is the structural drawing that second of the embodiment of the present invention is selected module.

Embodiment

Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.

As shown in Figure 6, be the CAM memory cell structure figure with interval matching feature of the embodiment of the present invention.With respect to prior art, the CAM storage unit of the embodiment of the present invention has been removed phase inverter INV, supposes OPEQ=1 simultaneously.Particularly, this CAM storage unit with interval matching feature comprises read-write and storage unit 100, the first metal-oxide-semiconductor MN1, the second metal-oxide-semiconductor MN2, the 3rd metal-oxide-semiconductor MN3, the 4th metal-oxide-semiconductor MN4, the 5th metal-oxide-semiconductor MN5 of series connection mutually and the 7th metal-oxide-semiconductor MN7 and the 8th metal-oxide-semiconductor MN8 of the 6th metal-oxide-semiconductor MN6 and series connection mutually.In one embodiment of the invention, the first metal-oxide-semiconductor MN1 to the eight metal-oxide-semiconductor MN8 are NMOS pipe.Certainly the first metal-oxide-semiconductor MN1 can be partly PMOS pipe to described the 8th metal-oxide-semiconductor MN8 in other embodiments of the invention, or is all PMOS pipe.Wherein, read-write and storage unit 100 are connected with word line WL and bit line BL respectively, and described read-write and storage unit have first end D and the second end D#, and wherein, the second end D# is the logic NOT of described first end D.The first end of the first metal-oxide-semiconductor MN1 and the second metal-oxide-semiconductor MN2 is connected with the second input GE path with the first input EQ path respectively, and the second end of the first metal-oxide-semiconductor MN1 and the second metal-oxide-semiconductor MN2 is respectively as the first output and the second output.The grid of the 5th metal-oxide-semiconductor MN5 and the 6th metal-oxide-semiconductor MN6 is connected with the second end D# with the first end D of read-write and storage unit 100 respectively, and the first end of the 5th metal-oxide-semiconductor MN5 is connected with the 3rd input SL, the first end of the 6th metal-oxide-semiconductor MN6 is connected with the 4th input SL#, and the node between the 5th metal-oxide-semiconductor MN5 and metal-oxide-semiconductor MN6 is all connected with the grid of the second metal-oxide-semiconductor MN2 with the first metal-oxide-semiconductor MN1.The grid of the 7th metal-oxide-semiconductor MN7 and the 8th metal-oxide-semiconductor MN8 is connected with first end D with the second end D# of read-write and storage unit 100 respectively, and the first end of the 7th metal-oxide-semiconductor MN7 is connected with the 3rd input SL, the first end of the 8th metal-oxide-semiconductor MN8 is connected with the 4th input SL#, wherein, the 4th input SL# is the logic NOT of the 3rd input SL.The grid of the 3rd metal-oxide-semiconductor MN3 is connected with the node between the 7th metal-oxide-semiconductor MN7 and the 8th metal-oxide-semiconductor MN8, and the first end of the 3rd metal-oxide-semiconductor MN3 is connected with the second input GE path.The grid of the 4th metal-oxide-semiconductor MN4 is connected with the 3rd input SL, and the first end of the 4th metal-oxide-semiconductor MN4 is connected with the second end of the 3rd metal-oxide-semiconductor MN3, and the second end ground connection of the 4th metal-oxide-semiconductor MN4.

In one embodiment of the invention, read-write and storage unit 100 further comprise the first phase inverter and second phase inverter of mutual reverse parallel connection, the 9th metal-oxide-semiconductor MN9 and the tenth metal-oxide-semiconductor MN10.Wherein, two nodes between the first phase inverter and the second phase inverter are respectively first end D and the second end D#, the grid of the 9th metal-oxide-semiconductor MN9 and the tenth metal-oxide-semiconductor MN10 is connected with word line WL respectively, and the first end of the 9th metal-oxide-semiconductor MN9 and the tenth metal-oxide-semiconductor MN10 is connected with the second end D# with first end D respectively, and the second end of the 9th metal-oxide-semiconductor MN9 is connected with the first bit line BL, the second end of the tenth metal-oxide-semiconductor MN10 is connected with the second bit line BL#.Preferably, the 9th metal-oxide-semiconductor MN9 and the tenth metal-oxide-semiconductor MN10 are NMOS pipe.

In embodiments of the present invention, suppose OPGE=1, the operation of CAM storage unit is as follows:

1) if SL=D, the first metal-oxide-semiconductor MN1 opens, otherwise the first metal-oxide-semiconductor MN1 closes.

2), when SL > D, i.e. SL=1, during D=0, the 3rd metal-oxide-semiconductor MN3 and the 4th all conductings of metal-oxide-semiconductor MN4, the line on the second metal-oxide-semiconductor MN2 left side is pulled to 0, the remaining unchanged of the right, and the second metal-oxide-semiconductor MN2 closes.

As shown in Figure 7, be the CAM unit module structural drawing with interval matching feature of the embodiment of the present invention.For the sake of clarity, the label of element in each CAM storage unit not shown in this Figure.This CAM unit module with interval matching feature comprises: the first precharge unit 200, the second precharge unit 300, with M CAM storage unit as above of mutually connecting, wherein, the first output of N-1 CAM storage unit is connected with the first input EQ path of N CAM storage unit, and the first output ground connection of M CAM storage unit is to form EQ link, the second output of described N-1 CAM storage unit is connected to form GE link with the second input EQ path of described N CAM storage unit, wherein M and N are integer, and N is less than or equal to M.Wherein, as can be seen from Figure 7, do not need OPGE signal here, so the writing speed of OPGE can be accelerated greatly.

In one embodiment of the invention, 3 the CAM storage unit of take are described as example, suppose that input word is SK, and memory word is SD, and OPGE=1 (judge SK whether > SD).Circuit is with the work of preliminary filling-evaluation mode, and when evl_eq and evl_ge=0, the first precharge unit 200 and the second precharge unit 300 are charged to V in advance by A and B point _dD, during evaluation, according to the comparative result of SD and SK, the A point GND that discharges into good conditionsi, is shown in Fig. 8.As shown in Figure 8, be the working state figure of 3 CAM storage unit of the embodiment of the present invention.Specifically, during evaluation:

1) if SD=111, SK=111, now A point discharges into GND, B point, due to passage over the ground not, keeps original high level.

2) if SD=111, SK=101, SK < SD now, A point and B point all keep original high level.

3) if SD=101, SK=111, A point keeps original high level, B o'clock by two NMOS tube discharges of the 2nd (the 2nd CAM storage unit) to GND.

The CAM storage unit that the embodiment of the present invention is above-mentioned and CAM unit module can directly be used among word circuit as shown in Figure 5.Yet, in a preferred embodiment of the invention, a kind of word circuit with interval matching feature also having been proposed, this word circuit can reduce the load of controller OPEQ.Be illustrated in figure 9 the word circuit structure diagram with interval matching feature of the embodiment of the present invention, what be as can be seen from the figure connected with OPEQ only has 4 NMOS and 4 PMOS, therefore can reduce the load of controller OPEQ.This word circuit comprise the first precharge unit 200, the second precharge unit 300, four groups of interconnective CAM unit modules as above (M=4), four first select module 400, four second to select module 500, output module 600 and logic processing module 700.Wherein, first selects the structure of module 400 and output module 600 with existing identical, does not repeat them here.Wherein, every group of CAM unit module comprises four CAM storage unit of series connection mutually.Every group of CAM unit module includes an EQ link and a GE link, each first selection module 400 is all connected with an EQ link, wherein, select module 400 mutually to connect for four first, and first the first selection module 400 is connected with the first precharge unit 200.Each second selection module 500 is all connected with a GE link, and first the second selection module 500 is connected with the second precharge unit 300, wherein, four second controls of selecting module 500 to be all subject to the 5th input OPEQ, and the input end of Q the second selection module is connected with the output terminal of Q-1 the first selection module, 1 < Q≤4.The input end of output module 600 is connected with the output terminal of last the first selection module 400, and selects the output terminal of modules 500 to be all connected with four second.Logic processing module 700 is processed the Output rusults of output module 600 according to the Output rusults of the 6th input OPGE and last the first selection module 400.

In an embodiment of the present invention, word circuit can complete following operation: " >=", " <=", "==" three kinds of operations.Action type is determined by control word (OPEQ, POGE).The word of supposing storage is SD, and the search word of sending into is SK, and respective operations is in Table 1.

Table 1 control word (OPEQ, POGE) representative operation

(OPEQ，OPGE)	Operation	Result
			(1，x)	SK＝SD？	RW＝(SK＝＝SD？)1:0
(0，1)	SK＞＝SD？	RW＝(SK＞＝SD？)1:0
			(0，0)	SK＜＝SD？	RW＝(SK＜＝SD？)1:0

Wherein, RW=(SK==SD?) meaning that represents of 1:0 is if SK equates with SD, RW is 1, otherwise RW=0.

In one embodiment of the invention, the EQ passage of Fig. 7 (EQ chain) and GE passage (GE Chain) are separately represented.Suppose 16 of word lengths, CAM unit module is comprised of 4 CAM storage unit, and a word is comprised of 4 CAM unit modules so.Suppose that memory word is SD, the search word of input is SK, and both are 16.At this, will divide SD=SK, SD > SK, tri-kinds of its principle of work of briefing of SD < SK, oscillogram is shown in Figure 10.As shown in figure 10, be the work wave schematic diagram of the embodiment of the present invention.Here RW# is that the patrolling of RW " non-" is anti-.

1), equate operation, i.e. (OPEQ, OPGE)=(1, x).Due to OPEQ=1, GE pathway closure.The P1 that is each element circuit closes, and N1 opens.The output EQ_G3 of element circuit is high level to EQ_G0.Last RWT also rises to high level.

2), be more than or equal to operation, i.e. (OPEQ, OPGE)=(0,1).Due to OPEQ=0, now GE passage, EQ passage are all opened.Suppose SK > SD, and be greater than operation and betide [7:4] position, i.e. the 3rd CAM unit module.Now EQ_G3, EQ_G2 and GE_G1 reverse, and RWT also reverses.Due to OPGE=1, RWT sends by transmission gate TG1, last RW#=0.

3), be less than or equal to operation, i.e. (OPEQ, OPGE)=(0,1).Suppose SK < SD, and be less than operation and betide [7:4] position, now only have EQ_G3, EQ_G2 to reverse, finally RW#=1.

Above-described is the situation of OPGE=1, if OPGE=0, the result of RWT will and be sent by transmission gate TG2 after Sheffer stroke gate.For example:

(if OPEQ, OPGE)=(1,0), transmission gate TG1 closes, and TG2 opens, now RW#=! EQ_G0 (logic " non-").

(if OPEQ, OPGE)=(0,0), transmission gate TG1 closes, and TG2 opens, now RW#=RWT.

As shown in figure 11, be the logic processing module structural drawing of the embodiment of the present invention.This logic processing module 700 comprises the 3rd phase inverter 710, first and non-selection device 720, the first transmission gate 730, the second transmission gate 740 and the 4th phase inverter 750.Wherein, the input of the 3rd phase inverter 710 is connected with the output of last the first selection module 400.First is connected with the output terminal of output module 600 with the output terminal of the 3rd phase inverter 710 respectively with the input end of non-selection device 720.The input end of the first transmission gate 730 is connected with the output terminal of non-selection device 720 with first, and the input end of the second transmission gate 740 is connected with the output terminal of output module 600, and the first transmission gate 730 and the second transmission gate 740 are controlled by the 6th input OPGE.The input end of the 4th phase inverter 750 is all connected with the output terminal of the second transmission gate 740 with the first transmission gate 730.

As shown in figure 12, for second of the embodiment of the present invention, select the structural drawing of module.This second selection module comprises that the 2nd PMOS pipe MP2 of a PMOS pipe MP1, series connection and the 3rd PMOS pipe MP3 and the 12 NMOS that the 11 NMOS manages MN11, series connection manage MN12, the 13 NMOS pipe MN13 and the 14 NMOS pipe MN14.Wherein, the grid of a PMOS pipe MP1 is connected with the 5th input OPEQ, and the first end of a PMOS pipe MP1 is connected with power supply.The grid of the 2nd PMOS pipe MP2 and the 11 NMOS pipe MN11 is connected with the output terminal of the second precharge unit or Q-1 the first selection module, and the second end of the 11 NMOS pipe MN11 is connected with described GE link, and the first end of the 2nd PMOS pipe MP2 is connected with the second end of a PMOS pipe MP1.The grid of the 3rd PMOS pipe MP3 and the 12 NMOS pipe MN12 is all connected with the output terminal of the 11 NMOS pipe MN11 with the 2nd PMOS pipe MP2, and the second end ground connection of the 2nd PMOS pipe MP2, and the first end of the 3rd PMOS pipe MP3 is connected with the second end of a PMOS pipe MP1.The grid of the 13 NMOS pipe MN13 is connected with the 5th input OPEQ, and the second end ground connection of the 13 NMOS pipe MN13, and the first end of the 13 NMOS pipe MN13 is connected with the output terminal of the 12 NMOS pipe MN12 with the 3rd PMOS pipe MP3.The grid of the 14 NMOS pipe MN14 is connected with the output terminal of the 12 NMOS pipe MN12 with the 3rd PMOS pipe MP3, and the first end of the 14 NMOS pipe MN14 is connected with the input end of output circuit 600.

In the description of this instructions, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And the specific features of description, structure, material or feature can be with suitable mode combinations in any one or more embodiment or example.

Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.

Claims

1. A content-addressable memory CAM cell module with interval matching function, is characterized in that, comprising:

M content-addressable memory CAM storage units with interval matching function connected in series, wherein, the first output of the N-1th content-addressable memory CAM storage unit is connected to the N-th content-addressable memory CAM storage unit connected to the first input (EQ path), and the first output of the Mth content addressable memory CAM storage unit is grounded to form an EQ link, and the first output of the N-1th content addressable memory CAM storage unit The second output is connected to the second input (GE path) of the Nth content addressable memory CAM storage unit to form a GE link, the M and N are integers, and N is less than or equal to M, wherein the content Addressable memory CAM memory cells include:

A read-write and storage unit, the read-write and storage unit is respectively connected to a word line (WL) and a bit line (BL), and the read-write and storage unit has a first terminal (D) and a second terminal (D#) , wherein, the second terminal (D#) is the logical negation of the first terminal (D), and the read-write and storage unit further includes: a first inverter and a second inverter connected in antiparallel to each other, so The two nodes between the first inverter and the second inverter are respectively the first terminal (D) and the second terminal (D#) of the read-write and storage unit; and the ninth MOS transistor ( MN9) and the tenth MOS transistor (MN10), the gates of the ninth MOS transistor (MN9) and the tenth MOS transistor (MN10) are respectively connected to the word line (WL), and the ninth MOS transistor ( MN9) and the first end of the tenth MOS transistor (MN10) are respectively connected to the first end (D) and the second end (D#) of the read-write and storage unit, and the ninth MOS transistor (MN9) The second end is connected to the first bit line (BL), and the second end of the tenth MOS transistor (MN10) is connected to the second bit line (BL#), wherein the ninth MOS transistor (MN9) and the Ten MOS tubes (MN10) are all NMOS tubes;

The first MOS transistor (MN1) and the second MOS transistor (MN2), the first ends of the first MOS transistor (MN1) and the second MOS transistor (MN2) are respectively connected to the first input (EQ path) and the second input (GE path), and the second ends of the first MOS transistor (MN1) and the second MOS transistor (MN2) are respectively used as the first output and the second output;

The fifth MOS transistor (MN5) and the sixth MOS transistor (MN6) connected in series, the gates of the fifth MOS transistor (MN5) and the sixth MOS transistor (MN6) are respectively connected with the first One end (D) is connected to the second end (D#), and the first end of the fifth MOS transistor (MN5) is connected to the third input (SL), and the first end of the sixth MOS transistor (MN6) Connected to the fourth input (SL#), the node between the fifth MOS transistor (MN5) and the sixth MOS transistor (MN6) is connected to the first MOS transistor (MN1) and the second MOS transistor (MN2) The gates are all connected;

The seventh MOS transistor (MN7) and the eighth MOS transistor (MN8) connected in series, the gates of the seventh MOS transistor (MN7) and the eighth MOS transistor (MN8) are respectively connected to the first The two terminals (D#) are connected to the first terminal (D), and the first terminal of the seventh MOS transistor (MN7) is connected to the third input (SL), and the first terminal of the eighth MOS transistor (MN8) connected to the fourth input (SL#), wherein the fourth input (SL#) is the logical negation of the third input (SL);

The third MOS transistor (MN3), the gate of the third MOS transistor (MN3) is connected to the node between the seventh MOS transistor (MN7) and the eighth MOS transistor (MN8), and the third MOS transistor (MN8) The first end of the tube (MN3) is connected to said second input (GE path); and

A fourth MOS transistor (MN4), the gate of the fourth MOS transistor (MN4) is connected to the third input (SL), the first end of the fourth MOS transistor (MN4) is connected to the third MOS The second end of the tube (MN3) is connected, and the second end of the fourth MOS tube (MN4) is grounded,

Wherein, the first MOS transistor (MN1) to the eighth MOS transistor (MN8) are all NMOS transistors.

2. A word circuit with an interval matching function, is characterized in that, comprising:

a first pre-charging unit and a second pre-charging unit;

Four groups of interconnected content addressable memory CAM unit modules as claimed in claim 1, each group of content addressable memory CAM unit modules comprising four mutually connected content addressable memory CAM storage units, wherein, Each set of CAM unit modules includes one EQ link and one GE link;

Four first selection modules, each of the first selection modules is connected to one of the EQ links, the four first selection modules are connected in series, the first one of the first selection modules is connected to the first The pre-charging unit is connected;

Four second selection modules, each of the second selection modules is connected to one of the GE links, and the first second selection module is connected to the second pre-charging unit, wherein the four Each of the second selection modules is controlled by the fifth input (OPEQ), and the input terminal of the Qth second selection module is connected to the output terminal of the Q-1th first selection module, 1<Q≤4;

an output module, the input terminal of the output module is connected to the output terminal of the last one of the first selection modules, and is connected to the output terminals of the four second selection modules; and

A logic processing module, the logic processing module processes the output result of the output module according to the sixth input (OPGE) and the last output result of the first selection module.

3. the word circuit with interval matching function as claimed in claim 2, is characterized in that, described logic processing module further comprises:

a third inverter, the input end of the third inverter is connected to the output end of the last one of the first selection modules;

a first NAND selector, the input terminals of the first NAND selector are respectively connected to the output terminal of the third inverter and the output terminal of the output module;

A first transmission gate and a second transmission gate, the input terminal of the first transmission gate is connected to the output terminal of the first NAND selector, the input terminal of the second transmission gate is connected to the output terminal of the output module connected, and both the first and second transmission gates are controlled by a sixth input (OPGE); and

A fourth inverter, the input terminals of the fourth inverter are both connected to the output terminals of the first transmission gate and the second transmission gate.

4. the word circuit with interval matching function as claimed in claim 2, is characterized in that, described second selection module further comprises:

A first PMOS transistor (MP1), the gate of the first PMOS transistor (MP1) is connected to the fifth input (OPEQ), and the first end of the first PMOS transistor (MP1) is connected to a power supply;

The second PMOS transistor (MP2) and the eleventh NMOS transistor (MN11) are connected in series, the gates of the second PMOS transistor (MP2) and the eleventh NMOS transistor (MN11) are connected to the second pre-charging unit or the first The output terminal of Q-1 first selection module is connected, and the second terminal of the eleventh NMOS transistor (MN11) is connected to the GE link, and the first terminal of the second PMOS transistor (MP2) connected to the second end of the first PMOS transistor (MP1);

The third PMOS transistor (MP3) and the twelfth NMOS transistor (MN12) are connected in series, the gates of the third PMOS transistor (MP3) and the twelfth NMOS transistor (MN12) are connected with the second PMOS transistor (MP2) ) is connected to the output end of the eleventh NMOS transistor (MN11), and the second end of the second PMOS transistor (MP2) is grounded, and the first end of the third PMOS transistor (MP3) is connected to the first The second end of the PMOS tube (MP1) is connected;

a thirteenth NMOS transistor (MN13), the gate of the thirteenth NMOS transistor (MN13) is connected to the fifth input (OPEQ), and the second end of the thirteenth NMOS transistor (MN13) is grounded, The first end of the thirteenth NMOS transistor (MN13) is connected to the output ends of the third PMOS transistor (MP3) and the twelfth NMOS transistor (MN12); and

The fourteenth NMOS transistor (MN14), the gate of the fourteenth NMOS transistor (MN14) is connected to the output terminals of the third PMOS transistor (MP3) and the twelfth NMOS transistor (MN12), and the tenth The first ends of the four NMOS transistors (MN14) are connected to the input ends of the output module.

5. A content-addressable memory CAM memory with interval matching function, is characterized in that, comprising:

A plurality of word circuits as claimed in claims 2-4.