CN102339846A - Semiconductor memory device having transistor with adjustable gate resistance value - Google Patents

Abstract

The present invention discloses a semiconductor memory element with a transistor having an adjustable gate resistance value, including an array of memory cells capable of storing multiple bits of data. The memory cells are arranged in a plurality of memory strings connected to a common source line. Each memory cell includes a programmable transistor of a resistance value connected in series. The transistor includes a gate dielectric layer that can be switched and controlled between a plurality of different resistance values. The threshold voltage of the transistor varies according to the resistance value of the gate dielectric layer. Therefore, the storage state of these memory cells is related to the individual resistance values of the dielectric layer of the transistor.

Description

Semiconductor memory element having transistor with adjustable gate resistance value

technical field

The present invention relates to electronic memory devices, and in particular to semiconductor memory devices having transistors with adjustable gate resistance values suitable for use as non-volatile memory devices.

Background technique

An electronic memory device is a well-known electronic component that can be found in various electronic systems. For example, electronic memory elements (sometimes referred to as computer memory) can be found in computers and other computer elements. Various removable electronic memory devices or free-standing electronic memory devices are also known, such as memory cards or solid-state data access systems. For example, access photos from a digital camera using a removable memory card, or access recorded movies using a digital video recorder.

Most electronic memory elements can be classified as volatile or nonvolatile. A typical volatile electronic memory device is one that requires power to retain stored information. Volatile electronic memory elements may be, for example, static random access memory (SRAM) or dynamic random access memory (DRAM) computer memory elements, which retain stored data only when the computer is turned on, and when the computer After turning off or cutting off the power, the previously stored data will be lost. In contrast, general non-volatile electronic memory devices still have the ability to retain and store data without external power supply. A non-volatile memory is, for example, a memory card, which is widely used in digital cameras. The memory card can store the photos taken by the camera, and even if the memory card has been removed from the camera, the memory card can still retain these photo data.

As systems using electronic memory components become more powerful, the requirements for data storage capacity also increase. For example, more powerful computers and software generally operate better with more random access memory (RAM); high-resolution cameras produce larger photo and movie files, requiring greater storage capacity The memory card is set in it. Therefore, it is a trend in the electronic memory device industry to find a way to increase the data storage capacity of the memory device. However, simply increasing the capacity is not enough. It is generally desired to increase the data storage capacity while maintaining or even reducing the size of the memory element. Therefore, increasing data storage capacity for a given size is another trend in the electronic memory device industry, in other words, the trend towards greater bit density. There are also cost considerations. For example, as the bit density of an electronic memory device increases, it is desirable to maintain or reduce its manufacturing cost. In other words, it is desirable to reduce the bit cost (manufacturing cost per bit) of electronic memory components. Another consideration is related performance, such as providing faster data storage and faster stored data access on electronic memory devices.

A method provided to increase bit density is to reduce the size of individual memory cells. For example, when the manufacturing process is improved, smaller structures can be formed, thus allowing the manufacture of smaller memory cells. However, there are some plans that in the future when using this method, the cost of bits will start to increase, because the process cost will likely start to increase faster than the speed of memory cell shrinkage.

Contents of the invention

The present invention discloses memory devices and methods related to memory elements.

According to one aspect of the present invention, it is proposed that a memory element may include a memory cell array, wherein at least one memory cell among the plurality of memory cells includes a transistor having a first terminal, a second terminal, and a gate structure , and the gate structure includes a gate dielectric layer. The memory cell also includes a resistor connected in series with the gate structure of the transistor. The gate dielectric layer switchably corresponds to a first resistance value and a second resistance value, and the first resistance value and the second resistance value respectively correspond to a first storage state and a second storage state.

The first resistance of the gate dielectric layer corresponds to a soft breakdown state of the transistor. The second resistance of the gate dielectric layer corresponds to an at least partially inverted soft breakdown state of the transistor.

The transistor may further include a well terminal. At least one of a read operation, a program operation, and an erase operation may include applying a predetermined voltage to terminals of the well region. The programming operation includes applying a predetermined voltage to the gate structure, and the erasing operation includes applying a predetermined voltage to terminals of the well region. This programming operation induces a soft breakdown state of the transistor. This erase operation can at least partially reverse the soft breakdown state of the transistor.

The gate dielectric layer may include at least one of silicon dioxide (SiO ₂ ), hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), and titanium dioxide (TiO ₂ ).

The resistor may include a high resistance layer, and the gate structure may include a low resistance layer, and wherein the high resistance layer may be disposed between the gate dielectric layer and the low resistance layer.

According to another aspect of the present invention, a memory device may include a bit line, a word line, a memory string including a memory cell, and a common source line connected to the memory string. This string is connected to the bit line. The memory cell is connected between the common source line and the bit line. The memory cell includes a transistor having a first terminal, a second terminal, and a gate structure, wherein the gate structure includes a gate dielectric layer. The memory cell also includes a resistor electrically connected in series between the gate dielectric layer of the transistor and the word line. The gate dielectric layer switchably corresponds to a first resistance value and a second resistance value, and the first resistance value and the second resistance value respectively correspond to a first storage state and a second storage state.

The first resistance value of the gate dielectric layer corresponds to a soft breakdown state of the transistor. The second resistance of the gate dielectric layer corresponds to an at least partially inverted soft breakdown state of the transistor.

The transistor further includes a well terminal. At least one of a read operation, a program operation, and an erase operation may include applying a predetermined voltage to terminals of the well region. The programming operation may include applying a predetermined voltage to the gate structure, and the erasing operation may include applying the predetermined voltage to well region terminals. This programming operation induces a soft breakdown state of the transistor. This erase operation can at least partially reverse the soft breakdown state of the transistor.

The gate dielectric layer may include at least one of silicon dioxide (SiO ₂ ), hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), and titanium dioxide (TiO ₂ ). The resistor may include a high resistance layer, and the gate structure may include a low resistance layer, and wherein the high resistance layer is disposed between the gate dielectric layer and the low resistance layer.

The memory cell may be a first memory cell, and the memory element may further include a second memory cell formed on the first memory cell in a stacking direction such that the first memory cell and the second memory cell included in a three-dimensional memory array.

In order to make the above content of the present invention more comprehensible, these and other features, viewpoints, and embodiments of the present invention will be described in detail in the following section [implementation mode].

Description of drawings

FIG. 1 is a block diagram of a memory array according to an embodiment disclosed in the present invention.

FIG. 2 is a schematic diagram of a memory string of the memory device shown in FIG. 1 .

FIG. 3 is a schematic diagram of a storage unit of the memory device shown in FIG. 1 .

FIG. 4 is a graph showing the relationship between the gate resistance and the threshold voltage of the memory cell resistor shown in FIG. 3 .

FIG. 5 is a schematic diagram of a transistor of the memory cell shown in FIG. 3 .

FIG. 6 is a graph showing the relationship between the gate leakage current Ig and the gate voltage Vg of the transistors shown in FIG. 3 and FIG. 5 .

FIG. 7 is a graph showing the relationship between the gate leakage current Ig and the gate voltage Vg of an alternative embodiment of the memory cell shown in FIG. 3 .

FIG. 8 is a graph illustrating source characteristics of the transistors shown in FIGS. 3 and 5 .

9 and 10 illustrate a simulation result showing the effect of changing the resistance value Rp of the memory cell.

FIG. 11 is a graph showing the relationship between the gate current Ig and the number of soft breakdown-inducing voltage pulses applied to the gate of the transistor shown in FIG. 3 and FIG. 5 .

FIG. 12 shows gate characteristic curves of the transistors shown in FIGS. 3 and 5 in the pre-soft breakdown state, soft breakdown state, and at least partially reversed soft breakdown state.

FIG. 13 is a block diagram of a memory device, including the memory array shown in FIG. 1 .

FIG. 14 is a schematic diagram of memory cells of an embodiment of the memory array shown in FIG. 1 and the memory string shown in FIG. 2 .

FIG. 15 is a schematic diagram of polysilicon resistivity characteristics applicable to the memory cell shown in FIG. 14 .

FIG. 16 is a schematic diagram of an embodiment of the memory array with a three-dimensional structure shown in FIG. 1 .

[Description of main component symbols]

100, 252: memory array

102a-102c: storage unit

108a-108c: Transistors

110a-110c: grid

112a-112c: resistance

114, 254: Semiconductor substrate

116: source

118: drain

120: gate dielectric layer

122: Gate electrode

130: Defect

134, 138, 144, 148: solid line

136, 140, 146, 150: dotted line

160, 161, 162, 163, 164, 170, 171, 172, 173, 174, 180, 182, 184: curve

200: structure

202: block

204: page

222: High resistance value layer

224: Low resistance layer

250: 3D memory array

256: Conductive source line column

258a-258c: Bit line conductors

260c-260d: Conductive pillars

262: Ground Select Transistor Region

264: storage unit area

266: cascade select transistor area

268: Conductive channel

270, 280, 290: memory columnar semiconductor layer

272, 282, 292: memory gate insulating layer

274, 284, 294: Gate structure

BL1-BL3: bit lines

GSL: Ground Selection Line

MS1-MS3: storage string

Rg: fixed resistance value

Rp: variable gate resistor value

SL: source line

SSL, 260a-260b: serial selection line

Va: applied voltage

Vg: gate voltage

Vth: threshold voltage

Vth _high : High threshold voltage

Vth _low : low threshold voltage

WELL: well area

WL1-WL3: word lines

Detailed ways

FIG. 1 is a block diagram of a memory array 100 according to an embodiment disclosed in the present invention. The memory array 100 includes a plurality of memory cells 102, a plurality of bit lines BL1-BL3, a plurality of word lines WL1-WL3, a string select line SSL, a ground select line GSL, and a common source line SL.

The memory array 100 can be configured such that the storage units 102 are arranged as an array of m×n storage units 102 , where m and n are natural numbers respectively. More specifically, the memory array 100 can be configured in such a way that the memory cells 102 therein are a plurality of memory strings MS1-MS3. Each memory string MS includes one series selection transistor SST, one group of n memory cells 102, and ground selection transistors GST connected in series. The memory strings MS1-MS3 are connected to bit lines BL1-BL3, respectively. The memory strings MS1-MS3 are all connected to the common source line SL.

FIG. 2 shows a schematic diagram of a storage string MS1, which is an example of a storage string, and the storage string can be any of the storage strings MS1-MS3 shown in FIG. 1 . The memory string MS1 includes a serial select transistor SST, first to fourth memory cells 102a-102c, and a ground select transistor GST. The series selection transistor SST, the first to third memory cells 102a-102c, and the ground selection transistor GST are connected in series between the bit line BL1 and the common source line SL. Although memory string MS1 includes three memory cells 102a-102c, actual implementations may include additional memory cells, such as 16, 32, 64 or more memory cells. The first through third memory cells 102a-102c include transistors 108a-108c, respectively. Transistors 108a-108c include gates 110a-110c with adjustable resistance, respectively. Memory cells 102a-102c also include resistors 112a-112c, respectively. Additionally, in some embodiments, adjacent transistors 108 may share a common source and/or common drain to reduce memory cell size. If neither the source nor the drain is shared in an adjacent transistor, it is difficult to achieve a desired design rule, which cannot be larger than 4F ² .

The gate of the series selection transistor SST is connected to the series selection line SSL. The source of the series selection transistor SST is connected to the bit line BL1. The drain of the series selection transistor SST is connected to the first memory cell 102a.

The gate of the ground selection transistor GST is connected to the ground selection line GSL. The source of the ground select transistor GST is connected to the last memory cell 102c. The drain of the ground selection transistor GST is connected to the common source line SL.

FIG. 3 is a schematic diagram of a storage unit 102 according to an embodiment disclosed in the present invention. The storage units 102a-102c may be configured as shown in FIG. 3 . The memory cell 102 includes a transistor 108 and a resistor 112 . The transistor 108 includes a gate 110 with adjustable resistance.

The transistor 108 may be a field effect transistor (FET), such as a metal oxide semiconductor field effect transistor (MOSFET). The transistor 108 may include a semiconductor substrate 114 , a source 116 , a drain 118 , and a gate 110 . The gate 110 includes a gate dielectric layer 120 and a gate electrode 122 . The source 116 of the transistor 108 is connected to the bit line BL through the serial connection of the select transistor SST and any memory cell 102 therebetween as shown in FIG. 2 . The drain 118 of the transistor 108 is connected to the common source line SL through the ground select transistor GST and any memory cells 102 therebetween as shown in FIG. 2 . The gate electrode 122 of the transistor 108 is connected to the word line WL through the resistor 112 . The semiconductor substrate 114 is connected to an array of well contact leads.

The resistor 112 can be a fixed resistor with a fixed resistance value Rp. The resistor 112 is connected in series with the gate 110, and the gate 110 has a variable gate resistance Rg. It is explained here that the resistance Rg is adjustable. The memory cell 102 receives the voltage Va applied to the memory cell from the word line. A voltage difference (Va−Vg) is generated across the resistor 112 , and the gate voltage Vg is applied to the gate 110 of the transistor 108 . According to equation (1) shown below, the gate voltage Vg has a corresponding relationship with the applied voltage Va.

$\mathrm{<span\; class="notranslate">\; Vg</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; Va</span>}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; Rg</span>}}{\mathrm{<span\; class="notranslate">\; Rp</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; Rg</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Therefore, the gate voltage Vg and the gate resistance Rg are dependent. Therefore, if the gate resistance Rg is controlled to change from one resistance value to another resistance value, the effective gate voltage Vg will also change accordingly, resulting in a different current.

FIG. 4 shows a simulation result of a MOSFET. When the gate resistance Rg changes from 1 GΩ to 1 MΩ, the curve changes from a solid line 134 to a dashed line 136 . In this example, a MOSFET has a 3 nm gate oxide, a P-type well doping of about 2E17 cm ⁻³ , and resistor 112 with a fixed resistance value of 1 MΩ. FIG. 4 shows that the resistance Rg changes from 1GΩ to 1MΩ, causing the threshold voltage Vth to shift from a lower threshold voltage Vth _low to a high threshold voltage Vth _high . Therefore, the transistor 108 with adjustable resistance can cause the threshold voltage Vth to drift by changing the gate resistance Rg. In contrast, for the floating gate transistor, the threshold voltage Vth drift of the floating gate transistor is caused by caused by the stored charge. The adjustable resistance transistor 108 does not need to have stored charge to obtain a shift in the threshold voltage Vth.

The gate dielectric layer 120 may be formed of thin silicon dioxide (SiO ₂ ). The change of the resistance value on the gate 110 can be implemented by utilizing a well-known soft breakdown (SBD) state, which has been undesirable in the past. As shown in FIG. 5 , in newly manufactured MOS devices, there is an arbitrary number of defects 130 in the gate oxide of the gate dielectric layer 120 . Over time, due to operating stress, more defects 130 are formed, so that tiny conductive paths are created through the oxide. During this process, current conduction is induced due to conductive paths formed by oxide defects and gate oxide tunneling through the gate dielectric layer 120 . The formation of these conductive paths is considered a soft breakdown. These conductive paths may be repaired due to the high temperature generated at the defect site by the high current density. The high temperature may reset some of the oxide defects 130, destroying the conductive path. The gate dielectric layer 120 may be formed by replacing the thin silicon dioxide (SiO ₂ ) with a high-k material having a high or higher dielectric constant than silicon dioxide. K value. Examples of suitable high dielectric constant materials include hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), and titanium dioxide (TiO ₂ ). High-k materials generally have more defects than silicon dioxide, thus providing a simpler operation in changing the gate resistance Rg.

FIG. 6 shows the relationship between the gate leakage current Ig and the gate voltage Vg of a transistor 108 before and after the soft breakdown, wherein the transistor 108 is represented by a solid line 138 before the soft breakdown, and the transistor 108 is indicated by dashed line 140 after soft breakdown. For example, before soft breakdown, the gate leakage current of the oxide layer of the thin gate dielectric layer 120 with a thickness less than 3 nm is generally less than 1 nA, and the corresponding gate resistance Rg is greater than 1 GΩ. In a MOSFET, soft breakdown of the gate dielectric layer 120 can be induced by applying a gate voltage Vg of about +4.3V. After the soft breakdown of the gate dielectric layer 120 occurs, the gate leakage current becomes about 1 μA, and the corresponding gate resistance Rg is about 1 MΩ. Soft breakdown uses lower power consumption than general phase change random access memory (PCRAM) or phase change memory (PRAM).

The characteristics of the adjustable resistance transistor 108 can be changed according to the above description. For example, the thickness of the gate oxide and the doping of the P-well region can be varied according to the above-mentioned exemplary values. In addition, the resistance value of the fixed resistor 112 can also be changed from the above-mentioned resistance value of 1 MΩ.

For example, FIG. 7 shows the relationship between the gate leakage current Ig and the gate voltage Vg of an alternative embodiment of the memory cell 102 . Transistor 108 is an N-channel MOSFET with a 1 nm thick gate oxide. The resistor 112 has a fixed resistance value of 20MΩ. The relationship between the gate leakage current Ig and the gate voltage Vg before the soft breakdown is shown by the solid line 144 , and the relationship after the soft breakdown is shown by the dashed line 146 . In this embodiment, the initial gate oxide resistance Rg before soft breakdown is about 1 GΩ. Soft breakdown can be induced using a 4.3V pulse voltage with a duration of about 1 μs. After the soft breakdown, the gate oxide resistance Rg decreases and is fixed by the fixed resistor 112 . In this embodiment, the resistance value Rg of the gate oxide after the soft breakdown is reduced to about 1 MΩ.

FIG. 8 illustrates the source characteristics of the transistor 108 of the memory cell 102 of this embodiment. The relationship between the source current Is and the gate voltage Vg before the soft breakdown is shown by the solid line 148 , and the relationship after the soft breakdown is shown by the dashed line 150 . As shown in FIG. 8 , after soft breakdown, the source current drops significantly, because compared to the gate resistance Rg of the gate 110, the applied gate voltage difference is the majority across the resistor 112 The relationship on the fixed resistance value Rp. Therefore, the soft breakdown causes an obvious drop in the drain/source current of the transistor 108 . In this embodiment, the current difference between the source current Is before the soft breakdown and the source current Is after the soft breakdown exceeds two orders of magnitude. Therefore, the significantly different drain/source currents of the transistor 108 can be used as different storage states of the memory cell 102 .

9 and 10 illustrate simulation results showing the effect of changing the resistance Rp of the memory cell 102 . More specifically, FIG. 9 shows the gate current characteristics of the transistor 108 under the fixed resistance value Rp corresponding to different values; FIG. 10 shows the source/drain current of the transistor 108 under the fixed resistance value Rp corresponding to different values characteristic. In Fig. 9, curve 160 shows the result of the state before soft breakdown; Curve 161 shows the result when Rp=4.7MΩ; Curve 162 shows the result when Rp=20MΩ; Curve 163 shows when Rp = 40MΩ; and curve 164 shows the result when Rp = 80MΩ. In Fig. 10, curve 170 shows the result of the state before soft breakdown; Curve 171 shows the result when Rp=4.7MΩ; Curve 172 shows the result when Rp=20MΩ; Curve 173 shows when Rp = 40MΩ; and curve 174 shows the result when Rp = 80MΩ. Therefore, it can be seen from the simulation results in FIG. 9 and FIG. 10 that when the resistance value of the fixed resistance Rp increases, both the gate current and the drain/source current will decrease.

In some embodiments, the memory cell 102 can be used as a One Time Program memory element. FIG. 11 shows the relationship between the gate current Ig of the transistor 108 and the number of SBD-inducing voltage pulses applied to the gate 100 of the transistor 108 . When the soft breakdown inducing pulse voltage is applied to the transistor 108, the gate current Ig changes step by step. When the number of soft breakdown-inducing pulse voltages applied increases, the gate current Ig at a given read voltage of +2V increases accordingly. This occurs due to the progressive mechanism of gate oxide breakdown. Therefore, the memory cell 102 can be used as a multilayer one-time programmable memory device. In such an embodiment, the desired gate current Ig can be selected by applying a corresponding predetermined number of soft breakdown-inducing voltage pulses to the gate 110 of the transistor 108 .

In other embodiments, the memory cell 102 can be used as a re-writable memory element. FIG. 12 shows the gate characteristics of the transistor 108 according to the simulation results of the state before soft breakdown (curve 180 ) and the soft breakdown state (curve 182 ). The breakdown state represented by curve 182 can be induced by applying a gate pulse voltage for a predetermined period of time. In this simulation example, the breakdown state was induced by applying a pulse voltage of 4.3V with a pulse width of about 1 μs.

However, the soft breakdown state can be at least partially reversed by applying a pulse voltage having an opposite polarity to the voltage inducing the soft breakdown state. In addition, the pulse width of the SBD-reversing pulse voltage may be different from the pulse width of the SBD-inducing pulse voltage. The gate characteristic of the transistor 108 is represented by the curve 184 in FIG. 12 under the condition of partially inverting the soft breakdown voltage. In this illustrated example, the partially reversed soft breakdown state is achieved by applying a pulse voltage of -4.3V with a pulse width of approximately 3 μs.

The soft breakdown state of transistor 108 may be at least partially inverted to such an extent that the gate characteristics of transistor 108 in the soft breakdown state and the gate characteristics of transistor 108 in the partially reversed soft breakdown state are distinguishable. In addition, by applying an appropriate pulse voltage, the transistor 108 can be repeatedly switched between the soft breakdown state and the reverse soft breakdown state (or at least a part of the reverse soft breakdown state). Therefore, the soft breakdown state and the at least partially reversed soft breakdown state can be regarded as separate storage states. For example, the soft breakdown state represented by curve 182 may be considered a "programmed" state of memory cell 102, and the at least partially reversed soft breakdown state represented by curve 184 may be considered a "programmed" state of memory cell 102. an "erased" state.

Next please refer to FIG. 13 , similar to FIG. 1 and FIG. 2 , the operation of the rewritable memory embodiment of the memory array 100 will be described here. In general, the voltage levels of word lines WL1-WL3, bit lines BL1-BL3, and source lines SL, as well as the states of ground select transistors GST and series select transistors SST can be controlled to control any memory cell of memory array 100. For programming, erasing, or reading actions. A more detailed description is that along with the operation of the memory array 100, specific references will be made to one or more specific memory cells of the memory array 100; Other memory cells, and can also be equivalent to other alternative embodiments of the memory array 100, including additional memory cells, bit lines, word lines, ground selection transistors, cascaded selection transistors, and/or other elements.

The memory array 100 may be a part of a memory device 200 organized by a plurality of blocks 202 , and each block 202 is further organized by a plurality of pages 204 . For example, in one embodiment, a 2-Gbit embodiment of the memory device 200 may include 2048 blocks 202, with 64 pages 204 in each block 202, and each page 204 has 2112 bits, So that the memory device 200 is composed of a series of 128-kbyte blocks 202 . Other embodiments may include additional or fewer bits of memory, blocks 202 , pages 204 , and/or bits per page 204 .

The memory device 100 may also include a multi-bit interface (not shown) for data transmission or reception to the memory array 100, such as an 8 or 16-bit interface. The received data can be written into memory as binary data, which is stored as logic level 1 or logic level 0. Memory element 200 may be initialized such that memory cells 102 are initially set to a logic level 1 or a logic level 0. After initialization, data can be written into such memory cells 102 using erase and program operations. The erase operation can store a logic level 1 into the memory cell 102 . The program operation may store a logic level 0 into the memory cell 102 . In some embodiments, erase operations are sequentially performed on a block 202 of memory elements 200, and program operations are sequentially performed on bits of the memory.

The programming operation changes the state of the erased bit to a logic level zero state. The programming operation completes this state transition by inducing a transistor 108, which selects the memory cell 102 to be programmed, to have a soft breakdown state. For example, in the above-described embodiment, the soft breakdown state can be induced by applying a word line WL voltage of 4.3V to the selected memory cell 102 . The remaining memory cells 102 of the memory array 100 can be kept below the soft breakdown induced voltage level.

For example, referring to FIG. 1 , a selected memory cell 102 (shown by a dotted box) can be programmed by raising the voltage of the word line WL1 to 4.3V while the bit line BL3 is set at 0V. At this time, the remaining word lines WL2 and WL3 are boosted to 3.3V, and the remaining bit lines BL1 and BL2 are also boosted to 3.3V. Since the potential across the other unselected memory cells 102 is lower than the voltage requirement for inducing the soft breakdown state, the other unselected memory cells 102 will not be programmed. In addition, the series selection transistor SST of the third memory string is turned on, for example, by raising the voltage of the series selection line SSL to (or greater than) the threshold voltage Vth of the series selection transistor SST, such as 3.3V. Since the voltage of the bit line BL3 is 0V, and the voltage of the bit lines BL1 and BL2 is 3.3V, only the serial selection transistor SST of the third storage string MS3 is turned on; The series selection transistor SST remains off. The ground select transistor GST of the third memory string MS3 remains turned off, and the source line SL is floating. Therefore the voltage across the selected memory cell 102 at the intersection of the word line WL1 and the bit line BL3 is at least high enough to induce a soft breakdown state in the transistor 108 of the selected memory cell 102, so it is selected memory cell 102 is programmed.

As another example, please still refer to FIG. 1, the bit line BL3 can be set at 0V, and the voltage of the word line WL1 can be raised to 4.3V to program the selected memory cell 102 (shown by a dotted box) . Simultaneously, the remaining word lines WL2 and WL3 are boosted to 3V, and the remaining bit lines BL1 and BL2 are also boosted to 1V. Since the voltage across the other unselected memory cells 102 is less than the requirement to induce a soft breakdown state, the other unselected memory cells 102 will not be programmed. In addition, the series selection memory SST of the third storage string MS3 is turned on, for example, by raising the voltage of the series selection line SSL to (or greater than) the threshold voltage of the series selection transistor SST, such as 1V, and the series selection The threshold voltage of transistor SST is 0.7V. Since the voltage of the bit line BL3 is 0, and the voltage of the bit lines BL1 and BL2 is 1V, only the serial selection transistor SST of the third storage string MS3 is turned on; the remaining first storage string MS1 and the second storage string MS2 The series select transistor SST remains off. The ground select transistor GST of the third memory string MS3 may remain turned off, and the source line SL may be floating. Therefore, the voltage across the selected memory cell 102 at the intersection of the word line W1 and the bit line BL3 is at least high enough to induce a soft breakdown state in the transistor 108 of the selected memory cell 102 and is therefore called Selected memory cells 102 are programmed.

The erase operation changes the state of the programmed bit to a logic level 1 state. The erase operation accomplishes this state transition by at least partially inverting a soft breakdown state of the transistor 108 that selects the memory cell 102 to be erased. For example, in the above-described embodiment, the soft breakdown state can be partially reversed by applying a word line WL voltage of -4.3V across the selected memory cell 102 . In other words, the word line of the programmed memory cell 102 is set to a potential that is lower than 4.3V in the substrate well region of the transistor 108 of those memory cells 102 that are programmed. The remaining memory cells 102 of the memory array 100 can be kept below the soft breakdown induced voltage level.

For example, referring to FIG. 1, a selected memory cell 102 (shown by a dashed box) may be erased by an erase process that includes a block erase step that erases memory cells 102 throughout memory array 100. erase. After the block erase, any memory cells 102 that should store a logic level of 0 can be reprogrammed to a logic level of 0. The erasing process includes setting the voltage of the word lines WL1-WL3 at 0V, while the voltage of the substrate well region is set at 4.3V. In addition, the series selection transistor SST and the ground selection transistor GST of the first memory string MS1 to the third memory string MS3 are turned off, for example, by raising the voltage of the series selection line SSL and the ground selection line GSL to approximately the same as the well region voltage 4.3V to generate a net potential of 0V across the series select transistor SST and the ground select transistor GST. Bit lines BL1-BL3 and source line SL may be floating. Therefore, the negative word line WL potential across the plurality of memory cells 102 of the memory array 100 is at least high enough to at least partially reverse the soft breakdown state of the transistors 108 of these memory cells 102, so that these memory cells 102 Cell 102 is erased. It should be understood here that if an insufficient number of memory cells 102 are to be erased, then some erase processes may include erase status verification as well as the block erase process described above.

The read operation detects the state of a selected memory cell 102 to determine whether the selected memory cell 102 is set to a logic level 0 or a logic level 1 state. The read operation can detect the logic level of the selected memory cell 102 by applying a read voltage Vread to the word line connected to the selected memory cell 102 , in this example word line WL1 . As shown in FIG. 4 , the threshold voltage Vth of the transistor 108 is related to whether the transistor 108 is set in a soft breakdown state or is set in an at least partially inverted soft breakdown state. When the transistor 108 is in the soft breakdown state, the gate resistance Rg is relatively low, so the threshold voltage Vth is set to a relatively high threshold voltage Vth _high . On the other hand, when the transistor 108 is in the at least partially inverted soft breakdown state, the gate resistance Rg is relatively high, so the threshold voltage Vth is set to a relatively low threshold voltage Vth _low . Therefore, the state of the transistor 108 and the similar storage state of the memory cell 102 can be detected by detecting whether the threshold voltage of the transistor 108 is a high threshold voltage Vth _high or a low threshold voltage Vth _low . Therefore, the logic level of the selected memory cell 102 can be detected by applying a gate voltage to the transistor 108 of the selected memory cell 102, so that the transistor 108 can only be set to a low threshold voltage when the threshold voltage Vth of the transistor is set to a low threshold voltage. Vth _low will be turned on. Therefore, the applied gate voltage should be selected to be greater than or equal to the low threshold voltage Vth _low and less than the high threshold voltage Vth _high .

For example, the storage state of the selected memory cell 102 can be detected by applying a read voltage Vread across the word line across the memory cell 102 . The read voltage Vread is selected such that the V _GS of the transistor 108 of the selected memory cell 102 is less than the high threshold voltage Vth _high and greater than or equal to the low threshold voltage Vth _low . The remaining memory cells 102 in string MS3 are operated in a pass-through mode. Since the storage states of the remaining memory cells 102 of the memory string MS3 can be logic level 1 or logic level 0, the V _GS applied to these memory cells 102 should be greater than or equal to the high threshold voltage Vth _high to operate in the pass-through mode These transistors 108 do not care about the storage states of these memory cells 102 . In addition, the series selection transistor SST and the ground selection transistor GST of the memory string MS3 are turned on, and the voltage level of the bit line BL3 is raised, so that if the transistor 108 of the selected memory cell 102 is turned on, the selected The V _DS of the transistor 108 of the memory cell 102 will rise to a voltage high enough to pass an appreciable drain current Id. The series selection transistors SST and ground selection transistors GST of the remaining memory strings MS1 and MS2 are turned off.

The following table (Table 1 ) summarizes the operation of the memory array 100 by way of example using voltage levels according to one embodiment of the memory array 100 . The exact voltage levels listed in Table 1 may vary for different embodiments, particularly those of transistor 108 characteristics and resistor 112 characteristics.

Referring next to FIG. 14 , a structure 220 shows an embodiment of the memory unit 102 . As shown in FIG. 3 , the memory cell 102 includes a resistor Rp connected in series with the gate terminal 122 . The structure 220 may provide a resistor 112 of resistance Rp connected in series to the gate 110 of the transistor 108 . The structure 220 includes a high resistance layer 222 disposed over the gate dielectric layer 120 . The structure 220 also includes a low resistance layer 224 disposed over the high resistance layer 222 . The low-resistance layer 224 can be formed of a low-resistance material, such as a metal silicide, so that the low-resistance layer 224 can be used as a low-resistance gate electrode. The high-resistance layer 222 may be composed of a low-doped polysilicon material. The layer 222 of low-doped polysilicon material is formed to provide a parasitic resistance Rp, for example, in a range of 1 MΩ to 10 MΩ.

FIG. 15 shows which doping concentration of the p-type polysilicon material can be selected to provide the desired resistivity of the low-resistance layer 224 . As shown in the data in FIG. 15, p-type polysilicon material can be doped to a concentration lower than 10 ¹⁷ cm ³ to obtain a resistivity higher than 10 ³ Ω-cm. Therefore, for the high-resistance layer 222, a resistance value Rp greater than 10 MΩ can be obtained at the node of 15 nm.

FIG. 16 shows a three-dimensional memory array 250 of one embodiment of the memory array 100 having a three-dimensional architecture. The three-dimensional memory array 250 includes a memory array 252 formed on a substrate 254 in a lamination direction. The memory array 252 is formed between a column of conductive source lines 256 and a series of vertically spaced bit line conductors 258a-258c. A series of conductive series select lines 260a-260b are formed on memory array 252 in a lamination direction. Cascade select lines 260a-260b may be connected to cascade select transistor region 266 through conductive pillars 260c and 260d.

The substrate 254 may be formed by a wafer, such as a silicon wafer or other types of wafers. In some embodiments, substrate 254 may include a buried oxide layer. For example, the substrate 254 may include a silicon-on-insulator (SOI) material.

The conductive source line column 256 can provide a common source line for the memory array 250 . The bit line conductors 258a-258c may be provided as bit lines BL1-BL3, respectively. Conductive source line field 256, bit line conductors 258a-258c, and series select lines and conductive posts 260a-260d may be formed of a conductive material, such as tungsten.

Memory array 252 includes ground select transistor region 262 , memory cell region 264 , and cascaded select transistor region 266 . A plurality of conductive vias 268 provide the desired conductive interconnection between the ground select transistor region 262 , the memory cell region 264 , and the cascode select transistor region 266 . The conductive channels 268 may be formed of a conductive material, such as tungsten.

The ground selection transistor region 262 includes a plurality of memory columnar semiconductor layers 270 . A plurality of memory gate insulating layers 272 are respectively formed as sidewalls of the memory columnar semiconductor layers 270 . A plurality of gate structures 274 are respectively formed on sidewalls of the memory gate insulating layer 272 . The memory columnar semiconductor layer 270 and the gate structure 274 are formed of polysilicon. Part of the memory columnar semiconductor layer 270 may be formed of p ⁺ and n ⁺ doped polysilicon. The memory gate insulating layer 272 may be formed of a gate dielectric material, such as silicon oxide.

The memory cell region 264 includes a plurality of memory columnar semiconductor layers 280 . The memory gate insulating layers 282 are formed as sidewalls of the memory columnar semiconductor layers 280 respectively. A plurality of gate structures 284 are formed on sidewalls of the memory gate insulating layer 282 . The memory columnar semiconductor layer 280 and the gate structure 284 may be formed of polysilicon. Part of the memory columnar semiconductor layer 280 may be formed of p ⁺ and n ⁺ doped polysilicon. The memory gate insulating layer 282 may be formed of a gate dielectric material such as silicon dioxide (SiO ₂ ) or a high dielectric constant material such as hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), and Titanium dioxide (TiO ₂ ).

The cascaded selection transistor region 266 includes a plurality of memory columnar semiconductor layers 290 . The memory gate insulating layers 292 are formed as sidewalls of the memory columnar semiconductor layers 290 respectively. A plurality of gate structures 294 are formed on sidewalls of the memory gate insulating layer 292 . The memory columnar semiconductor layer 290 and the gate structure 294 may be formed of polysilicon. Part of the memory columnar semiconductor layer 290 may be formed of p ⁺ and n ⁺ doped polysilicon. The memory gate insulating layer 292 may be formed of a gate dielectric material, such as silicon oxide.

Therefore, according to the present disclosure, a 1T MOSFET memory is provided, and the threshold voltage of the memory transistor is shifted by using the variation of the gate resistance Rg. A change in the gate resistance Rg through a series connection of the resistor Rp results in a significant shift in the threshold voltage Vth. Preferably, Rg (after soft breakdown) and Rp are between a similar range of resistance values. The difference between the drain current Id and the threshold voltage Vth is used to define the storage state of the memory cell as logic level 1 or logic level 0. The memory cell operates as a four-terminal device, including a gate/resistors Rp and Rg, a source, a drain, and a well region. Different high dielectric constant materials or materials similar to phase change memory can be used as the material of the gate resistance Rg. An array structure similar to a NAND gate can be used as the memory device disclosed in the present invention. The memory cell can be fabricated according to a 4F ² design rule. A three-dimensional NAND-like structure can also be used to provide ultra-high memory density, such as a 1T-bit capacity.

Compared with phase-change memory, the memory cell disclosed in the present invention can use phase-change memory material on the gate dielectric layer of a MOSFET, and the memory cell disclosed in the present invention uses the change of gate resistance for programming /erase operations instead of using charge storage for operations. Since the memory cell of the present invention sends a detection current through the source of the transistor, there is no need to ask for a larger current to break down the material, so the programming current of the memory cell of the present invention can be lower than that of a phase change memory. current. Since the present invention uses the change of gate resistance instead of charge storage for data storage, the memory cell of the present invention does not encounter the problem of charge storage.

The memory cell of the present invention may comprise an ultra-thin gate oxide (-1 nm) MOSFET in a memory array with ^4F2 memory cells. Since the ultra-thin gate oxide MOSFET can be scaled down to less than 10 nm, multiple extremely scaled devices (eg, channel aspect ratios less than 10 nm) are possible with the memory array of the present invention.

In summary, although the present invention has been described and disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (21)

1. A memory element comprising an array having a plurality of memory cells, at least one of the plurality of memory cells comprising: A transistor having a first terminal, a second terminal, and a gate structure including a gate dielectric layer; and a resistor in series with the gate structure of the transistor, Wherein the gate dielectric layer is switchably corresponding to a first resistance value and a second resistance value, and the first resistance value and the second resistance value respectively correspond to a first storage state and a second storage state. 2. The memory device according to claim 1, wherein the first resistance value of the gate dielectric layer corresponds to a soft breakdown state of the transistor. 3. The memory device of claim 2, wherein the second resistance value of the gate dielectric layer corresponds to an at least partially inverted soft breakdown state of the transistor. 4. The memory device of claim 3, wherein the transistor further comprises a well terminal. 5. The memory device of claim 4, wherein at least one of a read operation, a program operation, and an erase operation includes applying a predetermined voltage to the well region terminal. 6. The memory device according to claim 5, wherein the programming operation includes applying the predetermined voltage to the gate structure, and the erasing operation includes applying the predetermined voltage to the well region terminal. 7. The memory element of claim 6, wherein the programming operation induces the soft breakdown state of the transistor. 8. The memory element of claim 7, wherein the erase operation at least partially reverses the soft breakdown state of the transistor. 9. The memory element according to claim 1, wherein the gate dielectric layer comprises silicon dioxide (SiO ₂ ), hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), and titanium dioxide (TiO ₂ ) at least one of the 10. The memory device according to claim 1, wherein the resistor comprises a high resistance layer, and the gate structure comprises a low resistance layer, and wherein the high resistance layer is disposed on the gate dielectric layer and the low-resistance layer. 11. A memory element comprising: one bit line; one word line; a memory string including a memory cell; and a common source line connected to the memory string; wherein the memory string is connected to the bit line; Wherein the memory cell is connected between the common source line and the bit line, the memory cell includes: A transistor having a first terminal, a second terminal, and a gate structure including a gate dielectric layer; and a resistor electrically connected in series between the gate dielectric layer of the transistor and the word line, Wherein the gate dielectric layer is switchably corresponding to a first resistance value and a second resistance value, and the first resistance value and the second resistance value respectively correspond to a first storage state and a second storage state. 12. The memory device of claim 11, wherein the first resistance value of the gate dielectric layer corresponds to a soft breakdown state of the transistor. 13. The memory device of claim 12, wherein the second resistance value of the gate dielectric layer corresponds to an at least partially inverted soft breakdown state of the transistor. 14. The memory device of claim 13, wherein the transistor further comprises a well terminal. 15. The memory device of claim 14, wherein at least one of a read operation, a program operation, and an erase operation comprises applying a predetermined voltage to the well region terminal. 16. The memory device of claim 15, wherein the programming operation includes applying the predetermined voltage to the gate structure, and the erasing operation includes applying the predetermined voltage to the well region terminal. 17. The memory element of claim 16, wherein the programming operation induces the soft breakdown state of the transistor. 18. The memory element of claim 17, wherein the erase operation at least partially reverses the soft breakdown state of the transistor. 19. The memory element according to claim 11, wherein the gate dielectric layer comprises silicon dioxide (SiO ₂ ), hafnium dioxide (HfO ₂ ), zirconium dioxide (ZrO ₂ ), and titanium dioxide (TiO ₂ ) at least one of the 20. The memory device of claim 11, wherein the resistor comprises a high resistance layer, and the gate structure comprises a low resistance layer, and wherein the high resistance layer is disposed on the gate dielectric layer and the low-resistance layer. 21. The memory element according to claim 11, wherein the memory cell is a first memory cell, and wherein the memory element further comprises a second memory cell formed on the first memory cell in a stacking direction, The first storage unit and the second storage unit are included in a three-dimensional memory array.

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