CN102323529B - Characteristic present's method of the parasitical bipolar transistor of MOS transistor - Google Patents
Characteristic present's method of the parasitical bipolar transistor of MOS transistor Download PDFInfo
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- CN102323529B CN102323529B CN201110225196.0A CN201110225196A CN102323529B CN 102323529 B CN102323529 B CN 102323529B CN 201110225196 A CN201110225196 A CN 201110225196A CN 102323529 B CN102323529 B CN 102323529B
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- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000012360 testing method Methods 0.000 claims abstract description 9
- 238000005259 measurement Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 238000010998 test method Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
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Abstract
The present invention relates to a kind of characteristic present's method of parasitical bipolar transistor of MOS transistor, comprise the steps: the leakage current Id measuring described MOS transistor; Measure the gate-induced drain leakage Igidl of described MOS transistor; Measure the voltage Vds between the source electrode of described MOS transistor and drain electrode, the voltage Vce also namely between parasitic bipolar transistor emitter and collector; According to the described leakage current Id recorded and described gate-induced drain leakage Igidl, utilize Id=(1+ β) Igidl, calculate the current gain factor beta of described parasitical bipolar transistor; Generate the fitting function of the voltage Vce between the current gain factor beta of described parasitical bipolar transistor and emitter and collector.Method of testing of the present invention can contact the tagma of MOS transistor, and test process is simple.
Description
Technical field
The present invention relates to a kind of metal-oxide semiconductor (MOS) (MetalOxideSemiconductor, MOS) parasitical bipolar transistor (BipolarJunctionTransistor of transistor, BJT) characteristic present's method, particularly relate to characteristic present's method of the parasitic BJT of the MOS transistor of the silicon structure (SiliconOnInsulator, SOI) in a kind of laterally (lateral) dielectric substrate.
Background technology
The MOS transistor of soi structure is because having larger current driving force, and steep sub-threshold slope, less short channel, the advantages such as narrow-channel effect, are specially adapted to the application of high speed, low pressure, low consumption circuit.
Refer to Fig. 1, Fig. 1 is a kind of cross-sectional view of MOS transistor of soi structure of prior art.Described transistor comprises support substrates 11, is formed at the insulation course 12 on described substrate 11 surface, is formed at the tagma (body) 13 on described insulation course 13 surface, source region 14, drain region 15, gate medium 16 and grid 17.Produce floater effect (FloatingBodyEffects, FBE) due to the voltage fluctuation in tagma 13, the normal work of floater effect to SOIMOS transistor produces ill-effect, and wherein modal is kink effect and ambipolar effect.
When the channel region of MOS transistor is by local depletion and when applying high drain voltage, the electric field produced in MOS transistor produces impact ionization near drain region 15.Therefore, if SOIMOS transistor is N-MOS transistor, the hole of generation is injected into tagma 13 and produces positive electric charge body.The positive charge accumulated in tagma 13 causes the increase of bulk potential, and then causes SOIMOS crystal starting voltage V
treduction.Because the reduction of starting voltage improves drain current, the change of starting voltage shows as kink (Kink) in the transfer curve of SOIMOS transistor.
Because MOS transistor comprises the parasitical bipolar transistor of a transverse direction, namely the NPN transistor formed by source region 14, tagma 13, drain region 15, wherein, the collector (c) that the base stage (b) that source region 14 is the emitter (e) of described NPN transistor, tagma 13 is described NPN transistor, drain region 15 are described NPN transistor, as shown in Figure 2.The increase of described MOS transistor bulk potential also causes described NPN transistor conducting.Described NPN transistor is exaggerated the hole current near described drain region 15, and causes the second time kink effect of MOS transistor leakage current.
In each characterisitic parameter of bipolar transistor, current gain factor beta is one of most important characteristic, for characterizing the enlargement factor of bipolar transistor to base current.Therefore, the current gain factor beta of described bipolar transistor determines the enlargement factor of the hole current near described drain region 15, has material impact to the voltage breakdown (breakdownvoltage) of described MOS transistor and latch-up (latch-upeffect).In prior art, usually adopt the base current of the described bipolar transistor of test and collector current and obtain current gain factor beta.But, when testing described base current, needing proving installation to contact with described tagma 13, causing whole test process more complicated.
Summary of the invention
The object of the present invention is to provide a kind of characteristic present's method of parasitical bipolar transistor of the MOS transistor not needing tagma to contact.
Characteristic present's method of the parasitical bipolar transistor of MOS transistor, comprises the steps: the leakage current Id measuring described MOS transistor; Measure the gate-induced drain leakage Igidl of described MOS transistor; Measure the voltage Vds between the source electrode of described MOS transistor and drain electrode, described voltage Vds is the voltage Vce between the collector and emitter of the parasitical bipolar transistor of described MOS transistor; According to the described leakage current Id recorded and described gate-induced drain leakage Igidl, utilize Id=(1+ β) Igidl, calculate the current gain factor beta of described parasitical bipolar transistor; Generate the fitting function of the voltage Vce between the current gain factor beta of described parasitical bipolar transistor and described collector and emitter.
As preferred technique scheme, described MOS transistor is the MOS transistor of horizontal soi structure.
As preferred technique scheme, the scope of the voltage Vds between the source electrode of the described MOS transistor of measurement and drain electrode is 1.2V ~ 2.0V.
As preferred technique scheme, the test spacing of the voltage Vds between the source electrode of described MOS transistor and drain electrode is 0.1V.
As preferred technique scheme, described MOS transistor is nmos pass transistor, and described MOS transistor grid institute making alive is negative voltage.
As preferred technique scheme, described MOS transistor is PMOS transistor, and described MOS transistor grid institute making alive is positive voltage.。
Compared with prior art, method of testing of the present invention is by measuring the gate-induced drain leakage Igidl of MOS transistor, calculate the current gain factor beta of parasitical bipolar transistor in MOS transistor, thus generate the fitting function of the voltage Vce between current gain factor beta and collector and emitter, do not need the tagma contacting MOS transistor, thus simplify test process.
Accompanying drawing explanation
Fig. 1 is a kind of cross-sectional view of MOS transistor of soi structure of prior art.
Fig. 2 is the structural representation of the parasitic npn bipolar transistor of the MOS transistor shown in Fig. 1.
Fig. 3 is the process flow diagram of method of testing of the present invention.
Fig. 4 is the gate-induced drain leakage Igidl of MOS transistor and the relation schematic diagram of channel length.
Fig. 5 is the leakage current Id of MOS transistor and the relation schematic diagram of channel length.
Embodiment
Method of testing of the present invention is by measuring the gate-induced drain leakage Igidl of MOS transistor, calculate the current gain factor beta of parasitical bipolar transistor in MOS transistor, thus generate the source electrode of current gain factor beta and MOS transistor and the voltage Vds between draining, the fitting function of the voltage Vce yet namely between parasitic bipolar transistor emitter and collector, does not need the tagma contacting MOS transistor.For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
Refer to Fig. 3, Fig. 3 is the process flow diagram of method of testing of the present invention.Preferably, described MOS transistor is the MOS transistor of horizontal soi structure, and the parasitical bipolar transistor of described MOS transistor is NPN bipolar transistor.Method of testing of the present invention comprises the steps:
Measure the leakage current Id of described MOS transistor.
Measure the gate-induced drain leakage Igidl of described MOS transistor.
Measure the voltage Vds between the source electrode of described MOS transistor and drain electrode, the voltage Vce also namely between parasitic bipolar transistor emitter and collector.
According to the described leakage current Id recorded and described gate-induced drain leakage Igidl, utilize Id=(1+ β) Igidl, calculate the current gain factor beta of described parasitical bipolar transistor.
Change the voltage Vds between the source electrode of described MOS transistor and drain electrode, also the voltage Vce namely between parasitic bipolar transistor emitter and collector, and then change leakage current Id, gate-induced drain leakage Igidl and Vds of described MOS transistor, calculate the current gain factor beta corresponding with this source-drain voltage Vds.According to the principle of similitude, obtain the corresponding data of many group Vce and β.Preferably, the voltage Vds between the source electrode of the described MOS transistor of measurement and drain electrode, the voltage Vce scope also namely between parasitic bipolar transistor emitter and collector is 1.2V ~ 2.0V; Voltage Vds between the source electrode of described MOS transistor and drain electrode, the test spacing of the voltage Vce also namely between parasitic bipolar transistor emitter and collector is 0.1V.
Generate the current gain factor beta of described parasitical bipolar transistor and the source electrode of described MOS transistor and voltage Vds between draining, the fitting function between the voltage Vce also namely between parasitic bipolar transistor emitter and collector.
Concrete, the corresponding data of Vce and the β adopting said method to obtain is as shown in table 1:
| Vce(V) | 1.2 | 1.3 | 1.4 | 1.5 | 1.6 | 1.7 | 1.8 | 1.9 | 2.0 |
| β | 0.78 | 1.27 | 2.02 | 3.0 | 3.97 | 4.79 | 5.45 | 6.00 | 6.50 |
Table 1
The relation of the gate-induced drain leakage Igidl of MOS transistor and the channel length (channellength) of metal-oxide-semiconductor, as shown in Figure 4.Wherein, curve 31, curve 32 are illustrated respectively in the gate source voltage Vgs=-1V of MOS transistor, under the condition of channel width w=100 μm, when channel length is 0.13 μm, 10 μm, record the graph of relation of Igidl and Vds, as seen from the figure, when Vds is greater than 1.2V, the Igidl of long-channel MOS transistor and short channel MOS transistor is basically identical.
The relation of the leakage current Id of MOS transistor and the channel length of metal-oxide-semiconductor, as shown in Figure 5.Wherein, curve 41, curve 42, curve 43, curve 44 are illustrated respectively in the gate source voltage Vgs=-1V of MOS transistor, under the condition of channel width w=20 μm, when channel length is 20 μm, 1.2 μm, 0.5 μm, 0.18 μm, record the graph of relation of Id and Vds, as seen from the figure, under the condition that Vds is identical, Id reduces with the increase of the length of the raceway groove of MOS transistor.Therefore, the current gain factor beta of the parasitical bipolar transistor of MOS transistor reduces with the increase of channel length.
Compared with prior art, method of testing of the present invention is by measuring the gate-induced drain leakage Igidl of MOS transistor, calculate the current gain factor beta of parasitical bipolar transistor in MOS transistor, thus generate the source electrode of current gain factor beta and MOS transistor and the voltage Vds between draining, the fitting function of the voltage Vce also namely between parasitic bipolar transistor emitter and collector, do not need the tagma contacting MOS transistor, thus simplify test process, and method of testing accuracy of the present invention is high.
Many embodiments having very big difference can also be formed when without departing from the spirit and scope of the present invention.Should be appreciated that except as defined by the appended claims, the invention is not restricted to specific embodiment described in the description.
Claims (6)
1. characteristic present's method of the parasitical bipolar transistor of MOS transistor, is characterized in that, comprise the steps:
Measure the leakage current Id of described MOS transistor;
Measure the gate-induced drain leakage Igidl of described MOS transistor;
Measure the voltage Vds between the source electrode of described MOS transistor and drain electrode, described voltage Vds is the voltage Vce between the collector and emitter of the parasitical bipolar transistor of described MOS transistor;
According to the described leakage current Id recorded and described gate-induced drain leakage Igidl, utilize Id=(1+ β) Igidl, calculate the current gain factor beta of described parasitical bipolar transistor;
Generate the fitting function of the voltage Vce between the current gain factor beta of described parasitical bipolar transistor and described collector and emitter.
2. characteristic present's method of the parasitical bipolar transistor of MOS transistor according to claim 1, is characterized in that, described MOS transistor is the MOS transistor of horizontal soi structure.
3. characteristic present's method of the parasitical bipolar transistor of MOS transistor according to claim 1, is characterized in that, the scope of the voltage Vds between the source electrode of the described MOS transistor of measurement and drain electrode is 1.2V ~ 2.0V.
4. characteristic present's method of the parasitical bipolar transistor of MOS transistor according to claim 1, is characterized in that, the test spacing of the voltage Vds between the source electrode of described MOS transistor and drain electrode is 0.1V.
5. characteristic present's method of the parasitical bipolar transistor of MOS transistor according to claim 1, is characterized in that, described MOS transistor is nmos pass transistor, and described MOS transistor grid institute making alive is negative voltage.
6. characteristic present's method of the parasitical bipolar transistor of MOS transistor according to claim 1, is characterized in that, described MOS transistor is PMOS transistor, and described MOS transistor grid institute making alive is positive voltage.
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|---|---|---|---|---|
| US5900665A (en) * | 1997-04-01 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device operating at high speed with low current consumption |
| KR20030068372A (en) * | 2002-02-13 | 2003-08-21 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| CN1638127A (en) * | 2004-01-06 | 2005-07-13 | 松下电器产业株式会社 | Semiconductor integrated circuit device |
| CN1874002A (en) * | 2005-05-31 | 2006-12-06 | 敦南科技股份有限公司 | High-power semiconductor device that suppresses parasitic bipolar transistors |
| JP2009303159A (en) * | 2008-06-17 | 2009-12-24 | Sumitomo Electric Ind Ltd | Amplifier and optical module |
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| TWI431771B (en) * | 2004-10-07 | 2014-03-21 | Fairchild Semiconductor | Metal oxide semiconductor (MOS) gated power transistor with band gap design |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5900665A (en) * | 1997-04-01 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device operating at high speed with low current consumption |
| KR20030068372A (en) * | 2002-02-13 | 2003-08-21 | 미쓰비시덴키 가부시키가이샤 | Semiconductor device |
| CN1638127A (en) * | 2004-01-06 | 2005-07-13 | 松下电器产业株式会社 | Semiconductor integrated circuit device |
| CN1874002A (en) * | 2005-05-31 | 2006-12-06 | 敦南科技股份有限公司 | High-power semiconductor device that suppresses parasitic bipolar transistors |
| JP2009303159A (en) * | 2008-06-17 | 2009-12-24 | Sumitomo Electric Ind Ltd | Amplifier and optical module |
Non-Patent Citations (3)
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| SOI技术问题和BSIM3SOIv1.3模型参数特点;顾爱军 等;《电子与封装》;20071130;第7卷(第11期);第31-34，第38页 * |
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| 高压SOI PLDMOS的寄生双沟道特性分析及其改进结构;王靖琳 等;《电子器件》;20090228;第32卷(第1期);第31-34页 * |
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