CN102322875B - Visible light sensor - Google Patents

Abstract

The invention discloses a visible light sensor, which mainly solves the problem that the existing technology cannot effectively suppress infrared light, is affected by dark current and noise, and has low precision. It includes an ambient light detection circuit (1), an infrared light detection circuit (2), A current control circuit (3), an analog-to-digital conversion circuit (4), a timing control circuit (5), a reference voltage generation circuit (6), a reference current generation circuit (7) and a data storage circuit (8), and the ambient light detection circuit will The detected optical signal is converted into a current signal and the current signal converted by the infrared light detection optical signal is operated by the current control circuit, and the operation result is output to the analog-to-digital conversion circuit, and the analog-to-digital conversion circuit sends the conversion result to the data storage circuit. To the external microprocessor, the timing control circuit provides timing control signals for all circuits. The invention has two measuring ranges, can effectively suppress infrared light, eliminate dark current, filter flicker noise in artificial light sources, mainly respond to visible light, and can be applied to intelligent control of electronic products.

Description

visible light sensor

technical field

The invention belongs to the technical field of electronic devices and relates to a light sensor, which can be used in the intelligent control of portable devices such as computers, mobile phones, tablet computers and PDAs, and televisions.

Background technique

In recent years, the development of liquid crystal display (LCD) has advanced by leaps and bounds, and it plays a decisive role in the field of flat panel display. Televisions, computers, mobile phones, and tablet computers using liquid crystal display devices as display screens are widely used. LCD is a light valve display that modulates lamp or ambient light. It does not emit light itself, but only reflects or transmits external light. Reflective LCD has low brightness and poor color gamut, and is used in low-power applications, such as watches, etc. It is not suitable for the display of TVs, computers, mobile phones and tablet computers, and transmissive LCDs are generally used. When using LCD as a display in these occasions, it is necessary to add a backlight to the LCD to enhance the contrast.

Ambient light levels have a great influence on the performance of display devices used to modulate light sources. While many of the above applications are portable devices that need to be powered by batteries, usually the main power consumption object of these devices is the display device. It has been recognized that the operation of the display can be modified by using the information of the light sensor to improve the performance of the display. When the ambient light is high, increase the brightness of the backlight to increase the contrast, and when the ambient light is low, reduce the brightness of the backlight.

Ambient light sources mainly contain visible light and infrared light. There are great differences in the optical power density of the two in different environmental light sources, and only visible light has an impact on people watching the display. It is hoped to obtain a light sensor that is similar to the human eye mainly responding to visible light. However, the existing ambient light sensor does not suppress the infrared light in the ambient light to a high degree; the photodiode PD contained in the ambient light sensor has the problem of generating dark current by itself, and the dark current is greatly affected by the voltage. Indistinguishable from photocurrent, which will lead to inaccurate results; in artificial light sources, the ambient light sensor is also affected by 50Hz/60Hz flicker noise, the above factors affect the response accuracy of the ambient light sensor to visible light, thus affecting the ambient light sensor in The effect of adjusting the brightness of the backlight in the LCD backlight system reduces the effect of people watching the LCD in different ambient light.

Contents of the invention

The purpose of the present invention is to avoid the deficiencies of the above-mentioned technologies, and provide a visible light sensor to effectively suppress infrared light, eliminate the dark current generated by the photodiode itself, suppress the 50Hz/60Hz flicker noise in the artificial light source, and improve the linearity and precision. , to approximate the response of the human eye to visible light in different ambient light.

To achieve the above object, the present invention includes:

The ambient light detection circuit 1 is used to convert the detected ambient light into a current signal I ₂ and output it to the current control circuit 3;

The infrared light detection circuit 2 is used to convert the detected infrared light of the ambient light into a current signal I ₁ and output it to the current control circuit 3;

The current control circuit 3 is mainly composed of a current mirror circuit 31, a first switching circuit 32, a first voltage stabilizing circuit 33, a second switching circuit 34 and a second voltage stabilizing circuit 35; the first voltage stabilizing circuit 33 adopts a three-layer common source The common gate structure outputs the two input currents _I2 and _I1 to the first switch circuit 32; the second switch circuit 34 receives the current IREF output by the reference current generating circuit 7, conducts time-sharing through the switch, and outputs two currents I ₆ and _{I 7} are given to the first switch circuit 32 and the second voltage stabilizing circuit ₃₅ respectively; The mirror output current _I3 of the mirror tube is fed back to the first switch circuit 32, and the input current _I1 and the mirror current _I3 are time-division converted in the two mirror tubes to reduce the error caused by the asymmetry of the mirror tubes _MP1 and _MP2 ; The first switch circuit 32 is connected with the fifth control signal Mode_set output by the timing control circuit 5, when Mode_set is high, the current I ₃ is output to the second voltage stabilizing circuit 35, when Mode_set is low, the first switch circuit 32 The input three-way current I ₂ , I ₃ and I ₆ are subtracted to obtain the sampling/quantization current I _{0 and} output to the analog-to-digital conversion circuit 4; the second voltage stabilizing circuit 35 is used for the first switch circuit 32 and the second The switching circuit 34 performs voltage stabilization and reduces switching noise;

The analog-to-digital conversion circuit 4 is used to convert the current signal _I0 input by the current control circuit 3 into a digital signal and output it to the data storage circuit 8, and is connected with the second output signal CTRL2 of the timing control circuit 5, so that the sensor can operate in two ranges Switch between, while suppressing 50Hz/60Hz flicker noise generated by artificial light sources;

The quasi-voltage generation circuit 6 is connected with the voltage input terminals of the current control circuit 3 and the analog-to-digital conversion circuit 4 respectively to provide a reference voltage;

A reference current generating circuit 7 is connected to the current input terminal of the current control circuit 3 to provide a reference current;

The timing control circuit 5 is respectively connected to the input ends of the current control circuit 3 , the analog-to-digital conversion circuit 4 and the data storage circuit 8 to provide them with different timing control signals.

The data storage circuit 8 is used for storing the digital signal input by the analog-to-digital conversion circuit 4 and outputting it to an external circuit at the same time.

Compared with the prior art, the present invention has the following advantages:

(1) The present invention adopts the voltage stabilizing circuit of three-layer cascode structure in the electric current control circuit, has shielded the impact of upper stratum circuit voltage change on ambient light detection circuit and infrared light detection circuit voltage, to the photodiode in its circuit Provide approximately the same voltage, so that the dark current generated by itself is the same, and the two equal dark currents are subtracted by the current control circuit, thereby eliminating the dark current.

(2) In the current control circuit of the present invention, the current mirror image is under timing control, and in the first half cycle and the second half cycle, the mirror current is converted in two mirror tubes, integrated in one cycle by the analog-to-digital conversion circuit, and eliminated The error caused by the asymmetry of the mirror tube in the actual circuit improves the accuracy.

(3) The analog-to-digital conversion circuit in the present invention can suppress the 50Hz/60Hz flicker noise generated by artificial light sources, and realize the response degree of human eyes to visible light in different ambient lights.

Description of drawings

Fig. 1 is a structural block diagram of a visible light sensor of the present invention;

Fig. 2 is a block diagram of a current control circuit in the present invention;

Fig. 3 is ambient light detection circuit of the present invention, infrared light detection circuit and electric current control circuit schematic diagram;

Fig. 4 is a schematic diagram of the analog-to-digital conversion circuit in the present invention.

Detailed ways

The present invention will be described in further detail below with reference to the accompanying drawings.

Referring to Fig. 1, the visible light sensor of the present invention mainly includes an ambient light detection circuit 1, an infrared light detection circuit 2, a current control circuit 3, an analog-to-digital conversion circuit 4, a timing control circuit 5, a reference voltage generation circuit 6, and a reference current generation circuit 7. Data storage circuit 8, wherein the ambient light detection circuit 1 is composed of 64 photodiode units coated with green filter coating, and the ambient light detection circuit 1 converts the detected ambient light, that is, visible light and infrared light, into current signals and outputs them to current The control circuit 3; the infrared light detection circuit 2 is composed of 64 photodiode units coated with green and red filter coatings. The infrared light detection circuit 2 converts the detected infrared light into a current signal and outputs it to the current control circuit 3. The current control circuit 3 calculates the current output by the ambient light detection circuit 1 and the infrared light detection circuit 2, outputs the sampling/quantization current to the analog-to-digital conversion circuit 4, and the analog-to-digital conversion circuit 4 digitizes it, and simultaneously inputs the digitized result to Data storage circuit 8. The twelve-bit output data of the data storage circuit 8 is sent to the external microprocessor, and the twelve-bit output data of the data storage circuit 8 can indicate the illuminance in the current ambient light, that is, the intensity of the visible light. Intelligent control of electronic products provides data basis. The reference voltage generation circuit 6 is respectively connected to the voltage input ends of the current control circuit 3 and the analog-to-digital conversion circuit 4 to provide reference voltages thereto. The reference current generating circuit 7 is connected to the current input end of the current control circuit 3 to provide it with a reference current. The timing control circuit 5 outputs ten digital signals, which are respectively connected to the input terminals of the current control circuit 3 , the analog-to-digital conversion circuit 4 and the data storage circuit 8 to provide them with different timing control signals.

Each unit circuit structure of the present invention is described in detail below:

With reference to Fig. 2, current control circuit 3 of the present invention comprises current mirror circuit 31, the first switch circuit 32, the first voltage stabilizing circuit 33, the second switching circuit 34, the second voltage stabilizing circuit 35 forms; The first voltage stabilizing circuit The voltage input terminal and the current current input terminal of 32 are respectively connected with the second reference voltage VREF2 of the reference voltage generating circuit 6, the output current _I2 of the ambient light detection circuit 1, and the output current _I1 of the infrared light detection circuit 2, and connect these The output currents _I2 and _I1 of the two detection circuits are output to the first switch circuit, and at the same time shield the upper circuit from the influence of the voltage of the ambient light detection circuit 1 and the infrared light detection circuit 2, so that the ambient light detection circuit 1 and the infrared light detection circuit The circuit 2 has the same voltage, so that the dark current generated by the photodiode itself in the two detection circuits is the same; The output control signal Enable of the digital conversion circuit 4 is connected to output currents I ₆ and I ₇ respectively, wherein IREF=50nA; the output current I ₆ is connected to the first switch circuit 10, and the output current I ₇ is connected to the second voltage stabilizing circuit 35 The voltage input terminal and the timing control input terminal of the current mirror circuit 31 are respectively connected with the first reference voltage VREF1 of the reference voltage generating circuit 6 and the sixth control terminal CLK2 of the timing control circuit 5, and the first switch circuit 32 will receive the current I ₁ is output to the current mirror circuit 31, and the current mirror circuit 31 feeds back the output current _I3 to the first switch circuit ₃₂ after the input current I1 is mirrored by two mirror tubes, and the input current _I1 and the mirror current _I3 are in two Time-sharing conversion in the mirror tube, to reduce the error caused by the asymmetry of the mirror tubes _MP1 and _MP2 ; the timing control terminal of the first switch circuit 32 is connected with the fifth control signal Mode_set of the timing control circuit 5, when the Mode_set is When 1, the first switch circuit 32 outputs the current I ₃ to the second voltage stabilizing circuit 35. When the Mode_set is 0, the first switch circuit 32 performs calculations on the input current signals I ₂ , I ₃ and I ₆ . , when the output control signal Enable of the analog-to-digital conversion circuit 4 is 0, I ₆ =0, I ₅ =IREF, the first switch circuit 32 outputs the current I ₀ =I ₂ -I ₃ , and at this time I ₀ is the sampling current , when Enable is 1, I ₆ =IREF, I ₅ =0, the first switch circuit 32 output current I ₀ =I ₆ -(I ₂ -I ₃ )=IREF-(I ₂ -I ₃ ), at this time I ₀ is the quantized current, and the first switch circuit 32 connects the output current I ₀ to the analog-to-digital conversion circuit 4; Voltage VREF2, output current I ₃ of the first switch circuit 32, output current I of the second switch circuit 12 ₇ to stabilize the voltage of the first switch circuit 32 and the second switch circuit 34 and reduce switching noise.

The structure of described current mirror circuit 31 is as shown in Figure 3, and it comprises the first inverter INV1, the second inverter INV2 and PMOS transistors _MP1 ～ _MP8 ; The input terminal of the first inverter INV1 and timing control The sixth control signal CLK2 of the circuit 5 is connected; the input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1; the PMOS transistors _MP1 and _MP2 are mirrored transistors, and their source terminals are connected to the power supply VDD, The gate terminal is connected to the drain terminal of the PMOS transistor _MP7 , and the drain terminal is respectively connected to the source terminals of the PMOS transistors _MP3 - _MP4 and PMOS transistors _MP5 - _MP6 ; the source terminals of the PMOS transistors _MP7 and _MP8 are respectively connected to the _MP3 , _MP4 are connected to the drain terminals of MP4 and _MP5 , the gate terminal thereof is connected to the first reference voltage VREF1 of the reference voltage generating circuit 6, and the drain terminals are respectively connected to the input _{current I2} and the output current _I3 ; the PMOS transistor M _P3 ~M _P6 constitutes a current selection circuit, the input terminal and output terminal of the second inverter INV2 are respectively connected to the gate terminals of _MP3 , _MP5 and _MP4 , _MP6 , when the signal CLK2 is 0, the current I ₁ is controlled by M _P2 is mirrored to _MP1 , and vice versa, _MP1 is mirrored to _MP2 to reduce the error caused by the asymmetry of mirror tubes _MP1 and _MP2 .

The structure of the first switch circuit 32 is shown in Figure 3, including a third inverter INV3, a fourth inverter INV4, PMOS transistors _MP9 - _MP10 and NMOS transistors _MN1 - _MN2 ; the third inverter The input terminal of the inverter INV3 is connected to the fifth control signal Mode set of the timing control circuit 5, the input terminal of the fourth inverter INV4 is connected to the output terminal of the third inverter INV3; the source terminals of the PMOS transistors _MP9 and _MP10 It is connected to the input current _I3 , the gate terminal is connected to the output terminal and input of the fourth inverter INV4, the drain terminals of the PMOS transistor M _P9 and the NMOS transistor M _N2 are connected to the input current _I6 and the output current _I0 , and the PMOS transistor M The drain end of _P10 outputs the current I ₃ ; the drain end of the NMOS transistor M _N1 is connected to the drain end of _MP7 in the current mirror circuit 31, and the gate ends of the NMOS transistors M _N1 and M _N2 are connected to the output end of the third inverter INV3 , the source terminals of NMOS transistors M _N1 and M _N2 respectively receive two input currents I ₁ and I ₂ , when Mode_set is 1, output current I ₃ to the second voltage stabilizing circuit 35, when Mode_set is 0, the first The switch circuit 32 performs operations on the input current signals I ₁ , I ₂ and I ₃ , and when the output control signal Enable of the analog-to-digital conversion circuit 4 is 0, I ₆ =0, I ₅ =IREF, and the output current I ₀ =I ₂ -I ₃ , at this time I ₀ is the sampling current, when Enable is 1, I ₆ =IREF, I ₅ =0, output current I ₀ =I ₆ -(I ₂ -I ₃ )=IREF-(I ₂ -I ₃ ), at this time, I ₀ is the quantized current, and the output current I ₀ is connected to the analog-to-digital conversion circuit 4 .

The structure of the first voltage stabilizing circuit 33 is shown in FIG. 3 , comprising six NMOS transistors _MN3 - _MN8 ; the gate terminals of the _MN3 - _MN8 are connected to the second reference voltage VREF2 of the reference voltage generation circuit 6 , the drain of M _N3 is connected to the source of M _N1 in the first switch circuit 32, the source of M _N3 is connected to the drain of M _{N5, the source of M N5 is} connected to the drain of M _N7 , the source of M _N7 The end receives the output current _I1 of the infrared light detection circuit 2, and _MN3 , _MN5 and _MN7 form a three-layer cascode structure; the drain end of _MN4 is connected to the source end of MN2 in the first switch circuit 32, and _MN4 The source terminal of _N4 is connected to the drain terminal of _MN6 , the source terminal of _MN6 is connected to the drain terminal of _MN8 , the source terminal of _MN8 receives the output current _I2 of the ambient light detection circuit 1, _MN4 , _MN6 and _MN8 Constitute a three-layer cascode structure; this circuit can shield the upper circuit from the influence of the voltage of the ambient light detection circuit 1 and the infrared light detection circuit 2, so that the ambient light detection circuit 1 and the infrared light detection circuit 2 have the same voltage, so that The dark currents generated by the photodiodes themselves in the two detection circuits are the same.

The structure of described second switch circuit 34 is as shown in Figure 3, and it is made up of flip-flop RS and two PMOS transistors M _P11 ～ _MP12 ; The two complementary output signals generated by it are respectively connected to the gates of the two PMOS transistors, the sources of the two PMOS transistors are connected to the reference current IREF of the reference current generating circuit 7, and the drains of the two PMOS transistors The poles output currents I ₆ and I ₇ respectively; when Enable is 1, I ₆ =IREF, I ₇ =0; when Enable is 0, I ₆ =0, I ₇ =IREF.

The structure of the second voltage stabilizing circuit 35 is as shown in Figure 3, and is made up of the first transconductance operational amplifier OTA1, and its output end is short-circuited with the inverting input end, and the non-inverting input end is connected with the first output of the reference voltage generating circuit 6. Two reference voltages VREF2 are connected.

With reference to Fig. 4, analog-to-digital conversion circuit 4 of the present invention comprises integration circuit 14, comparator COMP, flip-flop DFF, data selector, counter, data register 12bit_REG and AND gate AND; Current control circuit 3 output current I ₀ , and integral The input terminal of the circuit 14 is connected, and the integrating circuit 14 converts the current signal into a voltage signal V', which is connected with the non-inverting input terminal of the comparator COMP, and the comparator COMP connects the voltage signal V' with its inverting input terminal. The third reference voltage VREF3 is compared, and the output 1/0 level signal is connected to the data input terminal D of the flip-flop DFF; the clock input terminal clk and the clearing terminal clr of the flip-flop DFF are respectively connected to the fourth output of the timing control circuit 5 The terminal CLK is connected to the seventh output terminal CLR, and its output terminal is connected to the input terminal ADC_OUT of the counter; the two input terminals of the AND gate AND are respectively connected to the output terminal Q of the flip-flop DFF and the first output terminal CRTL1 of the timing control circuit 5 connected, the output control signal Enable; the clock input terminal clk and the clearing terminal clr of the counter are respectively connected with the fourth output signal CLK and the seventh output signal CLR of the timing control circuit 5, which generates twelve-bit data signals [11:0] , the data signal is input to the data register 12bit_REG; the clock input terminal clk and the clearing terminal clr of the data register 12bit_REG are respectively connected with the ninth output signal REG_CLK and the tenth output signal REG_CLR of the timing control circuit 5, and output twelve-bit data signals [11 :0] to the data storage circuit 8. The integrating circuit 14 includes three NMOS transistors _MN9 - _MN11 , four capacitors _C1 - _C4 and a second transconductance operational amplifier OTA2, wherein the non-inverting input terminal of the second transconductance operational amplifier OTA2 is connected to the second reference voltage VREF2 is connected, both ends of the eighth NMOS transistor _MN10 and the second capacitor _C2 are respectively connected to the inverting input terminal and output terminal of the second transconductance operational amplifier OTA2, and the first capacitor _C1 and the ninth NMOS transistor _MN9 are connected in series Connect with the inverting input terminal and the output terminal of the second transconductance operational amplifier OTA2 respectively after the second; The output terminal of the second transconductance operational amplifier OTA2 is respectively connected with one end of the third capacitor _C3 and the fourth capacitor _C4 , the third capacitor The other end _{of C3} is connected to the ground, and the _fourth capacitor _C4 is connected to the ground through the eleventh NMOS transistor _MN11 ; The three output signals are connected to RESET, the gate terminal of the ninth NMOS transistor _MN9 is connected to the second output signal CTRL2 of the timing control circuit 5, when the RESET signal is 1, the tenth NMOS transistor _MN10 is turned on, and the input terminal of the integrator 14 Short circuit with the output terminal is in the reset state, otherwise, the integrator 14 is in the normal integration working state, when CTRL2 is 1, the ninth NMOS transistor M _N9 is turned on, and the second capacitor C ₁ and the third capacitor C ₂ are connected in parallel as an integral The integrating capacitor of the integrator 14, the sensor works in a large range of 0-2000 lux at this time, on the contrary, the second capacitor _C2 is used as the integrating capacitor of the integrator 14, and the sensor works in a small range of 0-125 lux.

Effect of the present invention can be further illustrated by following simulation:

Simulation 1: When the present invention is at T=25°C, VDD=3V, and works in a small range of 0-125lux, the illuminances of incandescent lamps and cold fluorescent lamps are 10lux, 20lux, 50lux, 100lux and 125lux respectively In the case of , the digital output of the present invention is respectively simulated, and the results are shown in Table 1.

Table 1 Simulation results of working in a small range of 0 to 125lux

10lux 20lux 50lux 100lux 125lux Approximate slope incandescent lamp 324 648 1621 3242 4052 32.4 Cool fluorescent lamp 325 651 1629 3242 4074 32.5 ideal value 328 651 1629 3276 4095 32.7

It can be seen from Table 1 that when the sensor works in a small range of 0 to 125lux, the ratio of the response difference to the ideal value is about 0.5% when the illumination is the same in these two different light sources. Compared with the ideal value, Accuracy is 99.1% and 99.4%, respectively;

Simulation 2: When the present invention is at T=25°C, VDD=3V, and works in a large range of 0-2000lux, the illuminances of incandescent lamps and cold fluorescent lamps are respectively 200lux, 300lux, 500lux, 1000lux and 2000lux In the case of , the digital output of the present invention is respectively simulated, and the results are shown in Table 2.

Table 2 Simulation results of working in a large range of 0 to 2000lux

200lux 300lux 500lux 1000lux 2000lux Approximate slope incandescent lamp 405 608 1013 2026 4053 2.026 Cool fluorescent lamp 407 611 1013 2037 4074 2.037 ideal value 409 614 1023 2047 4095 2.048

It can be seen from Table 2 that when the sensor works in a large range of 0 to 2000 lux, the ratio of the response difference to the ideal value is about 0.5% when the illumination is the same in these two different light sources. Compared with the ideal value, Accuracy is 98.9% and 99.5%, respectively;

Since the proportion of infrared light in these two light sources is very different, it can be seen from the simulation results that the present invention can effectively suppress infrared light, thereby mainly responding to visible light, and has high linearity and precision at the same time.

The above is only a best example of the present invention, and does not constitute any limitation to the present invention. Obviously, under the conception of the present invention, various changes and improvements can be made to the circuit, but these are all included in the protection of the present invention.

Claims (10)

1. visible light sensor, it is characterized in that: it comprises:

Ambient light detection circuit (1) is used for converting the surround lighting that detects to current signal I ₂, output to current control circuit (3);

Infrared light detection circuit (2), the infrared light that is used for the surround lighting that will detect converts current signal I to ₁, output to current control circuit (3);

Current control circuit (3), mainly by current mirror circuit (31), the first on-off circuit (32), the first mu balanced circuit (33), second switch circuit (34) and the second mu balanced circuit (35) form; The first mu balanced circuit (33) adopts three layers of cascode structure, with the two-way electric current I of input ₂And I ₁Output to the first on-off circuit (32); Second switch circuit (34) receives the electric current I REF of reference current generating circuit (7) output, by switch timesharing conducting, and output two-way electric current I ₆And I ₇Give respectively the first on-off circuit (32) and the second mu balanced circuit (35); The first on-off circuit (32) is with the electric current I that receives ₁Output to current mirror circuit (31), current mirror circuit (31) is with input current I ₁By two mirror image pipe mirror image output current I ₃Feed back to the first on-off circuit (32), input current I ₁With image current I ₃Timesharing conversion in two mirror image pipes is to reduce because of mirror image pipe M _P1And M _P2Asymmetric caused error; The 5th control signal Mode_set of the first on-off circuit (32) and sequential control circuit (5) output is connected, as Mode_set when being high, with electric current I ₃Output to the second mu balanced circuit (35), when Mode_set when low, the first on-off circuit (32) is to three tunnel electric current I of input ₂, I ₃And I ₆Carry out subtraction, obtain sampling/quantification electric current I _O=I ₆-(I ₂-I ₃) and this sample quantization electric current I o is exported to analog to digital conversion circuit (4); The second mu balanced circuit (35) is used for the first on-off circuit (32) and second switch circuit (34) are carried out voltage stabilizing and reduce switching noise;

Analog to digital conversion circuit (4) is used for the current signal I with current control circuit (3) output _OConvert digital signal to and export to data storage circuitry (8), be connected with the second output signal CTRL2 of sequential control circuit (5), this sensor is changed between two ranges, suppress simultaneously the 50Hz/60Hz flicker noise that artificial light source produces;

Reference voltage generating circuit (6) is connected 4 with current control circuit (3) with analog to digital conversion circuit respectively) voltage input end be connected, for it provides reference voltage;

Reference current generating circuit (7) is connected with the current input terminal of current control circuit (3), for it provides reference current;

Sequential control circuit (5), with current control circuit (3), analog to digital conversion circuit (4) is connected 8 with data storage circuitry respectively) input end connect, for they provide different timing control signals;

Data storage circuitry (8) is used for the digital signal of analog to digital conversion circuit (4) output is stored, and exports to simultaneously external circuit.

2. visible light sensor according to claim 1 is characterized in that current mirror circuit (31) by the first phase inverter INV1, the second phase inverter INV2 and eight PMOS pipe M _P1～M _P8Form; The input end of the first phase inverter INV1 is connected with the 6th control signal CLK2 of sequential control circuit (5); The input end of the second phase inverter INV2 is connected with the output terminal of the first phase inverter INV1; PMOS manages M _P1And M _P2Be the mirror image pipe, its source is connected with power vd D, grid end and PMOS pipe M _P7Drain terminal connect, drain terminal respectively with PMOS pipe M _P3～M _P4With PMOS pipe M _P5～M _P6Source connect; PMOS manages M _P7And M _P8Source respectively with M _P3, M _P6And M _P4, M _P5Drain terminal connect, its grid end is connected with the first reference voltage V REF1 of reference voltage generating circuit (6), drain terminal respectively with input current I ₁With output current I ₃Connect; PMOS manages M _P3～M _P6Consist of current selecting circuit, the output terminal of the second phase inverter INV2 and input end respectively with M _P3, M _P5And M _P4, M _P6The grid end connect, when signal CLK2 is 0, electric current I ₁By M _P2Be mirrored to M _P1Otherwise,, by M _P1Be mirrored to M _P2, to reduce because of mirror image pipe M _P1And M _P2Asymmetric caused error.

3. visible light sensor according to claim 2 is characterized in that the first on-off circuit (32) by the 3rd phase inverter INV3, the 4th phase inverter INV4, and PMOS manages M _P9～M _P10With NMOS pipe M _N1～M _N2Form; The input end of the 3rd phase inverter INV3 is connected with the 5th control signal Mode_set of sequential control circuit (5), and the input end of the 4th phase inverter INV4 is connected with the output terminal of the 3rd phase inverter INV3; PMOS manages M _P9And M _P10Source and input current I ₃Connect, the grid end is connected with input end with the output terminal of the 4th phase inverter INV4 respectively, and PMOS manages M _P9With NMOS pipe M _N2Drain terminal and input current I ₆With output current I _OConnect, PMOS manages M _P10Drain terminal output current I ₃NMOS manages M _N1Drain terminal and the M in the current mirror circuit (31) _P7Drain terminal connects, NMOSM _N1And M _N2The grid end be connected with the output terminal of the 3rd phase inverter INV3, NMOS manages M _N1And M _N2Source receive respectively two-way input current I ₁And I ₂

4. visible light sensor according to claim 3 is characterized in that the first mu balanced circuit (33) is by six NMOS pipe M _N3～M _N8Form; This M _N3～M _N8The grid end be connected M with the second reference voltage V REF2 of reference voltage generating circuit (6) _N3Drain terminal and the M in the first on-off circuit (32) _N1Source connects, M _N3Source and M _N5Drain terminal connect M _N5Source and M _N7Drain terminal connect M _N7Source receive the output current I of infrared light detection circuit (2) ₁, M _N3, M _N5And M _N7Consist of three layers of cascode structure, play pressure stabilization function; M _N4Drain terminal and the first on-off circuit (32) in M _N2Source connect M _N4Source and M _N6Drain terminal connect M _N6Source and M _N8Drain terminal connect M _N8The output current I of source reception environment optical detection circuit (1) ₂, M _N4, M _N6And M _N8Consist of three layers of cascode structure, play pressure stabilization function.

5. visible light sensor according to claim 1 is characterized in that second switch circuit (34) is by trigger RS and two PMOS pipe M _P11～M _P12Form; The input end of trigger RS quantizes enable signal Enable with the output control signal of analog to digital conversion circuit (4) and is connected, two complementary output signals that it produces are connected with the grid of two PMOS pipes respectively, the source electrode of two PMOS pipes all is connected with the reference current IREF of reference current generating circuit (7), and the drain electrode of two PMOS pipes is output current I respectively ₆And I ₇

6. visible light sensor according to claim 1, it is characterized in that the second mu balanced circuit (35) is comprised of the first operational transconductance amplifier OTA1, its output terminal and inverting input short circuit, normal phase input end is connected with the second reference voltage V REF2 of reference voltage generating circuit (6) output.

7. visible light sensor according to claim 1 is characterized in that analog to digital conversion circuit (4) mainly by integrating circuit (14), comparator C OMP, trigger DFF, counter, data register 12bit_REG and form with door AND; The output current I of the input end of integrating circuit (14) and current control circuit (3) _OConnect, convert current signal to normal phase input end that voltage signal V ' is connected to comparator C OMP; The inverting input of comparator C OMP is connected with the 3rd reference voltage V REF3 of reference voltage generating circuit (6) output, and output terminal is connected with the data input pin D of trigger DFF; Be connected 5 with the output terminal Q of trigger DFF with sequential control circuit respectively with two input ends of door AND) the first output terminal CRTL1 be connected, the output control signal quantizes enable signal; The input end ADC_OUT of counter is connected with the output terminal of trigger DFF, and output terminal is connected with the input end of data register 12bit_REG; Data register 12bit_REG exports data to data memory circuit (8).

8. visible light sensor according to claim 7 is characterized in that integrating circuit (14) is mainly by three NMOS pipe M _N9-M _N11, four capacitor C ₁-C ₄Form with the second operational transconductance amplifier OTA2, the normal phase input end of the second operational transconductance amplifier OTA2 is connected with the second reference voltage V REF2, and the tenth NMOS manages M _N10With the second capacitor C ₂Two ends be connected the first capacitor C with output terminal with the inverting input of the second operational transconductance amplifier OTA2 respectively ₁With the 9th NMOS pipe M _N9Be connected with output terminal with the inverting input of the second operational transconductance amplifier OTA2 respectively after the series connection; The output terminal of the second operational transconductance amplifier OTA2 respectively with the 3rd capacitor C ₃With the 4th capacitor C ₄An end connect the 3rd capacitor C ₃The other end be connected to ground, the 4th capacitor C ₄By the 11 NMOS pipe M _N11Be connected to ground.

9. visible light sensor according to claim 1, it is characterized in that ambient light detection circuit (1) is made of 64 photodiode units that scribble green filtering plated film, this circuit can be that visible light and infrared light are converted to current signal with the surround lighting that detects.

10. visible light sensor according to claim 1, it is characterized in that infrared light detection circuit (2) is made of 64 photodiode units that scribble green and red filtering plated film, this circuit can be converted to current signal with the infrared light in the surround lighting that detects.

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