CN102316177A - Address resolution method, system thereof and address resolution device - Google Patents
Address resolution method, system thereof and address resolution device Download PDFInfo
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- CN102316177A CN102316177A CN201110277798A CN201110277798A CN102316177A CN 102316177 A CN102316177 A CN 102316177A CN 201110277798 A CN201110277798 A CN 201110277798A CN 201110277798 A CN201110277798 A CN 201110277798A CN 102316177 A CN102316177 A CN 102316177A
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Abstract
The invention provides an address resolution method, a system thereof and an address resolution device. The method comprises the following steps: switching an access address in an access frame sent by a management device into an address of each physical layer chip, and correspondingly sending the switched access address to each physical layer chip through a channel corresponding to each physical layer chip; resolving the access address, determining a physical layer chip corresponding to the access address, and sending a data segment in the access frame sent by the management device to the physical layer chip corresponding to the access address through the channel corresponding to the physical layer chip corresponding to the access address. The address resolution device comprises a switching module and a resolution module. The address resolution system comprises the management device, physical layer chips and the address resolution device. According to the invention, real-time access of a PHY chip by the management device is realized.
Description
Technical field
The present invention relates to technology, relate in particular to a kind of address resolution method, system and address resolver.
Background technology
In exchange board structure, medium access control (Media Access Control; Hereinafter to be referred as: MAC) chip and physical layer (Physical Layer; Hereinafter to be referred as: PHY) chip is two important component parts, and MAC mainly accomplishes message forwarding exchange work, and the PHY chip is mainly accomplished the conversion of physical interface signal.Usually pass through serial management interface (Serial Management Interface at equipment; Hereinafter to be referred as: SMI) the PHY chip is managed, SMI is for comprising a management data clock (Management Data Clock; Hereinafter to be referred as: MDC) with management data input and output (Management Data Input Output; Hereinafter to be referred as: synchronous serial interface MDIO).Usually the SMI interface that adopts the MAC chip to carry is connected with the corresponding SMI interface of PHY, comes directly visit PHY chip by the MAC chip.When needs were managed a plurality of PHY simultaneously, all PHY all were connected on the same SMI interface of same MAC, because each PHY has an own address, then MAC visits different PHY according to different address.But because the address of standard protocol specifies PHY has only 5, i.e. 32 PHY of multipotency management of SMI interface, and the address of each PHY under the same SMI interface can not conflict mutually, otherwise can't visit, thereby bring great design limit.In addition; Along with the function of MAC chip is progressively powerful, some MAC chip possesses the mechanism of automatic visit PHY, to reduce Software Operation; But this function is the fixing PHY address of restriction usually; Be the PHY address setting that the PHY that connects under the SMI interface need meet MAC chip defined, can't freely dispose the PHY address under the SMI interface, thereby limit the extensibility of module and the flexibility of design.
In order to address the above problem; Common way is on the SMI interface, to increase the one-level interface change-over device in the prior art; Tension management equipment is visited this interface change-over device earlier, the PHY chip of hanging down by the interface change-over device visit again, and promptly interface change-over device arrives Data Receiving local earlier; Carry out corresponding address switchover again, data are sent to the PHY chip.
Increased the address switchover process in the prior art, made tension management equipment can't visit the PHY chip in real time, and tension management equipment need be made corresponding sequential adaptation.
Summary of the invention
The present invention provides a kind of address resolution method, system and address resolver, realizes the real time access of management equipment to the PHY chip, and management equipment need not to carry out extra sequential and adapt to, and improves the apparatus upgrading scalability, has higher flexibility.
The present invention provides a kind of address resolution method, comprising:
Reference address in the visit frame that management equipment is sent switches to the address of each physical chip respectively, and the reference address after will switching is issued each physical chip accordingly through the passage of each physical chip correspondence;
Resolve said reference address; Confirm and said reference address corresponding physical layer chip; Data segment in the visit frame that said management equipment is sent sends to and said reference address corresponding physical layer chip through said and the corresponding passage of reference address corresponding physical layer chip.
The present invention provides a kind of address resolver, comprising:
Handover module, the reference address of the visit frame that is used for management equipment is sent switches to the address of each physical chip respectively, and the reference address after will switching is issued each physical chip accordingly through the passage of each physical chip correspondence;
Parsing module; Be used to resolve said reference address; Confirm and said reference address corresponding physical layer chip; Data segment in the visit frame that said management equipment is sent sends to and said reference address corresponding physical layer chip through said and the corresponding passage of reference address corresponding physical layer chip.
The present invention provides a kind of address resolution system, comprises management equipment, physical chip and above-mentioned address resolver.
Address resolution method provided by the invention, system and address resolver; Switch to the address of each PHY chip respectively through the reference address in the visit frame that management equipment is sent; And the reference address after will switching is issued each physical chip accordingly; According to the corresponding relation between the address of reference address and PHY chip, the data segment in the visit frame of management equipment transmission is sent to the PHY chip corresponding with this reference address; Present embodiment is resolved reference address wherein when receiving the visit frame in real time; And to corresponding PHY transmission; Realized the real time access of management equipment to the PHY chip; And management equipment need not to carry out extra sequential and adapts to, and has improved the apparatus upgrading scalability, has higher flexibility.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do one to the accompanying drawing of required use in embodiment or the description of the Prior Art below introduces simply; Obviously, the accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the flow chart of address resolution method embodiment one of the present invention;
Fig. 2 is the flow chart of address resolution method embodiment two of the present invention;
Fig. 3 is the circuit module structural representation of SMI address resolver among the address resolution method embodiment two of the present invention;
Fig. 4 changes sketch map for the signal among the address resolution method embodiment two of the present invention;
Fig. 5 is the structural representation of address resolver embodiment one of the present invention;
Fig. 6 is the structural representation of address resolver embodiment two of the present invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer; To combine the accompanying drawing in the embodiment of the invention below; Technical scheme in the embodiment of the invention is carried out clear, intactly description; Obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Fig. 1 is the flow chart of address resolution method embodiment one of the present invention, and as shown in Figure 1, present embodiment provides a kind of address resolution method, can specifically comprise the steps:
Step 101, the reference address in the visit frame that management equipment is sent switches to the address of each physical chip respectively, and the reference address after will switching is issued each physical chip accordingly through the passage of each physical chip correspondence.
Management equipment in the present embodiment can be specially the MAC chip; Present embodiment is provided with a SMI address resolver between management equipment and PHY chip; The SMI address resolver is provided with a plurality of ports; Each port connects the PHY chip of a correspondence respectively, and corresponding here implication is meant that there is corresponding relation in this PHY chip with the address of the port of the SMI address resolver that links to each other.Management equipment realizes the visit to the PHY chip through the address resolution of SMI address resolver; During PHY chip of management apparatus access; Send the visit frame to the SMI address resolver, the reference address in the visit frame is the address of the corresponding port of SMI address resolver.The SMI address resolver is in the visit frame that receiving management equipment sends; Should visit frame transmits to the PHY chip; The SMI address resolver is discerned and is analyzed each bit of visit frame; When receiving the reference address of visit in the frame, this reference address is switched to the address of each PHY respectively, and the reference address after will switching is issued each PHY chip accordingly through the passage of each PHY chip correspondence.In the present embodiment; A visit frame can be made up of wherein frame head, reference address and data segment; Before the SMI address resolver received the reference address in the visit frame, the frame head in the visit frame was transferred to each PHY chip respectively through the passage corresponding with each PHY chip.
Particularly, the above-mentioned steps in the present embodiment 101 can specifically comprise the steps: the frame head generation output control signal according to the visit frame of management equipment transmission; The reference address in the said visit frame is switched to the address of physical chip respectively according to said output control signal.
More specifically; The step that each bit of the above-mentioned said visit frame that sends according to management equipment generates the output control signal can specifically comprise the steps: the visit frame that the rising edge with the management data clock comes synchronous receiving management equipment to send; When a continuous N bit of frame head all meets the preceding M position in the preset frame structure in recognizing said visit frame, will export control signal and switch to second bit value by first bit value; When recognizing when transmitting afterwards the N position reference address of said M bit of accomplishing frame head in the said visit frame, will export control signal and switch to said first bit value by said second bit value; Wherein, said M is the number of bits of preset frame head, and said N is the number of bits of preset reference address.
More specifically; The above-mentioned said step that reference address in the said visit frame is switched to the address of physical chip respectively according to said output control signal can specifically comprise the steps: when said management data clock trailing edge occurs and changes, to generate and the synchronous address switchover signal of said output control signal; When the trailing edge variation did not appear in said management data clock, it was constant to keep said address switchover signal; When said address switchover signal is said first bit value, the frame head in the visit frame that transfer management equipment sends in each passage; When said address switchover signal is switched to said second bit value by said first bit value, the reference address of the visit frame that transmits in each passage is switched to the address with said passage corresponding physical layer chip respectively; When said address switchover signal is switched to said first bit value by said second bit value, trigger the operation of the data segment in the visit frame that transfer management equipment sends in each passage.
After the SMI address resolver receives the reference address in the visit frame; The SMI address resolver is according to the corresponding relation between the address of preset reference address and PHY chip; And combine this reference address; Resolve said reference address, confirm and said reference address corresponding physical layer chip, this corresponding relation is the corresponding relation between the address of address and PHY chip of port of SMI address resolver.The SMI address resolver sends to this PHY chip through the control passage corresponding with this PHY chip with the data segment in the follow-up visit frame that receives in real time, and the data segment that no longer will visit in the frame sends to other PHY chips, realizes the accurate transmission of data.
Particularly; Corresponding relation between the reference address in the visit frame that above-mentioned steps 102 in the present embodiment can specifically comprise the steps: to send according to management equipment and the address of reference address and physical chip; Confirm and said reference address corresponding physical layer chip, and calculated address is resolved gating signal; According to said address resolution gating signal continue conducting said with the corresponding passage of reference address corresponding physical layer chip; Close the corresponding passage of other physical chips, the passage of the data segment in the said visit frame through correspondence sent to said and reference address corresponding physical layer chip.
Present embodiment provides a kind of address resolution method; Switch to the address of each PHY chip respectively through the reference address in the visit frame that management equipment is sent; And the reference address after will switching is issued each physical chip accordingly; According to the corresponding relation between the address of reference address and PHY chip, the data segment in the visit frame of management equipment transmission is sent to the PHY chip corresponding with this reference address; Present embodiment is resolved reference address wherein when receiving the visit frame in real time; And to corresponding PHY transmission; Realized the real time access of management equipment to the PHY chip; And management equipment need not to carry out extra sequential and adapts to, and has improved the apparatus upgrading scalability, has higher flexibility.
Fig. 2 is the flow chart of address resolution method embodiment two of the present invention, and as shown in Figure 2, present embodiment provides a kind of address resolution method, can specifically comprise the steps:
Fig. 3 is the circuit module structural representation of SMI address resolver among the address resolution method embodiment two of the present invention, and as shown in Figure 3, the SMI address resolver in the present embodiment can specifically adopt the concrete structure among the figure.SMI address resolver in the present embodiment can comprise a plurality of ports; Correspondingly connect a plurality of PHY chips, suppose that here the SMI address resolver in the present embodiment comprises 3 ports, each port links to each other with 1 PHY chip respectively; Be PHYl, PHY2, PHY3, the address of PHY is 5 bit address.Correspondingly, this SMI address resolver can comprise frame identification module, d type flip flop, 3 gates, 35 bit shift register and 3 switches.In the present embodiment, the signal that management equipment is transmitted to the SMI address resolver through the bus that links to each other with the SMI address resolver simultaneously comprises MDC and MDIO, MDC for control each circuit module work clock (promptly～CLK).
In the present embodiment, the visit frame can be made up of frame head, reference address and data segment successively, and this step can be specially the frame head generation output control signal of frame identification module according to the visit frame of management equipment transmission.Particularly, management equipment is sent MDIO to the SMI address resolver, and the frame identification module obtains the visit frame with the MDIO that the rising edge of～CLK comes synchronous receiving management equipment to send.Frame identification module in the present embodiment is mainly used in identification SMI interface standard visit frame; Abbreviate the visit frame in the present embodiment as; The frame structure of this visit frame is the structure of normalized definition, and the visit of all SMI all adopts two kinds of frame structures as shown in table 1 below to read and write:
The frame structure of table 1 visit frame
In last table 1,32 of field " 32-Bit PRE " expressions leading, the frame beginning flag that field " 2-Bit Start of Frame " expression is 2; The command code that field " 2-Bit OpCode " expression is 2; The PHY address that field " 5-BitPHY Addr " expression is 5, the register address that field " 5-BitReg Addr " expression is 5, the state switching mark position that field " 2-BitTA " expression is 2; Be used to indicate the switching of current read-write state; The data field that field " 16-BitData Field " expression is 16, field " Idle " expression is idle, promptly representes to have no communication data on the SMI bus.Wherein, Field " 32-Bit pRE ", " 2-Bit Start of Frame " and " 2-Bit OpCode " can form the frame head in the visit frame; Field " 5-Bit PHY Addr " can be the reference address in the visit frame, and field " 5-Bit Reg Addr ", " 2-Bit TA ", " 16-Bit Data Field " and " Idle " can form the data segment in the visit frame.
In this step, when the frame identification module recognizes that the continuous N bit of frame head all meets the preceding M position of presetting in the frame structure in the visit frame, the frame identification module will be exported control signal and switch to second bit value by first bit value.The preset frame structure here can be specially the frame structure shown in the table 1, and M is the number of bits of preset frame head, and M is specially 36 here, and first bit value in the present embodiment is specially 0, the second bit value and is specially 1.Promptly recognize continuous 36 when meeting preceding 36 of any one frame structure in the table 1 of from the visit frame that management equipment receives frame head when the frame identification module; Then expression has received a standard SMI frame at this moment; And the PHY address that next will transmit 5 is used to visit corresponding PHY chip; Then will to export control signal be 1 by 0 to the frame identification module, and promptly the OC among Fig. 3 is output as 1.
When the frame identification module recognizes the N bit address section after transmitting said M bit accomplishing frame head in the said visit frame, will export control signal and switch to said first bit value by said second bit value.Wherein, N is the number of bits of preset address field, because the hypothesis reference address is 5 bit address in the present embodiment, then the N here can be specially 5.When the frame identification module recognizes 5 reference address after finishing receiving 36 bits of visiting frame head in the frame; Show that 5 PHY addresses that next MDIO transmits have transmitted completion; Then the frame identification module will be exported control signal and switch to 0 by 1, and promptly the OC among Fig. 3 is output as 0.
This step can be specially d type flip flop according to output control signal calculated address switching signal, and as can be seen from Figure 3, the output control signal is from the input D input of d type flip flop, and the address switchover signal is from the output Q output of d type flip flop.The frame identification module will be exported control signal and output in the d type flip flop, import synchronizing clock signals～CLK in the d type flip flop simultaneously.When d type flip flop input～when being changed by 1 to 0 trailing edge appearred in CLK, the output valve of the output Q of d type flip flop equaled the input value of input D; When d type flip flop input～CLK does not have trailing edge when changing, the output valve of the output Q of d type flip flop keeps initial value constant.Can know that from above-mentioned steps the frame identification module is before recognizing address field, the value of output control signal is 0, and when recognizing address field, the value of output control signal is 1, is recognizing after address field finished receiving, and the output control signal is 0; Then correspondingly, the output valve of the output Q of d type flip flop, promptly the address switchover signal is 1 from receiving the address field of visiting the frame in the time period that this address field finishes receiving also, all the other then are 0 constantly.
As can beappreciated from fig. 3, the output valve of the output Q of d type flip flop is input in 3 gates and 35 bit shift register simultaneously.This step can be specially the address switchover signal of gate according to its input s input, controls the visit frame that transmits in each passage, the reference address in the visit frame in each passage is switched to the address of the PHY chip corresponding with passage respectively.In the present embodiment; The visit frame of management equipment transmission can be transferred to a path of 3 gates through 3 passages respectively; Gate also is provided with the another one path; This path links to each other with the output of corresponding 5 bit shift register, and then gate can be exported outside the road direction in the signal that the different time section is selected to receive in two paths according to the address switching signal.Particularly, when the address switchover signal of the input s of gate input was 1, the path that this gate is selected was directly connected to output c for input b; When the address switchover signal of the input s of gate input was 0, the path that this gate is selected was directly connected to output c for input a.
As can beappreciated from fig. 3, the address switchover signal of d type flip flop output also is input among the input en of 5 bit shift register simultaneously.Preserve different original preset values in 5 bit shift register respectively, this original preset value is the address of the corresponding PHY chip of this 5 bit shift register.Wherein, The address of PHY1, PHY2, PHY3 chip is respectively 0x1,0x2,0x3; 5 bit shift register, 1,5 bit shift register, 2,5 bit shift register 3 are corresponding with PHY1, PHY2, PHY3 chip respectively, and then the original preset value of 5 bit shift register, 1,5 bit shift register, 2,5 bit shift register 3 is respectively 00001,00010,00011.In 5 bit shift register, import～trailing edge that CLK takes place by 1 to 0 changes; And its input en's is input as at 1 o'clock at this moment; The address switchover signal that is d type flip flop output is 1 o'clock; The inside of 5 bit shift register will be carried out by gt the original preset value, and the lowest order of current intrinsic value is outputed on the output out of 5 bit shift register.For example, the original preset value of supposing 5 bit shift register is 00101, and this moment, the output valve of its output out was 1; When～when a trailing edge took place CLK, the intrinsic value of 5 bit shift register became 00010, and this moment, the output valve of its output out was 0; When～when a trailing edge took place CLK again, intrinsic value became 00001, and this moment, the output valve of its output out was 1; By that analogy, when 4 trailing edge saltus steps take place in～CLK, then in the output out of 5 bit shift register 5 bit data of the inner original preset value of output respectively from low to high.When the input en of 5 bit shift register be input as 0 the time, its intrinsic value reverts to the original preset value, and no matter～whether CLK change, intrinsic value all remains unchanged, its output out is output as the lowest order of 5 original preset values.
In the present embodiment, each gate selects to connect a-c path or b-c path under the control of the address switchover signal of d type flip flop output; When connecting the a-c path, the original bit information that comprises in the visit frame will be continued to transmit to the PHY of correspondence chip through gate; When connecting the b-c path, the bit information of the original preset value of preserving in 5 bit shift register (i.e. the address of the PHY chip of correspondence) is transmitted to the PHY of correspondence chip.In the present embodiment; Begin to receive in the process that finishes at the reference address from receive the visit frame to each bit of visit address; The address switchover signal of d type flip flop output is 1; Then control each gate and connect b-c path, then visit the address that reference address in the frame is switched to the corresponding PHY chip of each gate respectively.
Step 204 according to the corresponding relation between the address of the reference address in the visit frame of management equipment transmission and reference address and physical chip, confirm and said reference address corresponding physical layer chip, and calculated address is resolved gating signal.
In the present embodiment; When the frame identification module recognizes the transmission of accomplishing reference address in the visit frame; And after through gate the reference address of the visit frame that transmits in each passage being switched to the address of each corresponding PHY chip respectively, the frame identification module also further calculated address resolve gating signal.The frame identification module is confirmed and said reference address corresponding physical layer chip specifically according to the corresponding relation between the address of the reference address in the visit frame of management equipment transmission and reference address and PHY chip, and calculated address is resolved gating signal.In the present embodiment, the corresponding relation between the address of reference address and PHY chip can preestablish, and is kept in the frame identification module.The corresponding relation here can be specially, and reference address 0x4,0x5,0x6 address 0x1,0x2, the 0x3 with the PHY chip respectively are corresponding one by one.Behind the reference address of frame identification module in identifying the visit frame; Just can get access to the address of the PHY chip corresponding with it according to this reference address; Then the frame identification module just can calculated address be resolved gating signal 1,2,3 according to corresponding result, and address resolution gating signal 1,2,3 is respectively applied for the transmission of the data of visit frame in follow-up each passage of control.For example; When identifying reference address and be 0x4, the address that the frame identification module gets access to its corresponding PHY chip is 0x1, and is promptly corresponding with PHY1; Then generation is 1 with the corresponding address resolution gating signal 1 of PHY1, and all the other PHY2, PHY3 corresponding address are resolved gating signal 2,3 and be 0.
This step is that the frame identification module is according to the address resolution gating signal that generates; Control the data segment in the visit frame that transmits in each passage; Promptly continue conducting said with the corresponding passage of reference address corresponding physical layer chip; Close the corresponding passage of other physical chips, send to physical chip with the passage of data segment through correspondence that will visit in the frame.Particularly, as shown in Figure 3, the frame identification module can specifically output to the address resolution gating signal that generates in the switch on each passage, controls the conducting or the disconnection of each switch through this address resolution gating signal.When address parsing gating signal is 1, keep this switch to continue conducting, when address parsing gating signal is 0, this switch is switched to off-state.For example, when the address gating signal 1,2,3 that generates is respectively 1,0,0, then make switch 1 continue conducting, switch 2,3 is all switched to off-state.Thus, the data segment transmission that then can realize visiting in the frame arrives PHY1, and can not be transferred to PHY2, PHY3.In the present embodiment; After the frame identification module is identifying reference address, continue to receive 23 MDC clocks after, frame identification module calculated address is resolved gating signal 1,2,3 and is 1; Make switch 1,2,3 whole conductings, expression accomplish the process of a frame identification.
To combine the running of whole SMI address resolver below, be example with address 0x4 to the address resolution of 0x1, and the running mechanism of whole SMI address resolver is described down.Promptly when MAC visit PHY address 0x4, actual transmissions is transformed to the frame of visit 0x1 in real time to the visit frame of PHY1, and sends to PHY1; Be used for mutual between MAC and the PHY1, and, for all the other PHY chips; With not receiving correct visit frame, thereby MAC is not responded.
Fig. 4 changes sketch map for the signal among the address resolution method embodiment two of the present invention; Clock signal as shown in Figure 4, that MDC (MAC) sends from MAC, the data-signal that MDIO (MAC) expression is sent from MAC; OC representes the output control signal of frame identification module output; Out1 representes the signal of 5 bit shift register, 1 output, and c1 representes the signal of gate 1 output, the signal that MDIO (PHY1) expression PHY1 receives; The signal that MDIO (PHY2) expression PHY2 receives, the signal that MDIO (PHY3) expression PHY3 receives.As shown in Figure 4, when MAC when read operation is initiated in PHY address 00100, will send MDIO (MAC) signal among Fig. 4, and the frame identification module will detect the data of MDIO at each MDC (MAC) rising edge.When the frame identification module detects last bit manipulation sign indicating number; With sending OC is 1 signal (when the rising edge of command code last 0 corresponding MDC take place like the OC among Fig. 40 to 1 saltus step); And when ensuing MDC trailing edge; This OC signal of d type flip flop locking, and the address switchover signal in the output map.At this moment, under the control of address switchover signal,, and the path of gate 1 switched in the output of 5 bit shift register 1 the displacement output function of opening 5 bit shift register.Like Fig. 4, when the address switching signal is 1, every MDC trailing edge, then actual PHY address (00001) order that will preset of out1 is sent, i.e. behind the proper operation sign indicating number that c1 output MAC sends, will switch and export 00001, and this is representing address resolving.Meanwhile, after completion was sent in the PHY address, the frame identification module was resolved gating signal with OPADD, off switch 2 and 3.PHY2 and PHY3 will not receive follow-up SMI frame this moment; So it can not give a response this visit, like MDIO among Fig. 4 (PHY1) and MDIO (PHY2), before completion is sent in the PHY address; To export proper data according to said process; And after completion was sent in the address, then interface was closed, and two MDIO signals will become high-impedance state.And after send to accomplish last position, PHY address, the address switchover signal also will become 0 by 1, and the output c1 of gate 1 is connected on the MDIO of MAC, make MAC can continue to accomplish the register read to PHY1.
Present embodiment provides a kind of address resolution method; Switch to the address of each PHY chip respectively through the reference address in the visit frame that management equipment is sent; And the reference address after will switching is issued each physical chip accordingly; According to the corresponding relation between the address of reference address and PHY chip, the data segment in the visit frame of management equipment transmission is sent to the PHY chip corresponding with this reference address; Present embodiment is resolved reference address wherein when receiving the visit frame in real time; And to corresponding PHY transmission; Realized the real time access of management equipment to the PHY chip; And management equipment need not to carry out extra sequential and adapts to, and has improved the apparatus upgrading scalability, has higher flexibility.Present embodiment carries out real time parsing to reference address; Therefore can not cause the variation of SMI interface accessing sequential, compatible traditional SMI interface index analysis principle fully can not destroy the SMI interface sequence index of original chip; Have extremely strong real-time, portable strong.After management equipment was sent the visit frame, corresponding PHY chip can receive this visit frame in real time, need not to wait for that the SMI address resolver finishes receiving.In addition, present embodiment uses easy hardware circuit just can realize, cost is low, realization is easy, reliability is low, need not to increase extra sequential adjustment; Can freely dispose it and resolve corresponding relation, be very easy to expanded application, improve the flexibility of design.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be accomplished through the relevant hardware of program command; Aforesaid program can be stored in the computer read/write memory medium; This program the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
Fig. 5 is the structural representation of address resolver embodiment one of the present invention, and as shown in Figure 5, present embodiment provides a kind of address resolver, can specifically carry out each step among the said method embodiment one, repeats no more here.The address resolver that present embodiment provides can be specially the SMI address resolver, can specifically comprise handover module 501 and parsing module 502.Wherein, parsing module 501 is used for the reference address of the visit frame of management equipment transmission is switched to respectively the address of each physical chip, and the reference address after will switching is issued each physical chip accordingly through the corresponding passage of each physical chip.Sending module 502 is used to resolve said reference address; Confirm and said reference address corresponding physical layer chip; Data segment in the visit frame that said management equipment is sent sends to and said reference address corresponding physical layer chip through said and the corresponding passage of reference address corresponding physical layer chip.Wherein, the handover module 501 in the present embodiment can specifically adopt frame identification module, d type flip flop, gate and 5 bit shift register among Fig. 3 to realize, parsing module 502 can specifically adopt frame identification module and the switch among Fig. 3 to realize.
Fig. 6 is the structural representation of address resolver embodiment two of the present invention, and as shown in Figure 6, present embodiment provides a kind of address resolver, can specifically carry out each step among the said method embodiment two, repeats no more here.The address resolver that present embodiment provides can be specially the SMI address resolver among Fig. 3, and on basis shown in Figure 5, handover module 501 can specifically comprise the first frame recognin module 511 and switching submodule 521.Wherein, the first frame recognin module 511 is used for the frame head generation output control signal according to the visit frame of management equipment transmission.Switching submodule 521 is used for according to said output control signal the reference address of said visit frame being switched to the address of physical chip respectively, and the reference address after will switching is issued each physical chip accordingly through the corresponding passage of each physical chip.Wherein, this first frame recognin module 511 can be included in the frame identification module shown in Figure 3, and switching submodule 521 can specifically adopt d type flip flop, gate and 5 bit shift register among Fig. 3 to realize.
Further, the first frame recognin module 511 in the present embodiment can specifically comprise first recognition unit 5111 and second recognition unit 5112.Wherein, First recognition unit 5111 is used for coming with the rising edge of management data clock the visit frame of synchronous receiving management equipment transmission; When a continuous N bit of frame head all meets the preceding M position in the preset frame structure in recognizing said visit frame, will export control signal and switch to second bit value by first bit value.Second recognition unit 5112 is used for when the reference address address, N position that recognizes after transmitting said M bit accomplishing said visit frame frame head, will exporting control signal and switching to said first bit value by said second bit value.Wherein, said M is the number of bits of preset frame head, and said N is the number of bits of preset reference address.
Further, the switching submodule in the present embodiment 521 can specifically comprise trigger element 5211 and gating unit 5212.Wherein, trigger element 5211 is used for when the trailing edge variation appears in said management data clock, generating and the synchronous address switchover signal of said output control signal; When the trailing edge variation did not appear in said management data clock, it was constant to keep said address switchover signal.Gating unit 5212 is used for when said address switchover signal is said first bit value, the frame head in the visit frame that transfer management equipment sends in each passage; When said address switchover signal is switched to said second bit value by said first bit value, the reference address of the visit frame that transmits in each passage is switched to the address with said passage corresponding physical layer chip respectively; When said address switchover signal is switched to said first bit value by said second bit value; The operation of the data segment in the triggering visit frame that transfer management equipment sends in each passage, and the reference address after will switching is issued each physical chip accordingly through the corresponding passage of each physical chip.Wherein, Trigger element 5211 can be specially the d type flip flop shown in above-mentioned Fig. 3; Gating unit 5212 can be specially the gate shown in above-mentioned Fig. 3, and gating unit 5212 is specifically accomplished the address under the shift register shown in Fig. 3 auxiliary parsing is switched.
Particularly, parsing module 502 can specifically comprise the second frame recognin module 512 and passage control submodule 522.Wherein, The second frame recognin module 512 is used for according to the corresponding relation between the address of the reference address of the visit frame of management equipment transmission and reference address and physical chip; Confirm and said reference address corresponding physical layer chip, and calculated address is resolved gating signal.Passage control submodule 522 be used for according to said address resolution gating signal continue conducting said with the corresponding passage of reference address corresponding physical layer chip; Close the corresponding passage of other physical chips, the passage of the data segment in the said visit frame through correspondence sent to said and reference address corresponding physical layer chip.Wherein, this second frame recognin module 512 also can be included in the frame identification module shown in Figure 3, and passage control submodule 522 can specifically adopt the switch among Fig. 3 to realize.
Present embodiment provides a kind of address resolver; Switch to the address of each PHY chip respectively through the reference address in the visit frame that management equipment is sent; And the reference address after will switching is issued each physical chip accordingly; According to the corresponding relation between the address of reference address and PHY chip, the data segment in the visit frame of management equipment transmission is sent to the PHY chip corresponding with this reference address; Present embodiment is resolved reference address wherein when receiving the visit frame in real time; And to corresponding PHY transmission; Realized the real time access of management equipment to the PHY chip; And management equipment need not to carry out extra sequential and adapts to, and has improved the apparatus upgrading scalability, has higher flexibility.
Present embodiment also provides a kind of address resolution system, can specifically comprise management equipment, physical chip and above-mentioned Fig. 5 or address resolver shown in Figure 6.
What should explain at last is: above embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although with reference to previous embodiment the present invention has been carried out detailed explanation, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the spirit and the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.
Claims (11)
1. an address resolution method is characterized in that, comprising:
Reference address in the visit frame that management equipment is sent switches to the address of each physical chip respectively, and the reference address after will switching is issued each physical chip accordingly through the passage of each physical chip correspondence;
Resolve said reference address; Confirm and said reference address corresponding physical layer chip; Data segment in the visit frame that said management equipment is sent sends to and said reference address corresponding physical layer chip through said and the corresponding passage of reference address corresponding physical layer chip.
2. method according to claim 1 is characterized in that, the address that the reference address in the said visit frame that management equipment is sent switches to each physical chip respectively comprises:
The frame head of the visit frame that sends according to management equipment generates the output control signal;
The reference address in the said visit frame is switched to the address of physical chip respectively according to said output control signal.
3. method according to claim 2 is characterized in that, the frame head of the said visit frame that sends according to management equipment generates the output control signal and comprises:
Come the visit frame of synchronous receiving management equipment transmission with the rising edge of management data clock; When a continuous N bit of frame head all meets the preceding M position in the preset frame structure in recognizing said visit frame, will export control signal and switch to second bit value by first bit value;
When recognizing when transmitting afterwards the N position reference address of said M bit of accomplishing frame head in the said visit frame, will export control signal and switch to said first bit value by said second bit value;
Wherein, said M is the number of bits of preset frame head, and said N is the number of bits of preset reference address.
4. method according to claim 3 is characterized in that, saidly according to said output control signal the address that the reference address in the said visit frame switches to physical chip is respectively comprised:
When the trailing edge variation appears in said management data clock, generate and the synchronous address switchover signal of said output control signal;
When the trailing edge variation did not appear in said management data clock, it was constant to keep said address switchover signal;
When said address switchover signal is said first bit value, the frame head in the visit frame that transfer management equipment sends in each passage;
When said address switchover signal is switched to said second bit value by said first bit value, the reference address of the visit frame that transmits in each passage is switched to the address with said passage corresponding physical layer chip respectively;
When said address switchover signal is switched to said first bit value by said second bit value, trigger the operation of the data segment in the visit frame that transfer management equipment sends in each passage.
5. according to each described method among the claim 1-4; It is characterized in that; The said reference address of said parsing; Confirm and said reference address corresponding physical layer chip that the data segment in the visit frame that said management equipment is sent is through said and the corresponding passage of reference address corresponding physical layer chip, send to said reference address corresponding physical layer chip and comprise:
According to the corresponding relation between the address of the reference address in the visit frame of management equipment transmission and reference address and physical chip, confirm and said reference address corresponding physical layer chip, and calculated address is resolved gating signal;
According to said address resolution gating signal continue conducting said with the corresponding passage of reference address corresponding physical layer chip; Close the corresponding passage of other physical chips, the data segment in the said visit frame is sent to said and reference address corresponding physical layer chip.
6. an address resolver is characterized in that, comprising:
Handover module, the reference address of the visit frame that is used for management equipment is sent switches the address of analysing to each physical chip respectively, and the reference address after will switching is issued each physical chip accordingly through the passage of each physical chip correspondence;
Parsing module; Be used to resolve said reference address; Confirm and said reference address corresponding physical layer chip; Data segment in the visit frame that said management equipment is sent sends to and said reference address corresponding physical layer chip through said and the corresponding passage of reference address corresponding physical layer chip.
7. address resolver according to claim 6 is characterized in that, said handover module comprises:
The first frame recognin module is used for the frame head generation output control signal according to the visit frame of management equipment transmission;
Switching submodule is used for according to said output control signal the reference address of said visit frame being switched to the address of physical chip respectively, and the reference address after will switching is issued each physical chip accordingly through the corresponding passage of each physical chip.
8. address resolver according to claim 7 is characterized in that, the said first frame recognin module comprises:
First recognition unit; Be used for coming the visit frame of synchronous receiving management equipment transmission with the rising edge of management data clock; When a continuous N bit of frame head all meets the preceding M position in the preset frame structure in recognizing said visit frame, will export control signal and switch to second bit value by first bit value;
Second recognition unit is used for will exporting control signal and switching to said first bit value by said second bit value when recognizing when transmitting afterwards the N position reference address of said M bit of accomplishing said visit frame frame head;
Wherein, said M is the number of bits of preset frame head, and said N is the number of bits of preset reference address.
9. address resolver according to claim 8 is characterized in that, said switching submodule comprises:
Trigger element is used for when the trailing edge variation appears in said management data clock, generating and the synchronous address switchover signal of said output control signal; When the trailing edge variation did not appear in said management data clock, it was constant to keep said address switchover signal;
Gating unit is used for when said address switchover signal is said first bit value frame head in the visit frame that transfer management equipment sends in each passage; When said address switchover signal is switched to said second bit value by said first bit value, the reference address of the visit frame that transmits in each passage is switched to the address with said passage corresponding physical layer chip respectively; When said address switchover signal is switched to said first bit value by said second bit value; Data segment in the visit frame that triggering transfer management equipment in each passage sends, and the operation of issuing each physical chip accordingly of the reference address after will switching through the passage of each physical chip correspondence.
10. according to each described address resolver among the claim 6-9, it is characterized in that said parsing module comprises:
The second frame recognin module; Corresponding relation between the reference address of the visit frame that is used for sending and the address of reference address and physical chip according to management equipment; Confirm and said reference address corresponding physical layer chip, and calculated address is resolved gating signal;
Passage control submodule; Be used for according to said address resolution gating signal continue conducting said with the corresponding passage of reference address corresponding physical layer chip; Close the corresponding passage of other physical chips, the passage of the data segment in the said visit frame through correspondence sent to said and reference address corresponding physical layer chip.
11. an address resolution system is characterized in that, comprises each described address resolver among management equipment, physical chip and the claim 6-10.
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| CN102316177B (en) | 2014-08-27 |
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