CN102315384B - Phase change random access memory and bottom electrode and making method thereof - Google Patents
Phase change random access memory and bottom electrode and making method thereof Download PDFInfo
- Publication number
- CN102315384B CN102315384B CN201010223482.9A CN201010223482A CN102315384B CN 102315384 B CN102315384 B CN 102315384B CN 201010223482 A CN201010223482 A CN 201010223482A CN 102315384 B CN102315384 B CN 102315384B
- Authority
- CN
- China
- Prior art keywords
- layer
- electrode
- semiconductor substrate
- manufacture method
- bottom electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 claims description 50
- 239000004065 semiconductor Substances 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 45
- 238000004519 manufacturing process Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 18
- 238000001020 plasma etching Methods 0.000 claims description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 239000003595 mist Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 106
- 230000008859 change Effects 0.000 description 32
- 238000003860 storage Methods 0.000 description 24
- 230000007704 transition Effects 0.000 description 24
- 239000007789 gas Substances 0.000 description 11
- 235000019593 adhesiveness Nutrition 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 210000004027 cell Anatomy 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 Co for example Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 210000002421 cell wall Anatomy 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012782 phase change material Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention relates to a phase change random access memory and a bottom electrode and a making method thereof. The making method for the bottom electrode comprises the following steps of: providing a semiconductor substrate; forming a casting mould layer with cylindrical patterns on the surface of the semiconductor substrate; forming a ring cylindrical side-wall electrode on an external vertical surface of the casting mould layer; and forming an insulating side wall on the external surface of the side-wall electrode. The bottom electrode formed by the invention has a small contact area with a phase change layer, and can be prevented from being separated from the semiconductor substrate during making of the phase change random access memory.
Description
Technical field
The present invention relates to semiconductor memory, particularly phase transition storage (PCRAM, Phase changeRAM), bottom electrode and manufacture method thereof.
Background technology
Phase transition storage is as a kind of emerging nonvolatile storage technologies, in all many-sides such as read or write speed, read-write number of times, data hold time, cellar area, many-valued realizations, flash memory FLASH is had to larger superiority, become the focus of current non-volatile memory technology research.The continuous progress of phase change memory technology makes it to become one of the strongest competitor of the following non-volatile memory technology mainstream product in the market.
In phase transition storage, can be by heat-treating having recorded the phase change layer of data, and change the value of memory.The phase-change material that forms phase change layer can enter due to the heating effect of applied electric current crystalline state or noncrystalline state.When phase change layer is during in crystalline state, the resistance of PCRAM is lower, and now memory assignment is " 0 ".When phase change layer is during in noncrystalline state, the resistance of PCRAM is higher, and now memory assignment is " 1 ".Therefore, PCRAM utilizes the nonvolatile memory that carrys out writing/reading data when the resistance difference of phase change layer during in crystalline state or noncrystalline state.
Fig. 1 provides existing a kind of phase change memory structure, comprises the phase change layer 30 between bottom electrode 10, top electrodes 20 and bottom electrode 10 and top electrodes 20.Wherein the crystalline state transition process of phase change layer 30 needs higher temperature, generally use 10 pairs of phase change layers 30 of bottom electrode to heat, and top electrodes 20 only plays interconnection effect.Bottom electrode 10 will directly affect the read-write speed of phase transition storage to the heating effect quality of phase change layer 30.In order to obtain good heating effect, phase transition storage generally adopts large-drive-current, therefore its write-operation current will reach 1mA left and right, however drive current can not unrestrictedly rise, large-drive-current can cause the small-sized difficulty of peripheral drive circuit and logical device.
Also have a kind of method that improves heating effect to be, dwindle the contact area that bottom electrode 10 and phase change layer 30 form ohmic contact, improve contact resistance.US Patent No. 7323357 provides the manufacture method of existing a kind of bottom electrode of phase change memory, and as shown in Figures 2 to 6, its basic step is as follows:
As shown in Figure 2, first on the surface of Semiconductor substrate 100, form successively bottom electrode layer 101, hard mask layer 102; Then described in etching, hard mask layer 102 until expose bottom electrode layer 101, forms groove.
As shown in Figure 3, adopt conventional sidewall forming processes, on the cell wall of cylindrical groove, form the hard mask sidewalls 103 of an annular.
As shown in Figure 4, etching is removed hard mask layer 102, then take described hard mask sidewalls 103 as mask etching bottom electrode layer 101 until expose Semiconductor substrate, forms structure as shown in Figure 5.
As shown in Figure 6, remove hard mask sidewalls 103 and form required bottom electrode 10.Fig. 7 is the perspective view of described bottom electrode 10.
In above-mentioned technique, the bottom electrode 10 of formation is annulated column type structure, and the thickness of post jamb is the thickness of described hard mask sidewalls 103, therefore can, by adjusting the formation technique of hard mask sidewalls 103, the thickness of column of bottom electrode 10 be adjusted.The phase transition storage that the above-mentioned bottom electrode 10 of take is made as basis, bottom electrode 10 is ring section with the contact-making surface of phase change layer, therefore can significantly reduce described contact area.
Yet there are the following problems for existing technique: in existing annulated column type bottom electrode 10, its bottom is similarly ring section with the contact-making surface of Semiconductor substrate, and contact area is also less.And the material of bottom electrode 10 is generally metal or metallic compound, the material of Semiconductor substrate is silicon or silicon compound, and both adhesivenesses are poor.If contact area is too small between bottom electrode 10 and Semiconductor substrate, will cause in making the process of phase transition storage, bottom electrode 10 comes off from the surface of Semiconductor substrate, and affects subsequent technique.
Summary of the invention
The problem that the present invention solves is to provide a kind of phase change memory structure, bottom electrode and preparation method thereof, and described bottom electrode and phase change layer have less contact area, and can avoid coming off from Semiconductor substrate.
The manufacture method of a kind of bottom electrode provided by the invention, comprising: Semiconductor substrate is provided, forms the mold layer with cylindricality figure at described semiconductor substrate surface; In the tapered outer surface of described mold layer, form the side-wall electrode of central column; At the outer surface of described side-wall electrode, form the supporting side walls of insulation.
Optionally, form after described insulating supporting sidewall, also comprise the step of removing mold layer.The material of described mold layer comprises silicon dioxide, amorphous carbon and silicon nitride.The height of described cylindricality mold layer is 800～1200
diameter is 40～100nm.
The side-wall electrode concrete steps of described formation central column comprise:
At the outer surface of described mold layer and the surface of Semiconductor substrate, form electrode layer; Electrode layer described in employing plasma etching industrial etching, retains the part that described electrode layer is positioned at mold layer tapered outer surface, as side-wall electrode.
Optionally, the material of described electrode layer is Co, Ni, W, AL, Cu, Ti, the compound of a kind of or its combination and above-mentioned each metal in Ta.Preferably, the material of described electrode layer is TiN or TaN, adopts a kind of formation in chemical vapour deposition (CVD), physical vapour deposition (PVD) or atomic deposition, and deposit thickness is 20～40
the parameter of described plasma etching industrial comprises: gas pressure intensity 2～10mTorr, and radio-frequency power 500W～1200W, bias power 100W～200W, etching gas is Cl
2and BCl
3, flow-rate ratio is 1: 1～2: 1.
The supporting side walls concrete steps of described formation insulation comprise:
Outer surface, the top surface of mold layer and the surface of Semiconductor substrate at described side-wall electrode form insulating medium layer; Insulating medium layer described in employing plasma etching industrial etching, retains the part that described insulating medium layer is positioned at side-wall electrode outer surface, as supporting side walls.
Optionally, the material of described insulating medium layer is silicon dioxide, silicon nitride or its combination.Described insulating medium layer adopts chemical vapour deposition (CVD) to form, and deposit thickness is 100～200
the parameter of described plasma etching industrial can be: gas pressure intensity 2～15mTorr, and radio-frequency power 200～600w, employing etching gas is CF
4and He mist, flow-rate ratio is 1: 1～1: 3.
Based on above-mentioned manufacture method, a kind of bottom electrode provided by the invention, is formed at semiconductor substrate surface, comprising: the central column electrode that is positioned at semiconductor substrate surface; Be positioned at the supporting side walls of the insulation of described electrode outer surface.
Optionally, the material of described electrode is Co, Ni, W, AL, Cu, Ti, the compound of a kind of or its combination and above-mentioned each metal in Ta.Preferably, the material of described electrode is TiN or TaN.The height of described central column electrode is 800～1200
internal diameter is 40～100nm, and thickness is 20～40
optionally, the material of described supporting side walls is silicon dioxide, silicon nitride or its combination.The thickness of described supporting side walls is 100～200
Phase transition storage of the present invention, comprises phase-change memory cell, and described phase-change memory cell comprises: the bottom electrode of top electrodes, preceding method made and the phase change layer between bottom electrode and top electrodes.
The bottom electrode of phase transition storage provided by the present invention, the supporting side walls that comprises the side-wall electrode of ring-type and be positioned at its tapered outer surface insulation, wherein can be by regulating the thickness reduction bottom electrode of side-wall electrode and the contact area that phase change layer forms ohmic contact, supporting side walls can improve the adhesiveness of bottom electrode and Semiconductor substrate, thereby plays supporting side walls electrode and prevent the effect that whole bottom electrode comes off from Semiconductor substrate.
Accompanying drawing explanation
By the more specifically explanation of the preferred embodiments of the present invention shown in accompanying drawing, above-mentioned and other object of the present invention, Characteristics and advantages will be more clear.In accompanying drawing, parts same as the prior art have been used identical Reference numeral.Accompanying drawing not drawn on scale, focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size in layer and region.
Fig. 1 is the sectional structure chart of existing phase transition storage;
Fig. 2 to Fig. 6 is the generalized section of existing a kind of bottom electrode manufacture method;
Fig. 7 is the perspective view of bottom electrode described in Fig. 6;
Fig. 8 is bottom electrode manufacture method flow chart of the present invention;
Fig. 9 to Figure 14 is the generalized section of embodiment of the present invention bottom electrode manufacture method;
Figure 15 is the schematic perspective view of bottom electrode shown in Figure 14.
Embodiment
In the formed phase transition storage of existing manufacture method, be to reduce the contact area of bottom electrode and phase change layer, described bottom electrode is made into central column structure, and the thickness that reduces as much as possible post jamb reaches the object that reduces above-mentioned contact area.Yet in the structure of described central column, its cross section is consistent from top to down, although can reduce the contact area of bottom electrode of phase change memory and phase change layer, but also reduced the contact area of bottom electrode and Semiconductor substrate, and the poor problem of adhesiveness causing due to both material difference, to cause bottom electrode to come off from Semiconductor substrate, affect the manufacturing process of phase transition storage.The present invention arranges supporting side walls by the tapered outer surface at central column electrode, addresses the above problem.
Concrete, the invention provides a kind of manufacture method of bottom electrode.Fig. 8 is described bottom electrode manufacture method flow chart, and basic step comprises:
S101, provide Semiconductor substrate, at described semiconductor substrate surface, form the mold layer with cylindricality figure;
Wherein, described mold layer is for play the effect of mould when making bottom electrode, so its height and diameter equidimension, has determined height, internal diameter and the cross sectional shape of follow-up bottom electrode.Optionally, described mold layer can, for cylindrical, can be also gengon cylindricality etc., and be not only confined to said structure.The material of described mold layer can be selected conventional dielectric or sacrificial dielectric, such as silicon dioxide, silicon nitride, amorphous carbon etc.
S102, in the tapered outer surface of described mold layer, form side-wall electrode;
Wherein, the formation technique of described side-wall electrode can adopt plasma etching to form the method for sidewall, for example, at mold layer outer surface and semiconductor substrate surface deposition one deck electrode layer, then pass through plasma etching, the part of removing mold layer top surface and semiconductor substrate surface, final residue just forms the side-wall electrode of central column in the segment electrode layer of mold layer tapered outer surface.The thickness of described side-wall electrode has determined that bottom electrode and phase change layer in follow-up phase transition storage form the contact area of ohmic contact, should select as required.
S103, the supporting side walls insulating in the tapered outer surface formation of described side-wall electrode.
Wherein, formation technique and the aforementioned lateral wall electrode of described supporting side walls are similar, adopt plasma etching to form the method for sidewall, at side-wall electrode outer surface, mold layer top surface and semiconductor substrate surface deposition one deck insulating medium layer, by plasma etching, remove the part that is positioned at mold layer top surface and semiconductor substrate surface, the SI semi-insulation dielectric layer that residues in side-wall electrode outer surface forms supporting side walls.The thickness of described supporting side walls has determined the contact area of bottom electrode and Semiconductor substrate in follow-up phase transition storage, should select as required.The material of described supporting side walls can be selected and the good semiconducting insulation medium of Semiconductor substrate adhesiveness, such as silicon dioxide, silicon nitride etc.Further, the thickness of described supporting side walls is larger, and the adhesiveness of formed bottom electrode and Semiconductor substrate is also better.
In addition,, after forming supporting side walls, mold layer can retain or remove, and depends on whether the existence of mold layer affects the manufacturing process of follow-up phase transition storage.Those skilled in the art can look concrete condition and select.
Below in conjunction with specific embodiment, the manufacture method to bottom electrode of the present invention, is described further.Fig. 9 extremely figure is the manufacture method generalized section of embodiment of the present invention bottom electrode.
First as shown in Figure 9, provide Semiconductor substrate 200, in Semiconductor substrate 200, form mold layer 201, and graphical described mold layer 201.
Concrete, described Semiconductor substrate 200 is not limited to elemental silicon substrate, can also comprise established other semiconductor device, structure etc., and for example, in phase transition storage, described bottom electrode is formed at gate tube or other surfaces of active regions.The material of described mold layer 201 is silicon dioxide, silicon nitride or amorphous carbon, can form by chemical vapour deposition (CVD), and deposit thickness is the height of the graphical rear cylindricality mold layer 201 forming.For simplifying technique, in the present embodiment, the material selection amorphous carbon of described mold layer 201, deposit thickness is 800～1200
described mold layer 201 after graphical is cylinder, and diameter of section is 40～100nm.
As shown in figure 10, at the outer surface of described mold layer 201 and the surface of Semiconductor substrate 200, form electrode layer 202.
Concrete, the material of described electrode layer 202 can be conventional electrode material, Co for example, Ni, W, AL, Cu, Ti, the compound of a kind of or its combination and above-mentioned each metal in Ta, can form by techniques such as chemical vapour deposition (CVD), physical vapour deposition (PVD), atomic depositions, and deposit thickness has determined the thickness of the side-wall electrode that subsequent technique forms.For simplifying technique, in the present embodiment, material selection TiN or the TaN of described electrode layer 202, adopt chemical vapor deposition method to form, and thickness is 20～40
As shown in figure 11, adopt plasma etching industrial, electrode layer 202 described in etching, forms the side-wall electrode 203 of central column in the tapered outer surface of mold layer 201.
Concrete, in described plasma etching industrial, the etching gas of use should have larger selective etching ratio to electrode layer 202, and does not affect Semiconductor substrate 200 and mold layer 201.And need to avoid excessive thinning electrode layer 202 to be positioned at the part of mold layer 201 tapered outer surface, remove the part that is positioned at mold layer 201 top surface and Semiconductor substrate 200 surfaces, concrete can realize to reduce the etch rate of side direction by adjusting the component of etching gas simultaneously.In the present embodiment, the parameter of described plasma etching industrial is: gas pressure intensity 2～10mTorr, and radio-frequency power 500W～1200W, bias power 100W～200W, etching gas is Cl
2and BCl
3, flow-rate ratio is 1: 1～2: 1.Adopt above-mentioned technological parameter to carry out after plasma etching, the thickness of formed side-wall electrode 203 and primary electrode layer 202 are basically identical.
As shown in figure 12, on outer surface, the top surface of mold layer 201 and the surface of Semiconductor substrate of described side-wall electrode 203, form insulating medium layer 204.
Concrete, described insulating medium layer 204 forms supporting side walls for subsequent technique, should there is the adhesiveness good with Semiconductor substrate and robustness, therefore material can be selected semiconducting insulation medium, for example silicon dioxide, silicon nitride or its combination, can form by chemical vapour deposition (CVD), deposit thickness has determined the thickness of the supporting side walls that subsequent technique forms.According to the aforementioned principle of mentioning, the thickness of described supporting side walls is larger, and the adhesiveness of formed bottom electrode and Semiconductor substrate is also better, but excessive gauge also will take device area, therefore should select according to actual needs.In the present embodiment, described insulating medium layer 204 is silicon dioxide, and thickness is 100～200
As shown in figure 13, adopt plasma etching industrial, insulating medium layer 204 described in etching, forms the supporting side walls 205 of central column in the tapered outer surface of side-wall electrode 203.
Concrete, in this step, can adopt conventional insulative sidewall to form technique, remove the part that insulating medium layer 204 is positioned at mold layer 201 top surface and semiconductor surface, and retain the part of the tapered outer surface that is positioned at side-wall electrode 203.Described plasma etching industrial parameter can be: gas pressure intensity 2～15mTorr, and radio-frequency power 200～600w, employing etching gas is CF
4and He mist, flow-rate ratio is 1: 1～1: 3.The thickness of the thickness of formed supporting side walls 205 and former insulating medium layer 204 is basically identical.
Optionally, as shown in figure 14, remove mold layer 201.
Due to when making phase transition storage, complete after the making of bottom electrode, need to cover deposition interlayer dielectric layer in bottom electrode surface, and form phase change layer on interlayer dielectric layer surface, and make phase change layer and bottom electrode form ohmic contact.In said process, even if removed mold layer 201, in described central column side-wall electrode 203, still can fill inter-level dielectric; Therefore in these cases,, if mold layer 201 is selected material of the same race or selects and the good material of phase change layer adhesiveness with interlayer dielectric layer, do not need to remove; If mold layer 201 and interlayer dielectric layer select unlike material and and phase change layer between adhesiveness not good, will cause existing between the phase change layer of follow-up formation and bottom electrode the problem of loose contact, need to remove described mold layer 201.In addition, suppose bottom electrode of the present invention and be not only confined to phase transition storage, and being applied to make the electrode that other need small area of contact, mold layer 201 also can be looked concrete condition and retains or remove.
Concrete, remove if necessary mold 201, can, according to the material of mold layer 201, adopt selective wet etching or other technique to remove.For example, in the present embodiment, the material of described mold layer 201 is amorphous carbon, can carry out high-temperature oxydation by passing into oxygen, makes amorphous carbon be oxidized to gaseous oxygen compound, thereby removes described mold layer 201.On the one hand, the required temperature of oxidation amorphous carbon is lower is about 300～500 ℃; On the other hand, the oxide of formation (being generally carbon dioxide) is gas, after volatilization, can not leave residue.
Figure 15 is the schematic perspective view of bottom electrode shown in Figure 14.As shown in figure 15, through above-mentioned technique, the formed bottom electrode of the present invention comprises: the central column side-wall electrode 203 that is positioned at semiconductor substrate surface; Be positioned at the supporting side walls 205 of the insulation of described side-wall electrode 203 outer surfaces.By above-mentioned bottom electrode, be applied in phase transition storage, described phase transition storage comprises phase-change memory cell, described phase-change memory cell comprises bottom electrode and the phase change layer between bottom electrode and top electrodes that top electrodes, above-mentioned technique are made.
In the contact-making surface of bottom electrode of the present invention and phase change layer, the contact-making surface that only has central column side-wall electrode and a phase change layer is part that can effective constitution ohmic contact.Therefore can, by regulating the thickness of side-wall electrode, reduce the contact area of bottom electrode and phase change layer.And supporting side walls plays supporting side walls electrode, prevent in the manufacture process of phase transition storage simultaneously, bottom electrode comes off from Semiconductor substrate (being formed with the semiconductor structures such as word line, gate tube).
Though it is pointed out that the present invention take phase transition storage as example, the manufacture method of described bottom electrode, is equally applicable in other Fabrication Technology of Electrodes that need small area of contact.Those skilled in the art of the present invention, should easily apply based on technical scheme disclosed in this invention.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (11)
1. a manufacture method for bottom electrode, is characterized in that, comprising:
Semiconductor substrate is provided, at described semiconductor substrate surface, forms the mold layer with cylindricality figure;
In the tapered outer surface of described mold layer, form the side-wall electrode of central column;
The supporting side walls that forms insulation at the outer surface of described side-wall electrode, the lower surface of described supporting side walls sticks to Semiconductor substrate, to improve the adhesiveness of side-wall electrode and Semiconductor substrate;
The side-wall electrode concrete steps of described formation central column comprise:
At the outer surface of described mold layer and the surface of Semiconductor substrate, form electrode layer;
Electrode layer described in employing plasma etching industrial etching, removes the part that is positioned at semiconductor substrate surface, retains the part that described electrode layer is positioned at mold layer tapered outer surface, as side-wall electrode.
2. manufacture method as claimed in claim 1, is characterized in that, forms after described insulating supporting sidewall, also comprises the step of removing mold layer.
3. manufacture method as claimed in claim 1, is characterized in that, the material of described mold layer comprises silicon dioxide, amorphous carbon or silicon nitride.
4. manufacture method as claimed in claim 3, is characterized in that, the height of described cylindricality mold layer is 800～1200
diameter is 40～100nm.
5. manufacture method as claimed in claim 1, is characterized in that, the material of described electrode layer is Co, Ni, W, AL, Cu, Ti, the compound of a kind of or its combination and above-mentioned each metal in Ta.
6. manufacture method as claimed in claim 5, is characterized in that, the material of described electrode layer is TiN or TaN, adopts a kind of formation in chemical vapour deposition (CVD), physical vapour deposition (PVD) or atomic deposition, and deposit thickness is 20～40
7. manufacture method as claimed in claim 6, is characterized in that, the parameter of described plasma etching industrial comprises: gas pressure intensity 2～10mTorr, and radio-frequency power 500W～1200W, bias power 100W～200W, etching gas is Cl
2and BCl
3, flow-rate ratio is 1:1～2:1.
8. manufacture method as claimed in claim 1, is characterized in that, the supporting side walls concrete steps of described formation insulation comprise:
Outer surface, the top surface of mold layer and the surface of Semiconductor substrate at described side-wall electrode form insulating medium layer;
Insulating medium layer described in employing plasma etching industrial etching, retains the part that described insulating medium layer is positioned at side-wall electrode outer surface, as supporting side walls.
9. manufacture method as claimed in claim 8, is characterized in that, the material of described insulating medium layer is silicon dioxide, silicon nitride or its combination.
10. manufacture method as claimed in claim 8, is characterized in that, described insulating medium layer adopts chemical vapour deposition (CVD) to form, and deposit thickness is 100～200
11. manufacture methods as claimed in claim 10, is characterized in that, the parameter of described plasma etching industrial can be: gas pressure intensity 2～15mTorr, and radio-frequency power 200～600w, employing etching gas is CF
4and He mist, flow-rate ratio is 1:1～1:3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010223482.9A CN102315384B (en) | 2010-07-02 | 2010-07-02 | Phase change random access memory and bottom electrode and making method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010223482.9A CN102315384B (en) | 2010-07-02 | 2010-07-02 | Phase change random access memory and bottom electrode and making method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102315384A CN102315384A (en) | 2012-01-11 |
| CN102315384B true CN102315384B (en) | 2014-04-02 |
Family
ID=45428337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010223482.9A Active CN102315384B (en) | 2010-07-02 | 2010-07-02 | Phase change random access memory and bottom electrode and making method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102315384B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7323357B2 (en) * | 2005-11-17 | 2008-01-29 | Qimonda Ag | Method for manufacturing a resistively switching memory cell and memory device based thereon |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100822800B1 (en) * | 2006-05-24 | 2008-04-17 | 삼성전자주식회사 | Phase change memory device and its formation method |
| US7989251B2 (en) * | 2007-05-14 | 2011-08-02 | Micron Technology, Inc. | Variable resistance memory device having reduced bottom contact area and method of forming the same |
-
2010
- 2010-07-02 CN CN201010223482.9A patent/CN102315384B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7323357B2 (en) * | 2005-11-17 | 2008-01-29 | Qimonda Ag | Method for manufacturing a resistively switching memory cell and memory device based thereon |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102315384A (en) | 2012-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10283710B2 (en) | Resistive random access memory device containing replacement word lines and method of making thereof | |
| TWI389363B (en) | Phase-change memory and method of making same | |
| CN101393964B (en) | Phase change memory device with different grain sizes and forming method thereof | |
| TWI325166B (en) | Programmable resistive ram and manufacturing method | |
| US11043537B2 (en) | Three-dimensional phase change memory device including vertically constricted current paths and methods of manufacturing the same | |
| KR100713936B1 (en) | Phase change memory device and manufacturing method thereof | |
| KR100985756B1 (en) | Phase change memory device and manufacturing method thereof | |
| CN102104055A (en) | Variable resistance memory device | |
| US10096654B2 (en) | Three-dimensional resistive random access memory containing self-aligned memory elements | |
| TWI497693B (en) | Memory cell and its process | |
| US9118008B2 (en) | Field focusing features in a ReRAM cell | |
| TW201640620A (en) | Resistive memory cells including localized filamentary channels, devices including the same, and methods of making the same | |
| CN103066204A (en) | Methods of manufacturing phase-change memory device and semiconductor device | |
| CN102376878B (en) | Manufacture method for bottom electrode of phase change memory | |
| TW201519485A (en) | Resistive random access memory and method of manufacture thereof | |
| CN102315384B (en) | Phase change random access memory and bottom electrode and making method thereof | |
| US8748958B1 (en) | Phase-change random access memory device and method of manufacturing the same | |
| CN102412367B (en) | Fabrication method of bottom electrode of phase change memory (PCM) | |
| CN102544363A (en) | Preparation method for phase change memory bottom electrode structure | |
| CN103325940B (en) | Phase-change memory cell and manufacturing method thereof | |
| CN203871380U (en) | Heating electrode and phase change memory structure | |
| CN102956820B (en) | The formation method of phase transition storage | |
| CN102299107B (en) | Method for manufacturing bottom electrode of memory cell of phase change memory | |
| CN102447058A (en) | Manufacturing method for phase change memory bottom electrode | |
| CN102468435B (en) | Manufacturing method of phase change memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121122 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20121122 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |