CN102315312B - Manufacturing process of silicon heterojunction solar cells - Google Patents
Manufacturing process of silicon heterojunction solar cells Download PDFInfo
- Publication number
- CN102315312B CN102315312B CN2010102268863A CN201010226886A CN102315312B CN 102315312 B CN102315312 B CN 102315312B CN 2010102268863 A CN2010102268863 A CN 2010102268863A CN 201010226886 A CN201010226886 A CN 201010226886A CN 102315312 B CN102315312 B CN 102315312B
- Authority
- CN
- China
- Prior art keywords
- silicon layer
- silicon
- layer
- electrical
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 164
- 239000010703 silicon Substances 0.000 title claims abstract description 164
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 163
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 24
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 23
- 150000002500 ions Chemical class 0.000 claims description 22
- 239000004744 fabric Substances 0.000 claims description 18
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000006243 chemical reaction Methods 0.000 description 11
- 239000010408 film Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 239000003245 coal Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000003345 natural gas Substances 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000007736 thin film deposition technique Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Photovoltaic Devices (AREA)
Abstract
The invention relates to a manufacturing process of a silicon heterojunction solar cell, which comprises a first electric silicon substrate, a first intrinsic silicon layer and a second intrinsic silicon layer which are respectively formed on two sides of the first electric silicon substrate and form a heterojunction with the first electric silicon substrate, and a second electric silicon layer and a first electric heavily doped silicon layer which are respectively formed on the first intrinsic silicon layer and the second intrinsic silicon layer; the second electrical silicon layer and the first electrical heavily doped silicon layer are formed by ion implantation to optimize the thickness and doping amount of the second electrical silicon layer and the first electrical heavily doped silicon layer.
Description
Technical field
The present invention relates to a kind of processing procedure of silicon heterojunction solar cell, relate in particular to a kind of processing procedure that reduces manufacturing cost and improve the silicon heterojunction solar cell of conversion efficiency.
Background technology
Along with the prosperity of science and technology, the evolution of civilization and the rapid growth of population, for use and the consumption sharp increase day by day of the energy.In the situation that the natural resources such as oil, natural gas and coal are limited, energy savings and look for, develop alternative energy source how, become just that everybody is primary solves and one of very important problem.Due to the energy from the sun greatly and continuously, therefore develop solar cell and just become gradually the main flow of new century as the equipment of generating, accumulate.
So-called solar cell is a kind ofly solar energy can be converted to the photoelectric subassembly of electric energy.The simplest solar cell structure comprises a p type semiconductor layer and a n type semiconductor layer, and both form a PN junction.When the solar radiation solar cell, energy from sunlight can be with the electron excitation in semiconductor layer out, electrons moves towards n type semiconductor layer because of built in potential, electric hole is to towards the p type semiconductor layer direction, moving, therefore when p type semiconductor layer and n type semiconductor layer connect external circuit formation loop, will generation current.The above-mentioned reaction that transfers luminous energy to electric current is referred to as photovoltaic effect (photovoltaic effect).
With reference to shown in Figure 1, it is the structural representation of the silicon heterojunction solar cell of electrical machinery of Japanese sanyo proposition.this silicon heterojunction solar cell 1 structure comprises a n type single crystal silicon substrate 11 (n-type single crystal silicon substrate), be formed at respectively one first intrinsic amorphous silicon layer 12 (intrinsic amorphoussilicon layer) and one second intrinsic amorphous silicon layer 13 of these n type single crystal silicon substrate 11 both sides, be formed at respectively a P type amorphous silicon layer 14 and a N+ type amorphous silicon layer 15 in this first intrinsic amorphous silicon layer 12 and these the second intrinsic amorphous silicon layer 13 outsides, be formed at respectively one first transparent conductive oxide (the transparent conductiveoxide in this P type amorphous silicon layer 14 and these N+ type amorphous silicon layer 15 outsides, TCO) layer 16 and 1 second including transparent conducting oxide layer 17 and one first electrode layer 18 and the second electrode lay 19 that are formed at respectively this first including transparent conducting oxide layer 16 and these the second including transparent conducting oxide layer 17 outsides.Because above-mentioned solar cell has silicon heterojunction and silicon intrinsic layer, HIT solar cell (Hetero-junction with Intrinsic Thin-layer solar cell) therefore is otherwise known as.The HIT solar cell is because possessing high-photoelectric transformation efficiency (photoelectric conversion efficiency) (Yue Keda 23%), and can engage by 200 ℃ of low temperature, be conducive to reduce the characteristics such as manufacturing cost, dropped into first solar energy market and namely deeply attract attention in 1997.
Wherein, P type amorphous silicon layer 14 in known structure and the thickness of N+ type amorphous silicon layer 15 are as thin as a wafer, approximately between several nanometers (nm) between tens nanometers, and for coordinating low temperature process, this P type amorphous silicon layer 14 and N+ type amorphous silicon layer 15 directly form film with plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD) usually.In the situation that film very thin (for example several nanometers) is difficult to film forming with the plasma enhanced chemical vapor deposition method, not only the concentration of doping is wayward, and the problem that the even or subregion of uneven film thickness can't film forming easily occurs.Because the film quality of above-mentioned amorphous silicon layer is affect the solar cell photoelectric conversion efficiency one large crucial, thus anxious to be resolved.
Summary of the invention
Therefore, the object of the invention is to propose a kind of processing procedure of silicon heterojunction solar cell, the film thickness of controlled doping layer and doping accuracy accurately thus, thus promote yield and the photoelectric conversion efficiency of silicon heterojunction solar cell.
To achieve these goals, the present invention proposes the processing procedure of silicon heterojunction solar cell, and its step comprises: preparation one first electrical crystalline silicon substrate; Form the first silicon layer and the second silicon layer on two sides of this first electrical crystalline silicon substrate, this first silicon layer and this second silicon layer form the silicon heterojunction with this first electrical crystalline silicon substrate respectively; Ion is implanted in this first silicon layer and this second silicon layer, cause subregion formation the second electrical silicon layer toward the outer side in this first silicon layer, and this second silicon layer subregion toward the outer side forms the first electrical heavy doping type silicon layer; Form one first oxidic, transparent, conductive layers on this second electrical silicon layer; And form respectively one first electrode layer and a second electrode lay on this first oxidic, transparent, conductive layers and this first electrical heavy doping type silicon layer.
By the silicon heterojunction solar cell that processing procedure of the present invention forms, can be in the situation that P type silicon layer and N+ type silicon layer as thin as a wafer, be controlled its doping content exactly.Avoid known process technique to produce the problem that thickness is uneven, doping is uneven.Relevant detailed technology content of the present invention and preferred embodiment, coordinate graphic explanation as after.
Description of drawings
Embodiments of the present invention are described in conjunction with graphic:
Fig. 1 is the structural representation of a known silicon heterojunction solar cell;
Fig. 2 is the flow chart of one embodiment of the invention; And
Fig. 3-1 is the schematic flow sheet of one embodiment of the invention to Fig. 3-8.
Embodiment
Relevant detailed description of the present invention and technology contents now coordinate graphic being described as follows:
With reference to shown in Figure 2, it is the flow chart of one embodiment of the invention, and as shown in the figure: the present invention proposes a kind of processing procedure of silicon heterojunction solar cell, and its step comprises: preparation one first electrical crystalline silicon substrate; Form the first silicon layer and the second silicon layer on two sides of this first electrical crystalline silicon substrate, this first silicon layer and this second silicon layer form the silicon heterojunction with this first electrical crystalline silicon substrate respectively; Ion is implanted in this first silicon layer and this second silicon layer, cause subregion formation the second electrical silicon layer toward the outer side in this first silicon layer, and this second silicon layer subregion toward the outer side forms the first electrical heavy doping type silicon layer; Form one first oxidic, transparent, conductive layers on this second electrical silicon layer; And form respectively one first electrode layer and a second electrode lay on this first oxidic, transparent, conductive layers and this first electrical heavy doping type silicon layer.
It should be noted that, above-mentioned so-called " first electrical " with " second electrical " refer to N-type doping or the doping of P type, even first is electrically N-type, second electrically just is reversed the P type; If first is electrically the P type, just second electrically be reversed N-type.On the other hand, so-called " heavy doping " refer to that N+ or P+ type adulterate.Yet,, for convenience of description with understanding,, with the detailed explanation of next embodiment, electrically be preset as N-type with first, second electrically is preset as the P type illustrates, but the present invention is not limited with it.
To shown in Fig. 3-8, it is the schematic flow sheet of one embodiment of the invention with reference to Fig. 3-1.At first as shown in Fig. 3-1, prepare a N-type crystalline silicon substrate 21, so-called N-type crystalline silicon substrate 21 can be n type single crystal silicon substrate (single crystal silicon substrate) or N-type polysilicon (polycrystal) substrate, its thickness is about 200~600 μ m, but with it, is not limited.Then, form respectively the first silicon layer 22 and the second silicon layer 23 on two sides of this N-type crystalline silicon substrate 21, as shown in Fig. 3-2.Wherein, the first silicon layer 22 and the second silicon layer 23 form the silicon heterojunction with N-type crystallizing silicon layer 21 respectively, and namely this first silicon layer 22 and the second silicon layer 23 can be amorphous silicon layer or polysilicon layer, and with the N-type crystalline silicon substrate 21 of monocrystalline, form the silicon heterojunction.In an above-mentioned embodiment, this N-type crystalline silicon substrate 21 is a N shape monocrystalline silicon substrate, and this first silicon layer 22 and the second silicon layer 23 be the amorphous silicon layer of intrinsic (doping), and its thickness is approximately between 0.3~15nm.
The mode that forms above-mentioned the first silicon layer 22 and the second silicon layer 23 does not have any restriction, can reach with any known semiconductive thin film deposition technique.For instance, in one embodiment of this invention, can utilize Low Pressure Chemical Vapor Deposition (low pressure chemicalvapor deposition, LPCVD) to form first, second silicon layer 22,23.Its process is first N-type crystalline silicon substrate 21 to be cleaned with standard RCA step, then inserts the low-pressure chemical vapor deposition boiler tube, and deposits simultaneously the first silicon layer 22 and second silicon layer 23 of amorphous in 21 two sides of N-type crystalline silicon substrate.The reaction equation of chemical vapour deposition (CVD) is SiH
4 (g)→ Si
(s)+ 2H
2 (g), its reaction temperature can be between 120~600 ℃, and reaction pressure can be between 0.1~500m-torr.
Shown in Fig. 3-4 and Fig. 3-5, after depositing respectively the first silicon layer 22 and the second silicon layer 23 in 21 two sides of N-type crystalline silicon substrate, then in the ion implantation mode, cause the subregion towards the outside in this first silicon layer 22 and the second silicon layer 23 to form respectively P type silicon layer 24 and N+ type silicon layer 25.Side by side, in this first silicon layer 22 and the second silicon layer 23, the part of the part outside P type silicon layer 24 and N+ type silicon layer 25 or close the first silicon layer 22 of N-type crystalline silicon substrate 21 and the second silicon layer 23 will form in fact an intrinsic silicon layer.
It should be noted that, in the situation that the first silicon layer 22 and the second silicon layer 23 are intrinsic silicon layer, after planting formation P type silicon layer 24 and N+ type silicon layer 25 with ion cloth, the first silicon layer 22 and the second silicon layer 23 can keep in fact intrinsic silicon state originally with the intersection of N-type crystalline silicon substrate 21.Relatively, if the first silicon layer 22 is in the situation of N-type silicon layer, after with P type ion, being implanted in the first silicon layer 22, the first silicon layer 22 can form P type silicon layer 24 towards lateral direction, and the first silicon layer 22 also can be because of positive and negative electrical neutralization towards the zone of N-type crystalline silicon substrate 21 intersections the self-assembling formation intrinsic silicon layer.Therefore the first silicon layer 22 and the second silicon layer 23 in the present invention need not to be defined in intrinsic silicon.
Further, after ion cloth has been planted, can pass through high temperature (900~1100 ℃) thermal anneal process, the atomic structure that causes cloth to plant ion and first, second silicon layer 22,23 produces bond, and removes simultaneously stress and defect again.In an above-mentioned embodiment, be with boron (B) or boron fluoride (BF
2) etc. group iii elements be that cloth is planted ion and is implanted in the first silicon layer 22, plant ion take arsenic or group-v element as cloth and be implanted in the second silicon layer 23.
On the other hand, in one embodiment, plant first, second silicon layer 22 with ion implanter may cloth, before 23, optionally prior to first forming respectively one first silicon oxide layer 31 (silicon oxide layer) and one second silicon oxide layer 32 on the first silicon layer 22 and the second silicon layer 23, use the resilient coating of as ion cloth, planting.Wait for ion cloth plant complete after, remove this first, second silicon oxide layer 31,32 with Wet-type etching (as utilizing SiO 2 etch liquid (buffered oxide etch, BOE) etching) again, cause this P type silicon layer 24 and this N+ type silicon layer 25 to expose, as Fig. 3-3 to as shown in Fig. 3-6.Wherein, the thickness of this first, second silicon oxide layer 31,32 is between 1~20nm.The mode that forms this first, second silicon oxide layer 31,32 is for example reached with chemical vapour deposition (CVD), and its reaction equation is exemplified below:
Si(OC
2H
5)
4(g)→SiO
2(s)+4C
2H
4(g)+2H
2O
2(g)
Wherein, the purpose and the advantage that form the first silicon oxide layer 31 and the second silicon oxide layer 32 are listed below: at first, first, second silicon oxide layer 31,32 can serve as first, second silicon layer 22 in the processing procedure that ion cloth is planted, a change layer of 23, to fill up first, second silicon layer 22,23 outstanding key (dangling bonds), make first, second silicon layer 22, the outstanding key on 23 surfaces reduces, strengthen architecture quality, to promote yield and the structural intergrity of silicon heterojunction solar cell, to increase simultaneously its photoelectric conversion efficiency.Secondly, the cloth of planting due to ion cloth is planted ion and can be passed through the first silicon oxide layer 31 and the second silicon oxide layer 32, and in first, second silicon layer 22, form the kind Gaussian Profile on 23, so this first, second silicon oxide layer 31,32 also can plant in order to adjust and to control cloth the degree of depth and the CONCENTRATION DISTRIBUTION of ion, to control concentration and the depth distribution of P type silicon layer 24 and N+ type silicon layer 25, make it to reach expect.On the other hand, first, second silicon oxide layer 31,32 also can be removed ion and vacancy (vacancies) not; The unnecessary vacancy that is to say generation when low weight ion and ion cloth are planted can be run superficially, and be distributed in first, second silicon oxide layer 31,32, so unnecessary cloth is planted ion or vacancy can remove with the etching of first, second silicon oxide layer 31,32.
Then, shown in Fig. 3-7, form the first oxidic, transparent, conductive layers 26 on this P type silicon layer 24, this first oxidic, transparent, conductive layers 26 can be used as the collecting layer of anti-reflecting layer and the electric current of sensitive surface, its material is for example tin indium oxide (ITO), but with it, is not limited.These N+ type silicon layer 25 outsides also optionally form the second oxidic, transparent, conductive layers 27 as current collection layer, and its material can be same as this first oxidic, transparent, conductive layers 26.Finally, respectively at the first oxidic, transparent, conductive layers 26 and second oxidic, transparent, conductive layers 27 outsides, form again the first electrode layer 28 and the second electrode lay 29, use electric connection place as silicon heterojunction solar cell, as shown in Fig. 3-8.
Silicon heterojunction solar cell by processing procedure formation of the present invention, can in the situation that P type silicon layer 24 and N+ type silicon layer 25 as thin as a wafer, control exactly its doping content, and can be by the auxiliary membrane quality that promotes P type silicon layer 24 and N+ type silicon layer 25 of silicon oxide layer.Moreover, if can with large-area ionic cloth plant machine fast cloth plant, cost may be comparatively cheap, and cloth plants precision and be easier to control, and can effectively promote the yield of processing procedure, and allow solar cell that better photoelectric conversion efficiency is arranged.
On the other hand,, though above-mentioned explanation also can in like manner be applicable to P type crystalline silicon substrate take N-type crystalline silicon substrate formation P-N-N+ structure as example, need to adjust simultaneously the electrical and concentration of doping this moment, make it form the N-P-P+ structure.Yet above said content, be only preferred embodiment of the present invention; the scope of patent protection of non-wish limitation patent of the present invention; therefore, the equivalence that all utilizations specification of the present invention and graphic content are done changes and modifies, and all in like manner is contained in the scope of the present invention.
Claims (7)
1. the processing procedure of a silicon heterojunction solar cell (1), its step comprises:
Prepare one first electrical crystalline silicon substrate;
Form the first silicon layer (22) and the second silicon layer (23) on two sides of the described first electrical crystalline silicon substrate; Described the first silicon layer (22) forms the silicon heterojunction with the described first electrical crystalline silicon substrate respectively with described the second silicon layer (23);
Form respectively one first silicon oxide layer (31) and one second silicon oxide layer (32) on described the first silicon layer (22) and described the second silicon layer (23) with chemical vapour deposition technique, to fill up the outstanding key of described the first silicon layer (22) and described the second silicon layer (23);
Ion is implanted in described the first silicon layer (22) and described the second silicon layer (23), cause subregion formation the second electrical silicon layer toward the outer side in described the first silicon layer (22), and described the second silicon layer (23) subregion toward the outer side forms the first electrical heavy doping type silicon layer;
Remove described the first silicon oxide layer (31) and described the second silicon oxide layer (32), cause the described second electrical silicon layer and the described first electrical heavy doping type silicon layer to expose;
Form one first oxidic, transparent, conductive layers (26) on the described second electrical silicon layer; And
Form respectively one first electrode layer (28) and a second electrode lay (29) on described the first oxidic, transparent, conductive layers (26) and the described first electrical heavy doping type silicon layer.
2. the processing procedure of silicon heterojunction solar cell according to claim 1 (1), it is characterized in that, before described the second electrode lay (29) is formed on the described first electrical heavy doping type silicon layer, also comprises and form the step of the second oxidic, transparent, conductive layers (27) on the described first electrical heavy doping type silicon layer.
3. the processing procedure of silicon heterojunction solar cell according to claim 1 (1), it is characterized in that, the described first electrical crystalline silicon substrate is a n type single crystal silicon substrate (21), the described second electrical silicon layer is a P type silicon layer (24), and the described first electrical heavy doping type silicon layer is a N+ type silicon layer (25).
4. the processing procedure of silicon heterojunction solar cell according to claim 1 (1), is characterized in that, described the first silicon layer (22) is the intrinsic amorphous silicon film with described the second silicon layer (23).
5. the processing procedure of silicon heterojunction solar cell according to claim 1 (1), is characterized in that, described the first silicon layer (22) forms with chemical vapour deposition technique with described the second silicon layer (23) simultaneously.
6. the processing procedure of silicon heterojunction solar cell according to claim 1 (1), is characterized in that, after ion cloth has been planted the described second electrical silicon layer and the described first electrical heavy doping type silicon layer, also comprises the step of a high-temperature thermal annealing.
7. the processing procedure of a silicon heterojunction solar cell (1), its step comprises:
Prepare a n type single crystal silicon substrate (21);
Form the first intrinsic amorphous silicon layer (12) and the second intrinsic amorphous silicon layer (13) on two sides of described n type single crystal silicon substrate (21);
Form respectively one first silicon oxide layer (31) and one second silicon oxide layer (32) on described the first intrinsic amorphous silicon layer (12) and described the second intrinsic amorphous silicon layer (13) with chemical vapour deposition technique, to fill up the outstanding key of described the first intrinsic amorphous silicon layer (12) and described the second intrinsic amorphous silicon layer (13);
Ion is implanted in described the first intrinsic amorphous silicon layer (12) and described the second intrinsic amorphous silicon layer (13), cause described the first intrinsic amorphous silicon layer (12) subregion toward the outer side to form P type amorphous silicon layer (14), described the second intrinsic amorphous silicon layer (13) subregion toward the outer side forms a N+ type amorphous silicon layer (15);
Remove described the first silicon oxide layer (31) and described the second silicon oxide layer (32), cause described P type amorphous silicon layer (14) and described N+ type amorphous silicon layer (15) to expose;
Form one first oxidic, transparent, conductive layers (26) on described P type amorphous silicon layer (14); And
Form respectively one first electrode layer (28) and a second electrode lay (29) on described the first oxidic, transparent, conductive layers (26) and described N+ type amorphous silicon layer (15).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010102268863A CN102315312B (en) | 2010-07-09 | 2010-07-09 | Manufacturing process of silicon heterojunction solar cells |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010102268863A CN102315312B (en) | 2010-07-09 | 2010-07-09 | Manufacturing process of silicon heterojunction solar cells |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102315312A CN102315312A (en) | 2012-01-11 |
CN102315312B true CN102315312B (en) | 2013-11-13 |
Family
ID=45428293
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2010102268863A Expired - Fee Related CN102315312B (en) | 2010-07-09 | 2010-07-09 | Manufacturing process of silicon heterojunction solar cells |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102315312B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103311376A (en) * | 2013-06-26 | 2013-09-18 | 英利集团有限公司 | Manufacturing method for N type solar cell |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1404113A (en) * | 2002-10-18 | 2003-03-19 | 中国科学院微电子中心 | Prepn of nitride-oxide film |
CN1445865A (en) * | 2001-11-29 | 2003-10-01 | 三洋电机株式会社 | Light generating device and manufacturing method thereof |
CN1534767A (en) * | 2003-04-02 | 2004-10-06 | �����ɷ� | Method for manufacturing read-only memory |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101000064B1 (en) * | 2007-12-18 | 2010-12-10 | 엘지전자 주식회사 | Heterojunction solar cell and its manufacturing method |
-
2010
- 2010-07-09 CN CN2010102268863A patent/CN102315312B/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1445865A (en) * | 2001-11-29 | 2003-10-01 | 三洋电机株式会社 | Light generating device and manufacturing method thereof |
CN1404113A (en) * | 2002-10-18 | 2003-03-19 | 中国科学院微电子中心 | Prepn of nitride-oxide film |
CN1178282C (en) * | 2002-10-18 | 2004-12-01 | 中国科学院微电子中心 | A kind of preparation method of nitrided oxide film |
CN1534767A (en) * | 2003-04-02 | 2004-10-06 | �����ɷ� | Method for manufacturing read-only memory |
Also Published As
Publication number | Publication date |
---|---|
CN102315312A (en) | 2012-01-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100965778B1 (en) | High efficiency polycrystalline silicon solar cell and manufacturing method thereof | |
KR101000064B1 (en) | Heterojunction solar cell and its manufacturing method | |
EP2385561A2 (en) | Solar Cell | |
US20100229927A1 (en) | Heterojunction solar cell based on epitaxial crystalline-silicon thin film on metallurgical silicon substrate design | |
JP2009503848A (en) | Composition gradient photovoltaic device, manufacturing method and related products | |
CN102064216A (en) | Novel crystalline silicon solar cell and manufacturing method thereof | |
US20110068367A1 (en) | Double-sided heterojunction solar cell based on thin epitaxial silicon | |
KR101886818B1 (en) | Method for manufacturing of heterojunction silicon solar cell | |
Park et al. | Tunnel oxide passivating electron contacts for high‐efficiency n‐type silicon solar cells with amorphous silicon passivating hole contacts | |
US20120015474A1 (en) | Method for fabricating silicon heterojunction solar cells | |
Chowdhury et al. | Analysis of passivation property using thin Al2O3 layer and simulation for realization of high-efficiency TOPCon cell | |
CN111584670A (en) | A tandem solar cell and its preparation method | |
US20120318335A1 (en) | Tandem solar cell with improved tunnel junction | |
KR20090078956A (en) | Method for manufacturing light absorption layer of polycrystalline silicon solar cell, high efficiency polycrystalline silicon solar cell using same and manufacturing method thereof | |
KR20100090015A (en) | Solar cell and method for fabricating the same | |
CN103107236B (en) | Heterojunction solar battery and preparation method thereof | |
CN102315312B (en) | Manufacturing process of silicon heterojunction solar cells | |
CN103107240B (en) | Multi-crystal silicon film solar battery and preparation method thereof | |
US20120255608A1 (en) | Back-surface-field type of heterojunction solar cell and a production method therefor | |
KR100965982B1 (en) | Polycrystalline Silicon Solar Cell and Manufacturing Method Thereof | |
CN103107234B (en) | Heterojunction solar battery and preparation method thereof | |
CN103107239B (en) | Heterojunction solar battery and preparation method thereof | |
KR101673241B1 (en) | Method for fabricating tandem solar cell with thin film silicon and bulk crystalline silicon using silicon thin film tunnel junction layer by PECVD and solar cell thereof | |
CN202977496U (en) | Heterojunction Solar Cells | |
CN202977495U (en) | Amorphous silicon thin film solar cell |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131113 Termination date: 20210709 |