CN102315196B - Multi-die stack package structure - Google Patents

Abstract

A multi-die stack package structure includes a substrate, a die-mounting region defined on an upper surface of the substrate and a plurality of contacts disposed outside the die-mounting region; the first crystal grain is provided with an active surface and a back surface, the back surface is arranged in the crystal grain arrangement area, a plurality of first welding pads are arranged on the active surface, and a first bump is formed on each first welding pad; a plurality of metal wires for connecting the first bumps to the contacts; the second crystal grain is provided with an active surface and a back surface, a plurality of second welding pads are arranged on the active surface, a second bump is formed on the second welding pads, and the second crystal grain is jointed with the first crystal grain by the active surface facing to the active surface of the first crystal grain, so that the second bump is respectively correspondingly connected with the metal wire and the first bump; the molding compound is used for covering the substrate, the first die, the second die and the metal wire.

Description

Multi-die stack package structure

【Technical field】

The invention relates to a multi-chip stacking packaging structure; in particular, it relates to a wafer-level stacking packaging structure using metal wires to connect bumps.

【Background technique】

In today's information society, with the successful development of portable products, users are pursuing high-speed, high-quality, and multi-functional portable electronic products, such as: notebook computers (Note Book), 3G mobile phones , Personal Digital Assistant (PDA) and game console (Video Game). As far as product appearance is concerned, the design of portable electronic products is moving towards the trend of being light, thin, short and small. In order to achieve the above goals, it is necessary to develop a multi-chip stacking structure, and the multi-chip stacking structure is to combine multiple chips in a stacked manner and electrically connect them under the same package size. To increase the memory capacity or add more functions.

With the progress of the manufacturing process, the operation speed and bandwidth required by each inter-chip bus (Bus) in the portable system are getting larger and larger, and the speed and bandwidth of the system bus depend on the package ( Package) technology, especially in the system-in-package (System in Package; SiP) that packages a variety of chips with different functions together. Therefore, when designing a multi-chip stack structure, it has faster transmission speed, shorter transmission path and better electrical characteristics, and further reduces the size and area of the chip packaging structure, thus making the chip stack structure common. It is used in various electronic products and will become the mainstream product in the future.

However, in the actual manufacturing process, the packaging of the multi-die stack structure faces challenges. First of all, as the performance of various consumer products improves, the demand for memory capacity is also greater. Therefore, when manufacturing large-capacity dynamic memory (DRAM), for example: 4Gb capacity DRAM; it is necessary to combine four 1Gb The DRAMs are packaged together, as shown in Figure 13A; to manufacture a DRAM with a capacity of 8Gb, eight 1Gb DRAMs need to be packaged together. With the increase of the number of grains, when using traditional metal wires as the connecting wires (trace) between the grains, in addition to the increase of the connecting path, or the inconsistent length of the connecting wires during the manufacturing process, it will cause In addition to the reduction of signal transmission speed or the generation of time delay and other effects, which will cause problems such as system inoperability or system access data errors; when using traditional metal wires as connecting wires for multiple die stacks, there is another problem The problem is the size of the package, that is, the height and area of a multi-die stack structure are limited, and this is another problem of using traditional metal wires as a multi-die stack between dies. question.

In order to solve this problem, a redistribution layer (RDL) can be used to shorten the connection path between multi-die stacks, and can effectively overcome the problem of the height of multiple die stacks, as shown in FIG. 13B . However, the high manufacturing cost of the redistribution layer (RDL) prohibits many high-performance products.

Therefore, in the multi-chip stack structure, how to maintain good electrical characteristics and optimal size, and how to achieve it with the lowest manufacturing cost has become an important issue that needs to be solved.

【Content of invention】

In order to solve the problems in the background technology related to the excessively long connection wires between the crystal grains and the inconsistent lengths of the connection wires in the multi-chip stacking structure, the present invention provides a wafer-level stack using metal wires to connect bumps The packaging structure, its main purpose is to provide multi-die stacking package, which can control the requirement of the same length of connecting wires between the die and the die with the stacking structure, so that the multi-die stacking structure after the package can have better electrical performance. features and reliability.

Another main purpose of the present invention is to provide a connection method using traditional metal wires and bumps as a multi-chip stack structure, which is used to replace the line redistribution layer (RDL) to reduce the multi-chip stack structure. manufacturing cost.

Another main purpose of the present invention is to provide a connection method using traditional metal wires and through-silicon via technology (Trough-Silicon-Vias, TSVs) as a connection method of a multi-chip stack structure, which can effectively reduce the package height and Increase the integration level of the stack, and increase the operation speed and bandwidth at the same time.

Another main purpose of the present invention is to provide a connection method using traditional metal wires and bumps as a connection method for a multi-chip stack structure or a connection method using traditional metal wires and silicon through-hole technology as a multi-chip stacking Structures are connected to form a system-level package structure.

According to the above-mentioned purpose, the present invention firstly provides a multi-chip stacked packaging structure, including a substrate with an upper surface and a lower surface, and a die setting area is defined on the upper surface and a plurality of contacts are configured, and the contacts are located at Outside the crystal grain setting area; a first crystal grain has an active surface and a back surface opposite to the active surface. A welding pad and a first bump is formed on the first welding pad; a plurality of metal wires are used to connect the first bump to the contact point; a second crystal grain has an active surface and a back surface opposite to the active surface, A plurality of second pads are arranged on the active surface, a second bump is formed on the second pads, the second crystal grain is bonded to the first crystal grain with the active surface facing the first crystal grain, The second bumps are respectively connected to the metal wires and the first bumps; the colloid is used to cover the substrate, the first crystal grain, the second crystal grain and the metal wires.

The present invention then provides a multi-die stacking package structure, including a substrate, which has an upper surface and a lower surface, a die setting area is defined on the upper surface and a plurality of contacts are arranged, and the contacts are located outside the die setting area ; a first crystal grain, having an active surface and a back surface opposite to the active surface, the first crystal grain is arranged in the crystal grain setting area with the back surface, a plurality of first pads are arranged on the active surface and the first A first bump is formed on the welding pad; a second crystal grain has an active surface and a back surface opposite to the active surface and a plurality of through-silicon crystal plugs, and the through-silicon crystal plugs penetrate the second crystal grain to make the active surface The back surface is electrically connected with each other, and a plurality of second bumps are formed on the active surface to connect with through-silicon plugs respectively, wherein the second crystal grain is bonded to the first crystal grain with the active surface facing the first crystal grain with the back surface, The through-silicon plugs are respectively connected to the first bump; a plurality of metal wires are used to connect the second bump to the contact point; a third crystal grain has an active surface and a back surface opposite to the active surface and a plurality of Through-silicon plugs, the through-silicon plugs penetrate the third crystal grain to electrically connect the active surface and the back surface, and a plurality of third bumps are formed on the active surface to connect the through-silicon plugs respectively, wherein the third crystal grain The grain faces the active surface of the second crystal grain with the active surface to bond the second crystal grain, so that the third bumps are respectively connected to the metal wires and the second bumps; a fourth crystal grain has an active surface and On the back side of the active side, a plurality of second pads are arranged on the active side, and a fourth bump is formed on the second pads, and the active side of the fourth grain faces the back side of the third grain Bonding the third die, so that the fourth bumps correspond to the through-silicon plugs connected to the third die; a colloid is used to cover the substrate, the first die, the second die, the third die, the fourth die Die and metal wire.

The present invention further provides a multi-die stacking package structure, which includes a substrate with an upper surface and a lower surface, a die setting area is defined on the upper surface and a plurality of contacts are arranged, and a concave is formed in the die setting area. The groove, and the contact is located outside the crystal grain setting area; a first crystal grain has an active surface and a back surface opposite to the active surface, the first crystal grain is arranged in the groove with the back surface, and the active surface is configured There are a plurality of first pads and a first bump is formed on the first pads; a plurality of metal wires are used to connect the first bumps to contacts; a second crystal grain has an active surface and an opposite active surface A back surface of the active surface is provided with a plurality of second welding pads, a second bump is formed on the second welding pads, and the active surface of the second crystal grain faces the active surface of the first crystal grain to bond the first The crystal grain, so that the second bump is respectively connected to the metal wire and the first bump; a colloid is used to cover the substrate, the first crystal grain, the second crystal grain and the metal wire.

The present invention further provides a multi-die stacking package structure, which includes a substrate with an upper surface and a lower surface, a die setting area is defined on the upper surface and a plurality of contacts are arranged, and a die setting area is formed in the die setting area. The groove, the contact point is located outside the crystal grain setting area; a first crystal grain has an active surface and a back surface opposite to the active surface, the first crystal grain is arranged in the groove with the back surface, and the active surface is configured There are a plurality of first welding pads and a first bump is formed on the first welding pads; a second crystal grain has an active surface and a back surface opposite to the active surface and a plurality of through-silicon plugs, the through-silicon plugs Through the second crystal grain to electrically connect the active surface and the back surface, a plurality of second bumps are formed on the active surface to respectively connect through silicon plugs, wherein the second crystal grain faces the first crystal grain with the back surface The active surface of the first die is bonded so that the through-silicon plugs are respectively connected to the first bumps; a plurality of metal wires are used to connect the second bumps to the contacts; a third die has an active surface and a back surface opposite to the active surface, and a plurality of through-silicon plugs. The through-silicon plugs penetrate the third grain to electrically connect the active surface and the back surface, and form a plurality of third bumps on the active surface. The blocks are respectively connected to through-silicon plugs, wherein the active surface of the third crystal grain faces the active surface of the second crystal grain and is bonded to the second crystal grain, so that the third bumps are respectively connected to the metal wires and the second bumps; The fourth crystal grain has an active surface and a back surface opposite to the active surface. A plurality of second pads are arranged on the active surface, and a fourth bump is formed on the second pads. The fourth crystal grain is The active surface faces the back side of the third crystal grain and joins the third crystal grain, so that the fourth bumps respectively correspond to the through-silicon plugs connected to the third crystal grain; a colloid is used to cover the substrate, the first crystal grain, the second crystal grain The second crystal grain, the third crystal grain, the fourth crystal grain and the metal wire.

The present invention further provides a multi-die stacking package structure, which includes a substrate with an upper surface and a lower surface, a die setting area is defined on the upper surface and a plurality of contacts are arranged, and the contacts are located on the die setting area. Outside; a first crystal grain, having an active surface and a back surface opposite to the active surface, the first crystal grain is arranged in the crystal grain setting area with the back surface, and a plurality of first solder joints are arranged on the peripheral area of the active surface A first bump is formed on the pad and the first pad; a plurality of metal wires are used to connect the first bump to the contact point; a second crystal grain has an active surface and a back surface opposite to the active surface and A plurality of through-silicon plugs, each through-silicon plug penetrates the second die to electrically connect the active surface and the back surface, and each through-silicon plug forms a first end on the active surface and connects to the back surface forming a second end, and forming a second bump on at least part of the second end of the through-silicon plug, wherein the second die is bonded to the first die with its back facing the active surface of the first die , so that the second bumps are respectively connected to the metal wires and the first bumps; a third crystal grain has an active surface and a back surface opposite to the active surface and a plurality of through-silicon crystal plugs, each through-silicon crystal plug through the third die so that the active surface and the back surface are electrically connected to each other, and each through-silicon plug forms a first end on the active surface and a second end on the back surface, and at least partially through silicon plugs A third bump is respectively formed on the second end of the crystal plug, wherein the third crystal grain is bonded to the second crystal grain with the back face facing the active surface of the second crystal grain, so that the third bumps of the third crystal grain respectively correspond to The first end of the through-silicon crystal plug connected to the second crystal grain; a colloid is used to cover the substrate, the first crystal grain, the second crystal grain, the third crystal grain and the metal wire.

【Description of drawings】

FIG. 1 is a schematic diagram of a wafer that has completed the front-end process;

2A to 2I are schematic cross-sectional views of an embodiment of the multi-die stacked packaging structure of the present invention;

3 is a schematic cross-sectional view of another embodiment of the multi-die stacked packaging structure of the present invention;

4 is a schematic cross-sectional view of yet another embodiment of the multi-die stacked packaging structure of the present invention;

5A to 5F are schematic cross-sectional views of an embodiment of a multi-die stacked package structure with a through-silicon plug of the present invention;

6 is a schematic cross-sectional view of another embodiment of a multi-die stacked package structure with through-silicon plugs of the present invention;

7 is a schematic cross-sectional view of yet another embodiment of the multi-die stacked package structure with through-silicon plugs of the present invention;

8A and 8D are cross-sectional schematic diagrams of a system-in-package structure formed by a multi-die stacked package structure of the present invention;

9 is a schematic cross-sectional view of yet another embodiment of a system-in-package structure formed by the multi-die stacked package structure of the present invention;

10A to 10D are schematic cross-sectional views of yet another embodiment of the multi-die stacked package structure with through-silicon plugs of the present invention;

11 is a schematic cross-sectional view of yet another embodiment of a multi-die stacked package structure with through-silicon plugs of the present invention;

12 is a schematic cross-sectional view of yet another embodiment of a system-in-package structure formed by a multi-die stacked package structure with a through-silicon plug of the present invention; and

13A and 13B are schematic cross-sectional views showing the prior art multi-die stacked package structure.

[Description of main component symbols]

Wafer 10

Die 100, 100a, 100b

Die Active Surface 101

Die Back 103

Pad 110

sealing layer 140

Bumps 20, 20a, 20b

Substrate 200

Substrate upper surface 210

Substrate lower surface 220

External contact 230 on the lower surface of the substrate

Substrate upper surface contacts 240

Groove 250 on substrate

Solder ball 260

Overlay 280

Metal wire 30

Dies 300, 300a, 300b with TSVs

Through the active surface 301 of the silicon plugged die

backside of die through silicon plug 303

Thru Silicon Plug 330

The first end 331 of the through-silicon plug

The second terminal 333 of the through-silicon plug

Bump 40

Stack structure 400A

Dies 400, 400a, 400b with through silicon plugs

Through the active surface 401 of the silicon plugged die

back side of die through silicon plug 403

Thru Silicon Plug 450

The first end 451 of the through-silicon plug

The second terminal 453 of the through-silicon plug

Through silicon plug bumps 455, 457

Bumps 50, 50a, 50b

Sealing layer 80

Sealant 90

Control grain 500

Bonding pad 510 for controlling the die

Grain 600

Pad 610

Bump 70

【Detailed ways】

The direction that the present invention discusses here is a wafer-level stacked packaging structure that uses metal wires to connect bumps. The packaged multi-chip stack structure can have better electrical characteristics and reliability. In order to provide a thorough understanding of the present invention, detailed steps and components thereof will be set forth in the following description. Apparently, on the one hand, the implementation of the present invention does not limit the method of die stacking, especially the various methods of die stacking familiar to those skilled in the art. On the other hand, the well-known grain formation method and the detailed steps of the back-end process such as grain thinning are not described in detail to avoid unnecessary limitation of the present invention. However, for the preferred embodiments of the present invention, it will be described in detail as follows, but in addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and the scope of the present invention is not limited. Subsequent patent scope shall prevail.

First, please refer to FIG. 1. In the modern semiconductor packaging process, a wafer 10 (wafer) that has completed the front end process (Front End Process) is subjected to a cutting process (sawing process) to form individual grains 100. , in which a plurality of pads 110 are arranged on the active surface of each crystal grain; and in an embodiment of the present invention, the plurality of welding pads 110 configured on the active surface of each crystal grain are located on the active surface The central area, as shown in Figure 1.

Next, please refer to FIGS. 2A-2H , which are schematic cross-sectional views of an embodiment of the process of forming a multi-chip stack structure of the present invention. First, as shown in FIG. 2A, the die 100 has an active surface 101 and an opposite back surface 103, and a plurality of welding pads 110 are disposed on the active surface 101, and the plurality of welding pads 110 are located on the active surface 101 of the die 100. of the central area. Next, please refer to FIG. 2B , a bump 20 is formed on the pad 110 , especially a stud bump (STUD BUMP), and the stud bump is sintered by wire bonding technology to form a bump on the pad 110 superior. It should be emphasized here that the bump 20 may be an electroplated bump, an electroless plated bump, a wiring bump, a conductive polymer bump or a metal composite bump, and the present invention is not limited thereto. The material of the bump 20 can be selected from the following groups: copper, gold, silver, indium, nickel/gold, nickel/palladium/gold, copper/nickel/gold, copper/gold, aluminum, conductive polymer materials and combinations thereof wait. At this point, a plurality of crystal grains 100 that have completed the bump 20 process have been formed. Next, please refer to FIG. 2C, the back surface 103 of the first crystal grain 100a as shown in FIG. A die setting area (not shown in the figure) is defined and a plurality of contacts 240 are configured. These contacts 240 are located outside the die setting area, and the first die 100a is the die adhered to the substrate 200 by the adhesive layer 120 within the setting area. In addition, on the lower surface 220 of the substrate 200, a plurality of external contacts 230 are disposed, and electrical connection components, such as solder balls (shown in FIG. 4 ), can be further disposed on the external contacts 230, as external electrical connections for sexual connection. Furthermore, referring to FIG. 2D, the first bump 20a on the first die 100a in FIG. 2C is electrically connected to the contact point 240 on the substrate 200 through a plurality of metal wires 30, as shown in FIGS. 2D and 2E Shown (wherein, Fig. 2D is the top view of Fig. 2E). The method of forming the metal wire 30 can be performed by selecting a reverse bonding process. Then, referring to FIG. 2F , a second die 100 b as in FIG. 2B is bonded to the first die 100 a in FIG. 2E in a flip chip manner, so that the second bumps 20 b are respectively connected to the metal wires 30 and the first bump 20a of the first die 100a. Therefore, the first crystal grain 100 a and the second crystal grain 100 b form an electrical connection, and are further electrically connected to the substrate 200 through the metal wire 30 .

In addition, it should be particularly noted that when the bump 20 in the foregoing embodiments is a flexible metal material, such as gold, the low hardness, high toughness and good compliance of the flexible metal can be used, It makes it possible to absorb the deformation (Deformation) generated in the horizontal and vertical directions on the bonding interface of the electrodes (ie, bumps) due to the mismatch of thermal expansion coefficients between the metal electrode materials when performing vertical stacking of multi-crystal grains. Overcoming the problem of roughness between metal electrode materials, it can effectively increase the reliability of the manufacturing process and products of multi-crystal grain vertical stacking.

Referring to FIG. 2G again, a polymer material filling process is selectively performed, so that the polymer material fills the space between the active surfaces 101 of the two crystal grains 100a, 100b to form a sealing layer 80 to stabilize Stack structure and provide electrical contact protection. This filling process can be filled in the gap between the dies 100a and 100b by using a high-pressure method after the completion of FIG. 2F, or it can be coated or pasted in the gap between the dies 100a and 100b before flip-chip bonding the second die 100b in FIG. 2E. on the first die 100a. The sealing layer 80 can be selected from the following groups: non-conductive paste (NCP), non-conductive film (non-conductive film; NCF), anisotropic conductive paste (anisotropic conductive paste; ACP), anisotropic Anisotropic conductive film (ACF), underfill, non-flow underfill, B-stage resin, molding compound, FOW (film-over- wire) film, etc.

Finally, an encapsulation process is performed to form an encapsulant 90 for covering the substrate 200 , the first die 100 a , the second die 100 b and the metal wire 30 . So far, the multi-die stacked packaging structure of this embodiment is completed, as shown in FIG. 2H .

In the multi-die stacked package structure of this embodiment, multiple dies 100 use a flip-chip method to connect a plurality of solder pads 110 on the active surface 101 of each die 100 to each other correspondingly, and through metal The wires 30 are connected to the contacts 240 on the upper surface 210 of the substrate 200 . Obviously, in this embodiment, the length of the metal wire 30 used to connect each solder pad 110 on the active surface 101 of each crystal grain 100 to each corresponding contact 240 on the upper surface 210 of the substrate 200 is the same. Therefore, in FIG. 13A , metal wires of different lengths are used to electrically connect different dies to cause signal transmission to cause time delay and other effects, thereby causing problems such as system inoperability or system access data errors. Therefore, this embodiment has better electrical characteristics and reliability.

Next, as shown in FIG. 2I , a control chip 500 is embedded in the structure of the substrate 200, and the control chip 500 is electrically connected to the substrate 200, so that the active surface of the control chip 500 passes through the substrate. The circuit in 200 is electrically connected to a plurality of external contacts 230 arranged on the lower surface 220 of the substrate 200; in addition, the method of embedding the control die 500 may be to arrange the control die 500 during the formation process of the multilayer circuit board. In the substrate 200 , since the control chip 500 is embedded in the substrate 200 using conventional techniques, it will not be described in detail. Obviously, the difference between FIG. 2I and FIG. 2H is: in FIG. 2H, a control crystal grain 500 embedded in the substrate 200 is further configured, and the rest of the connection process for forming the first crystal grain 100a and the second crystal grain 100b is the same as 2C to 2H are the same, so they will not be repeated here.

Please refer to FIG. 3 , which is a schematic cross-sectional view of another embodiment of the multi-die stacking structure of the present invention. In this embodiment, after the aforementioned structure in FIG. 2E is completed, another wiring bump 40 is further formed on the contact point where each metal wire 30 is electrically connected to the first bump 20a. The wiring bump 40 A bump is sintered by wire bonding technology and bonded to the connection point between the metal wire 30 and the first bump 20a to enhance the bonding strength of the metal wire 30 and provide a buffer effect for subsequent flip-chip bonding; then, another As shown in FIG. 2B, the second die 100b is bonded to the first die 100a in a flip-chip manner, so that the second bumps 20b of the second die 100b are connected to the wiring bumps 40 respectively. Therefore, the first die 100a and The second crystal grain 100b forms an electrical connection, and is further electrically connected to the substrate 200 through the metal wire 30 . The present embodiment does not limit the number of wiring bumps 40 disposed on the connection point between each metal wire 30 and the first bump 20a, and the number can be adjusted according to electrical properties and height requirements. Same as the previous embodiment, a polymer material filling process is optionally performed to form a sealing layer 80 in the space between the active surfaces 101 of the two dies 100a, 100b. The forming method and material of the sealing layer 80 are the same as those of the previous embodiments, so the description will not be repeated. Finally, an encapsulation process is performed to form an encapsulant 90 for covering the substrate 200 , the first die 100 a , the second die 100 b and the metal wire 30 .

In the stacked die package structure of this embodiment, multiple dies 100 are connected to each other through a flip-chip method to correspondingly connect a plurality of pads 110 on the active surface 101 of each die 100 , and through metal wires 30 connected to the contacts 240 on the upper surface 210 of the substrate 200 . Obviously, in this embodiment, the length of the metal wire 30 used to connect each solder pad 110 on the active surface 101 of each crystal grain 100 to each corresponding contact 240 on the upper surface 210 of the substrate 200 is the same. It is the same, so it can overcome the effects of time delay in signal transmission caused by the use of metal wires of different lengths for electrical connection of different chips, which will cause problems such as system inoperability or system access data errors. Therefore, this embodiment has better electrical characteristics and reliability.

Next, please refer to FIG. 4 , which is a schematic cross-sectional view of yet another embodiment of the multi-die stacked package structure of the present invention. Similarly, a grain arrangement area (not shown) is defined on the upper surface 210 of the substrate 200 of the present embodiment and a plurality of contacts 240 are configured, a groove 250 (cavity) is formed in the grain arrangement area, and these contacts 240 is located outside the crystal grain setting area, wherein the length and width of the groove 250 are larger than the length and width of the crystal grain 100, so a mechanical device can be used to pass a first crystal grain 100a as shown in FIG. 2B with its back surface 103 The adhesive layer 120 is pasted in the groove 250 . Next, an inverse wire bonding process may be selected to electrically connect the first bump 20a on the active surface 101 of the first die 100a to the contact point 240 on the substrate 200 with a plurality of metal wires 30 . Obviously, when the groove 250 of the substrate 200 is properly designed, for example, the depth of the groove 250 is designed to be close to the thickness of the first die 100a. In the groove 250, the contact point 240 on the upper surface 210 of the substrate 200 has a similar height to the first bump 20a on the first die 100a, so that a plurality of metal wires 30 can be connected with the smallest arc and the shortest length. The contact 240 on the substrate 200 is electrically connected to the first bump 20a on the first die 100a, so that the multi-die stack structure can have the best electrical characteristics. Then, a second crystal grain 100b that is the same as that shown in FIG. bumps 20a to form a multi-chip stack structure. Similarly, a polymer material filling process can also be optionally performed to form a sealing layer 80 in the space between the active surfaces 101 of the two dies 100a, 100b to stabilize the stack structure. Furthermore, the encapsulation process is performed to form an encapsulant 90 to cover the substrate 200, the first die 100a, the second die 100b and the metal wire 30, and the gap between the first die 100a and the groove 250 It is also filled up by the sealant 90 at the same time. Since the sealing layer filling process, sealing process and materials thereof are the same as those of the foregoing embodiments, the description thereof will not be repeated. Finally, a ball planting process can also be performed to dispose solder balls 260 on the plurality of external contacts 230 on the lower surface 220 of the substrate 200 as external electrical connection components. Therefore, when each die 100 in this stack structure is a 1Gb DRAM, then the packaging structure of this multi-die stack becomes a 2Gb DRAM product, which can be applied in portable electronic products, such as: notebook laptops, 3G mobile phones, personal digital assistants, and game consoles.

Obviously, in the embodiment of FIG. 4, the optimal length of the metal wire 30 can be used to connect the bumps 20a, 20b on the two dies 100a, 100b to the contact 240 of the substrate 200, so that this embodiment has a relatively Excellent electrical characteristics and reliability. Furthermore, through the configuration of the groove 250 on the substrate 200 , the height of the entire multi-chip stack package structure can be significantly reduced. Furthermore, this embodiment can also be similar to FIG. 3 , after the metal wires 30 are connected to the bumps 20a on the first die 100a, another connection bump 40 is formed between each metal wire 30 and the first bump 20a. The connection point of the metal wire 30 is used to enhance the bonding strength of the metal wire 30 and provide a buffer effect for subsequent flip-chip bonding. In this way, the multi-chip stacked packaging structure can have better matching of thermal expansion coefficients at the electrodes, which can increase the reliability of the package.

Please refer to FIG. 5A to FIG. 5E , which are schematic cross-sectional views of an embodiment of a multi-die stack package structure with TSVs of the present invention. First, as shown in FIG. 5A , it is a schematic cross-sectional view of a die 300 with TSVs of the present invention. The die 300 has a source surface 301 and a back surface 303 opposite to the active face 301 , and a plurality of vertical through holes penetrating the die 300 are formed on the die 300 . The way to form the through hole can be formed by laser drilling (laser drilling), dry etching (dryetching) or wet etching (wet etching), wherein the width of the through hole can be between 1 micron (um) to 50 microns ( um), and a preferred width is 10 microns (um) to 20 microns (um). Through silicon vias 330 (TSVs) are further formed in the through holes to electrically connect the active surface 301 and the back surface 303 . The first ends 331 of the TSVs 330 are adjacent to the active side 301 of the die 300 , and the opposite second ends 333 are adjacent to the backside 303 of the die 300 . The material of the TSV 330 can be selected from the following group: copper, tungsten, nickel, aluminum, gold, poly-silicon and combinations thereof. In this embodiment, the TSV 330 is disposed in the central area of the die 300 .

Next, please refer to FIG. 5B, a second die 300a having a plurality of through silicon plugs 330 as shown in FIG. 5A is bonded to the first die 100a in FIG. 2C to form a first stack structure, wherein the first die A stack structure is to electrically connect the second ends 333 of the plurality of through-silicon plugs 330 of the second die 300a to the first bumps 20a of the first die 100a respectively; and in a preferred embodiment In the same way, a sealing layer 140 may be formed between the first die 100a and the second die 300a, so as to make the first stack structure more stable. The sealing layer 140 can be laid on the active surface 101 of the first die 100a before the second die 300a is bonded to the first die 100a, or the sealing layer filling process can be performed after the entire multi-die stack structure is completed, The filling process and material of the sealing layer 140 are the same as the aforementioned sealing layer 80 , so the description will not be repeated.

Next, please refer to FIG. 5C, a plurality of second bumps 50a are formed on the first ends 331 of the plurality of through-silicon plugs 330 of the second die 300a. The type and material of the second bumps 50a are the same as those described above. The bumps 20 are the same. Next, the second bump 50 a on the second die 300 a in FIG. 5C is electrically connected to the contact point 240 on the substrate 200 through a plurality of metal wires 30 , as shown in FIG. 5D . The method of forming the metal wire 30 can be performed by selecting a reverse bonding process.

In addition, in the same process, a third crystal grain 300b as shown in FIG. 5A is electrically connected with a fourth crystal grain 100b as shown in FIG. 2B to form a second stack structure, wherein the second The stack structure is to electrically connect the second ends 333 of the plurality of through-silicon plugs 330 of the third crystal grain 300b to the fourth bumps 20b of the fourth crystal grain 100b respectively; A sealing layer 140 is formed between the die 300b and the fourth die 100b to obtain a stable second stack structure. Subsequently, a plurality of second bumps 50b are formed on the first ends 331 of the plurality of through-silicon plugs 330 of the third die 300b of the second stack structure. Then, the second stack structure is flip-chip, and the third bumps 50b on the third crystal grain 300b of the second stack structure are respectively connected to the second bumps of the second crystal grain 300a of the first stack structure. Block 50a and metal wire 30 to form a multi-chip stack structure composed of four stacked chips 100a, 100b, 300a, 300b, as shown in FIG. 5E. In addition, in this embodiment, after the third bump 50b is formed on the third die 300b, the third die 300b is electrically connected to the second die 300a, so that the third bumps 50b are respectively connected to the metal wires. 30 and the second bump 50a of the second die 300a; then, the fourth die 100b is flip-chip bonded to the third die 300b, so that the fourth bumps 20b on the fourth die 100b are respectively connected to The third die 300b is connected to the second end 333 of the silicon plug 330 to form a multi-die stack structure as shown in FIG. 5E .

Similarly, a polymer material filling process can also be optionally performed to form the sealing layer 80 in the space between the first stack structure and the second stack structure and to form the sealing layer 140 between the first crystal grain 100a and the second crystal grain 100a. between the grains 300a and between the third grain 300b and the fourth grain 100b to stabilize the multi-die stack structure. Next, an encapsulation process is performed to form an encapsulant 90 for covering the substrate 200 , the first die 100 a , the second die 300 a , the third die 300 b , the fourth die 100 b and the metal wire 30 . Since the sealing layer 80/140 filling process and sealing process and its materials are the same as those of the above-mentioned embodiments, the description thereof will not be repeated. Finally, solder balls (not shown in FIG. 5E ) can also be disposed on the plurality of external contacts 230 on the lower surface 220 of the substrate 200 as external electrical connection components. Obviously, when each die 100, 300 in this stack structure is a 1Gb DRAM, then this multi-die stack package structure becomes a 4Gb DRAM product, which can be applied to portable electronic products Among them, such as: notebook computers, 3G mobile phones, personal digital assistants and game consoles.

Next, as shown in FIG. 5F, a control die 500 is embedded in the structure of the substrate 200, and the control die 500 is electrically connected to the substrate 200, so that the active surface of the control die 500 passes through the substrate. The circuit in 200 is electrically connected to a plurality of external contacts 230 arranged on the lower surface 220 of the substrate 200; in addition, the method of embedding the control die 500 may be to arrange the control die 500 during the formation process of the multilayer circuit board. In the substrate 200 , the buried structure is formed by conventional techniques, so no detailed description is given here. Obviously, the difference between FIG. 5F and FIG. 5E is: in FIG. 5E, a control grain 500 embedded in the substrate 200 is further configured, and the rest form the first crystal grain 100a, the second crystal grain 300a, and the third crystal grain The connection processes of 300b and the fourth die 100b are the same as those in FIG. 5B to FIG. 5E , so details are not repeated here.

Next, please refer to FIG. 6 , which is a schematic cross-sectional view of an embodiment of the multi-chip stack structure formed on a substrate with grooves of the present invention. As shown in FIG. 6 , its multi-die stacking structure is the same as that in FIG. 5E , and the difference lies in the substrate 200 . The structure of the substrate 200 in this embodiment is the same as that of the substrate 200 in FIG. The grooves 250 and the contacts 240 are located outside the die placement area, wherein the length and width of the grooves 250 are greater than the length and width of the die 100 . After the first stack structure as shown in FIG. 5C is formed in the groove 250 of the substrate 200, the second bump 50a on the second crystal grain 300a is electrically connected to the second bump 50a on the second crystal grain 300a through, for example, a plurality of metal wires 30 formed by a reverse bonding process. connected to the contacts 240 on the substrate 200. Obviously, when the groove 250 of the substrate 200 is properly designed, for example: the depth of the groove 250 is designed to be close to the thickness of the first stack structure including the crystal grains 100a and 300a, therefore, when the first stack structure is After the back surface 103 of the first die 100a is pasted in the groove 250 of the substrate 200 through the adhesive layer 120, the contact 240 on the upper surface 210 of the substrate 200 is close to the second bump 50a on the second die 300a. height, so that a plurality of metal wires 30 can electrically connect the contact point 240 on the substrate 200 with the second bump 50a on the second crystal grain 300a with the smallest arc and the shortest length, so that the multiple metal wires 30 can be electrically connected together The die stack structure has the best electrical characteristics. Since the process of forming the multi-chip stack structure is the same as that of the previous embodiment, it will not be described again. Similarly, in this embodiment, a polymer material filling process can also be optionally performed to form the sealing layer 80/140 in the space between each die 100a, 300a, 300b, 100b, so as to stabilize the stack structure. At the same time, the encapsulation process can also be performed to form an encapsulation 90 to cover the substrate 200, the first die 100a, the second die 300a, the third die 300b, the fourth die 100b and the metal wire 30. , and the gap between the first die 100 a and the second die 300 a and the groove 250 is also filled by the encapsulant 90 at the same time. Since the sealing layer filling process, sealing process and materials thereof are the same as those of the foregoing embodiments, the description thereof will not be repeated. Finally, solder balls 260 can also be disposed on the plurality of external contacts 230 on the lower surface 220 of the substrate 200 as external electrical connection components.

Obviously, in the embodiment of FIG. 6, the optimal length of the metal wire 30 can be used to connect the bump 50a/50b on the die 300a/300b to the contact 240 on the substrate 200, so that this embodiment has better electrical characteristics and reliability. Furthermore, through the configuration of the groove 250 on the substrate 200 , the height of the entire multi-chip stack package structure can be significantly reduced. Furthermore, in this embodiment, similar to FIG. 3 , after the metal wires 30 are connected to the second bumps 50a on the second crystal grain 300a, another junction bump 40 is formed between each metal wire 30 and the second bump. The connection point of the block 50a is used to enhance the bonding strength of the metal wire 30 and provide a buffer effect for the subsequent flip-chip bonding. In this way, the multi-chip stack structure can have better thermal expansion coefficient matching at the electrodes, which can increase the reliability of the package.

Next, please refer to FIG. 7 , which is a schematic cross-sectional view of yet another embodiment of the multi-die stacked package structure of the present invention. As shown in FIG. 7 , firstly, vertically stack three crystal grains 300 having a plurality of through-silicon plugs 330 in FIG. A bump 50 is correspondingly formed on the first end 331; then the bump 50 of one crystal grain 300 is electrically connected to the second end 333 of the through-silicon plug 330 of the other crystal grain 300 respectively, and then the The stack structure of the three crystal grains 300 is electrically connected to the grain 100 of FIG. The ends 333 are correspondingly connected to the bumps 20 of the die 100 . Then, the bump 50 on the uppermost die 300 in the first stack structure is electrically connected to the contact point 240 on the substrate 200 through a plurality of metal wires 30, and the method of forming the metal wire 30 can be selected inversely. Wired process to execute.

In addition, in the same manufacturing process, the three crystal grains 300 with a plurality of through-silicon plugs 330 in FIG. 100 are electrically connected to form a second stack structure; since the process of forming the second stack structure is the same as the process of forming the first stack structure, the description will not be repeated. Then, the second stack structure is flip-chip, and the plurality of bumps 50 exposed on the second stack structure are respectively connected to the metal wire 30 and the plurality of bumps 50 exposed on the first stack structure, In order to form a multi-chip stack structure formed by stacking eight chips 100/300, as shown in FIG. 7 . Similarly, a polymer material filling process can also be optionally performed to form a sealing layer 80/140 in the space between the first stack structure and the second stack structure and between each crystal grain 100/300 to stabilize This multi-die stack structure. Next, an encapsulation process is performed to form an encapsulant 90 for covering the substrate 200 , the eight dies 100 / 300 and the metal wires 30 . Since the sealing layer filling process, sealing process and materials thereof are the same as those of the foregoing embodiments, the description thereof will not be repeated. Finally, solder balls (not shown in FIG. 7 ) can also be disposed on the plurality of external contacts 230 on the lower surface 220 of the substrate 200 as external electrical connection components. Obviously, when each die 100/300 in this stack structure is 1Gb DRAM, then this multi-die stack package structure becomes an 8Gb DRAM product, which can be applied in portable electronic products, For example: notebook computers, 3G mobile phones, personal digital assistants and game consoles.

In addition, it should be particularly noted that when the bumps 20 and 50 in the above-mentioned embodiments use a flexible metal as the material, such as gold, the low hardness, high toughness and good conforming coplanar properties of the flexible metal can be used, When vertically stacking multiple crystal grains, it is possible to absorb the deformation in the horizontal and vertical directions on the bonding interface of the electrodes (ie, bumps) due to the mismatch of thermal expansion coefficients between the metal electrode materials, and it can also effectively overcome the metal electrodes. The problem of roughness between materials can effectively increase the reliability of the process and products of multi-chip vertical stacking.

Next, please refer to FIG. 8A , which is a schematic cross-sectional view of the system-in-package structure formed by the multi-die stacked package structure of the present invention. First, as shown in FIG. 8A, the structure of its substrate 200 is the same as that of the substrate 200 in FIG. A groove 250 is formed inside, and the contacts 240 are located outside the die placement area, wherein the length and width of the groove 250 are larger than the length and width of the die 100 . In this embodiment, a control die 500 is placed in the groove 250 first, and the control die 500 is electrically connected to the substrate 200. The method of electrically connecting the control die 500 to the substrate 200 can be flip-chip In this way, the active surface of the control die 500 faces the substrate 200 and is electrically connected to a plurality of terminals (not shown in the figure) of the substrate 200 disposed at the bottom of the groove 250 . Alternatively, the control die 500 can be pasted in the groove 250 on the back side, and wires can be formed by bonding to electrically connect the pads on the active surface of the control die 500 to the endpoint of the substrate 200 disposed at the bottom of the groove 250. (not shown in the figure), and then, a FOW (Film-over-wire) film is laid on the active surface of the control die 500 to cover the wire (not shown in the figure). Next, a first die 100a shown in FIG. 2B is pasted on the back side of the control die 500 with its back side 103 through the adhesive layer 120 or directly on the FOW film with its back side 103 . Next, an inverse wire bonding process may be selected to electrically connect the bumps 20 a on the first die 100 a to the contacts 240 on the substrate 200 with a plurality of metal wires 30 . Obviously, when the groove 250 of the substrate 200 is properly designed, for example: after the first die 100a is pasted on the backside of the control die 500 or on the FOW film, the contact 240 on the upper surface 210 of the substrate 200 and the second The bumps 20a on a die 100a have similar heights, so that a plurality of metal wires 30 can electrically connect the contacts 240 on the substrate 200 to the bumps 20a on the first die 100a with the smallest arc and the shortest length. Connected together, it can make this multi-die stack structure have the best electrical characteristics. Then, a second crystal grain 100b identical to that shown in FIG. 2B is flip-chip connected to the bump 20b on it to the metal wire 30 and the bump on the first crystal grain 100a fixed in the groove 250. 20a to form a multi-die stack structure. Similarly, a polymer material filling process can also be optionally performed to form the sealing layer 80 between the two dies 100a, 100b to stabilize the stacked structure. Next, a sealing process is performed to form a sealing body 90 for covering the substrate 200, the first die 100a, the second die 100b and the metal wire 30, and the control die 500 and the first die 100a are in contact with the recesses. The gaps between the grooves 250 are also filled by the sealant 90 at the same time. Since the sealing layer filling process, sealing process and materials thereof are the same as those of the foregoing embodiments, the description thereof will not be repeated. Finally, solder balls 260 can also be disposed on the plurality of external contacts 230 on the lower surface 220 of the substrate 200 as external electrical connection components. Obviously, by controlling the configuration of the die 500, the multi-die stacked package structure of this embodiment forms a system-in-package (SiP), and when each die 100 is a 1Gb DRAM, the present embodiment The multi-die stacked package structure can control the access of the 2Gb DRAM by controlling the die 500, so as to achieve the characteristics of larger capacity, higher operating speed and larger bandwidth. Therefore, it can be applied in portable electronic products, such as notebook computers, 3G mobile phones, personal digital assistants and game consoles.

Next, please refer to FIG. 8B , which is a schematic cross-sectional view of another embodiment of the system-in-package structure formed by the multi-die stacked package structure of the present invention. Obviously, the only difference between FIG. 8B and FIG. 8A is that in FIG. 8B, the control die 500 is disposed in the groove 250 of the substrate 200 and electrically connected to the substrate 200, and then integrated with the four stacks. The dies 100/300 of the control die 100/300 are solidly connected into one body; the way in which the control die 500 is electrically connected to the substrate 200 and the way of being fixed to the die 100 is the same as that in FIG. 8A; in addition, the four dies 100/300 stacked into one The stacking process and structure of 300 are the same as those in FIG. 5E , so details are not repeated here. Obviously, by controlling the configuration of the die 500, the multi-die stacked package structure of this embodiment forms a system-in-package (SiP), and when each die is a 1Gb DRAM, the multiple dies of this embodiment The chip stack package structure can control the access of the 4Gb DRAM by controlling the chip 500, so as to achieve the characteristics of larger capacity, higher operating speed and larger bandwidth. Therefore, it can be applied in portable electronic products, such as notebook computers, 3G mobile phones, personal digital assistants and game consoles.

Next, please refer to FIG. 8C , which is a schematic cross-sectional view of another embodiment of the system-in-package structure formed by the multi-die stacked package structure of the present invention. FIG. 8C is the same as FIG. 8A, forming a groove 250 in the crystal grain setting area of the substrate 200, and disposing a control crystal grain 500 in the groove 250, and controlling the crystal grain 500 to form an electrical connection with the substrate 200, The manner of electrical connection between the control crystal grain 500 and the substrate 200 is the same as that of the aforementioned FIG. The gap between the grain 500 and the groove 250. After that, a multi-chip stack structure as shown in FIG. 8A is formed on the capping layer 280 . Since the process of forming the multi-chip stack structure is the same as that of the previous embodiment, it will not be described again.

Next, please refer to FIG. 8D , which is a schematic cross-sectional view of yet another embodiment of the system-in-package structure formed by the multi-die stacked package structure of the present invention. Obviously, the structure of FIG. 8D is the same as that of FIG. 8C, and the control crystal grain 500 is disposed in the groove 250; Covering and filling the gap between the control die 500 and the groove 250 ; then, forming a stack structure of four die 100/300 same as that in FIG. 8B on the covering layer 280 . Since the method of controlling the electrical connection between the die 500 and the substrate 200 is the same as that of FIG. 8A , and the process of forming the multi-die stack structure is also the same as that of the previous embodiment, the description will not be repeated.

Obviously, by controlling the configuration of the die 500, the multi-die stacked package structure of this embodiment forms a system-in-package (SiP), and when each die is a 1Gb DRAM, the multiple dies of this embodiment The chip stack package structure can control the access of 2Gb DRAM (the structure of FIG. 8C ) or 4Gb DRAM (the structure of FIG. 8D ) by controlling the chip 500, so as to achieve larger capacity, higher operating speed and larger bandwidth characteristics. Therefore, it can be applied in portable electronic products, such as notebook computers, 3G mobile phones, personal digital assistants and game consoles.

Next, please refer to FIG. 9 , which is a schematic cross-sectional view of yet another embodiment of the system-in-package structure formed by the multi-die stacked package structure of the present invention. As shown in FIG. 9, a control die 500 is pasted on the back surface 103 of the uppermost die 100 (fourth die 100b) of the multi-die stack structure in FIG. A wire bonding process electrically connects the bonding pads 510 on the control die 500 to the contacts 240 on the upper surface 210 of the substrate 200 . Therefore, this embodiment also forms a system-in-package, so the access of the 2Gb DRAM can be controlled by controlling the die 500 to achieve the characteristics of larger capacity, higher operating speed and larger bandwidth.

Next, please refer to FIG. 10A to FIG. 10D , which are schematic cross-sectional views of yet another embodiment of a multi-chip stack structure with multiple through-silicon plugs of the present invention. First, as shown in FIG. 10A , it is a schematic cross-sectional view of a die 400 with multiple TSVs of the present invention. The die 400 has an active face 401 and a back face 403 opposite to the active face 401, and a plurality of vertical through holes penetrating the active face 401 and the back face 403 are formed on the die 400, and further formed in each vertical through hole The through-silicon plug 450 is electrically connected to the active surface 401 and the back surface 403 to form a through hole and the material of the through-silicon plug 450 is the same as that of FIG. 5A . In this embodiment, the plurality of through-silicon plugs 450 form a first end 451 on the active surface 401 and a second end 453 on the back surface 403, and on the second ends 453 of some of these through-silicon plugs 450 Bumps 457 protruding from the backside 403 of the die 400 are formed, and some of the first ends 451 of the TSVs 450 also form bumps 455 protruding from the active surface 401 of the die 400 . These bumps 455 and bumps 457 can be part of the through-silicon plug 450, that is, integrally formed with the same material as the through-silicon plug 450, or can be formed on the first end of the through-silicon plug 450 with other conductive materials. 451 and the second end 453. Then, a plurality of crystal grains 400 with the same structure as in FIG. 10A are vertically stacked to form a stacked structure 400A, as shown in FIG. 10B . The stacking method in FIG. 10B is to combine the bumps 457 on the second end 453 of the plurality of through-silicon plugs 450 of each upper-layer die 400 with the plurality of through-silicon plugs 450 on the first end 451 of the lower-layer die 400. The bumps 455 are electrically connected together correspondingly. In this embodiment, four dies 400 are stacked to form a multi-die stacking structure 400A. In addition, in another embodiment, no bump 455 may be formed on the first ends 451 of the plurality of through-silicon plugs 450 of the die 400; therefore, in this embodiment, the stacking method in FIG. 10B is to The bumps 457 on the second ends 453 of the plurality of through-silicon plugs 450 of each upper die 400 are directly connected to the first ends 451 of the plurality of through-silicon plugs 450 of the lower die 400 respectively.

Next, the stack structure 400A of FIG. 10B is electrically connected to another crystal grain 600 fixed on the active surface 210 of the substrate 200, as shown in FIG. 10C; wherein, the crystal grain 600 has an active surface and an opposite a back side, and its back side is fixed in the crystal grain setting area (not shown in the figure) of the substrate 200, a plurality of welding pads 610 are arranged on the peripheral area of the active surface of the crystal grain 600, and each welding pad 610 is formed Bump 70; then the bump 70 formed on the pad 610 is electrically connected to a plurality of contacts 240 on the active surface 210 of the substrate 200 through the metal wire 30; then, the stack structure 400A and the die 600 are electrically connected The electrical connection method is to connect the bump 457 on the second end 453 of the through-silicon plug 450 of the lowest layer of the die 400 in the stack structure 400A to the metal wire 30 and the bump 70 on the die 600 respectively. A stacked structure of multiple crystal grains as shown in FIG. 10C can be formed. It should be noted that in this embodiment, the plurality of through-silicon plugs 450 located in the middle area of the die 400 can be electrically connected to the through-silicon plugs located in the peripheral area through the circuit (not shown) inside the die 400 . The die plug 450 is then correspondingly connected to the metal wire 30 and the bump 70 on the die 600 through the bump 457 formed on the through-silicon plug 450 in the peripheral region. In this embodiment, the die 600 may be a die having the same function as the die 100/300, such as DRAM; and the die 600 may also be a die having a different function from the die 100/300, for example : Flash memory (Flash Memory) or a non-functional dummy die (dummy die), and the die 600 can also be a control chip or other special-purpose chips (ASIC), such as a digital signal processor (DSP), a central Processor (CPU), microprocessor control unit (MCU), etc., the present invention is not limited to this.

Next, in this embodiment, a polymer material filling process can also be optionally performed to form the sealing layer 140 between the crystal grains 400 of the stack structure 400A, and the sealing layer 80 between the stack structure 400A and the crystal grains 600, so as to This multi-die stack structure is stabilized. Next, an encapsulation process may also be performed to form an encapsulation 90 for covering the substrate 200 , the stack structure 400A, the die 600 and the metal wire 30 . Since the sealing layer filling process, sealing process and materials thereof are the same as those of the foregoing embodiments, the description thereof will not be repeated. Finally, solder balls 260 may also be disposed on the plurality of external contacts 230 on the lower surface 220 of the substrate 200 as external electrical connection components, as shown in FIG. 10C .

In addition, the present invention can further embed a control grain 500 in the substrate 200 of FIG. 10C , as shown in FIG. 10D , wherein the method of forming the control grain 500 in the substrate 200 is the same as that of FIG. 2I , so it will not be repeated. illustrate.

Please refer to FIG. 11 again, which is a schematic cross-sectional view of yet another embodiment of the multi-die stack structure with multiple through-silicon plugs of the present invention. As shown in FIG. 11 , the combination of the stack structure 400A, the die 600 and the plurality of metal wires 30 is the same as that in FIG. 10C , but the difference lies in the substrate 200 . The structure of the substrate 200 in this embodiment is the same as that of the substrate 200 in FIG. groove 250 , and the contacts 240 are located outside the die placement area, wherein the length and width of the groove 250 are larger than the length and width of the die 600 . Obviously, after the crystal grain 600 in FIG. The bumps 70 on the pads 610 of the chip 600 are electrically connected to the contacts 240 on the substrate 200 . Obviously, when the groove 250 of the substrate 200 is properly designed, for example: the depth of the groove 250 is designed to be close to the thickness of the crystal grain 600, therefore, when the crystal grain 600 is fixed to the groove 250 of the substrate 200 The contact 240 on the upper surface 210 of the substrate 200 has a similar height to the bump 70 on the die 600, so that the plurality of metal wires 30 can connect the contact 240 on the substrate 200 to the die 600 with the smallest arc and the shortest length. The bumps 70 on the die 600 are electrically connected together, so that the multi-die stack structure has the best electrical characteristics. Since the process of forming the multi-chip stack structure is the same as that of the previous embodiment, it will not be described again. Similarly, this embodiment can also optionally perform a polymer material filling process to form sealing layers 140, 80 between the crystal grains 400 of the stack structure 400A and between the stack structure 400A and the crystal grains 600, so as to stabilize multiple Die stack structure. Next, the encapsulation process can also be performed to form an encapsulation 90 to cover the substrate 200, the stack structure 400A, the die 600 and the metal wire 30, and the gap between the die 600 and the groove 250 is also sealed at the same time. Colloid 90 is filled. Since the sealing layer filling process, sealing process and materials thereof are the same as those of the foregoing embodiments, the description thereof will not be repeated. Finally, solder balls 260 are disposed on the plurality of external contacts 230 on the lower surface 220 of the substrate 200 as external electrical connection components.

Furthermore, please refer to FIG. 12 , which is a schematic cross-sectional view of yet another embodiment of the system-in-package structure formed by the multi-die stacked package structure of the present invention. As shown in FIG. 12 , the grain stacking structure is the same as that in FIG. 11 , the difference between the two is that in this embodiment, a control grain 500 is further arranged in the groove 250 of the substrate 200, and the control grain 500 is It is electrically connected with the substrate 200 . The way in which the control die 500 is electrically connected to the substrate 200 can electrically connect the active surface of the control die 500 to multiple terminals (not shown in the figure) disposed at the bottom of the groove 250 of the substrate 200 in a flip-chip manner. connection, or paste the control die 500 in the groove 250 with the back side, and form a wire by bonding to electrically connect the pad on the active surface of the control die 500 to the end point of the substrate 200 disposed at the bottom of the groove 250 (not shown in the figure); then, a filling material can be optionally used to partially fill in the groove 250 to form a covering layer 280 to cover and fill between the control grain 500 and the groove 250 Next, a multi-die stacked package structure as shown in FIG. 12 is formed on the cover layer 280 to form a system-in-package structure.

The above descriptions are only specific embodiments of the present invention, and are not intended to limit the patent scope of the present invention; all other equivalent changes or modifications that do not deviate from the spirit disclosed by the present invention should be included in the following within the scope of the patent application.

Claims (14)

1. A multi-die stacked packaging structure, comprising: A substrate having an upper surface and a lower surface, the upper surface defines a die setting area and is configured with a plurality of contacts, and the contacts are located outside the die setting area; A first crystal grain has an active surface and a back surface opposite to the active surface, the first crystal grain is arranged in the crystal grain arrangement area with the back surface, and a plurality of first welding pads are arranged on the active surface and a first bump is formed on the first pad; A second crystal grain has an active surface, a back surface opposite to the active surface, and a plurality of through-silicon crystal plugs, and the through-silicon crystal plugs penetrate through the second crystal grain to make the gap between the active surface and the back surface are electrically connected to each other, and a plurality of second bumps are formed on the active surface to respectively connect to the through-silicon plugs. A die, so that the through-silicon plugs are respectively connected to the first bumps; a plurality of metal wires for connecting the second bumps to the contacts on the substrate; A third crystal grain has an active surface, a back surface opposite to the active surface, and a plurality of through-silicon crystal plugs, and the through-silicon crystal plugs penetrate the third crystal grain to make the gap between the active surface and the back surface are electrically connected to each other, and a plurality of third bumps are formed on the active surface to respectively connect to the through-silicon plugs, wherein the active surface of the third grain is bonded to the active surface of the second grain. The second crystal grain is such that the third bump is respectively connected to the metal wire and the second bump; A fourth crystal grain has an active surface and a back surface opposite to the active surface, a plurality of second pads are arranged on the active surface, and a fourth bump is formed on the second pads, the The fourth die is bonded to the third die with the active surface facing the back face of the third die, so that the fourth bumps respectively correspond to the through-silicon plugs connected to the third die; and A colloid is used to cover the substrate, the first crystal grain, the second crystal grain, the third crystal grain, the fourth crystal grain and the metal wire. 2. The multi-die stacked package structure according to claim 1, wherein the first bonding pad is located at the central area of the active surface of the first die and the second bonding pad is located at the second In the central area of the active surface of the four crystal grains, the through-silicon plugs are respectively arranged in the central areas of the second crystal grain and the third crystal grain. 3 . The multi-die stack package structure according to claim 1 , wherein at least one fifth bump is further disposed between the metal wire and the third bump. 4 . 4. A multi-die stack package structure, comprising: A substrate having an upper surface and a lower surface, the upper surface defines a crystal grain setting area and is configured with a plurality of contacts, a groove is formed in the crystal grain setting area, and the contacts are located outside the crystal grain setting area ; A first crystal grain has an active surface and a back surface opposite to the active surface, the first crystal grain is disposed in the groove with the back surface, a plurality of first welding pads are arranged on the active surface and forming a first bump on the first pad; A second crystal grain has an active surface, a back surface opposite to the active surface, and a plurality of through-silicon crystal plugs, and the through-silicon crystal plugs penetrate through the second crystal grain to make the gap between the active surface and the back surface are electrically connected to each other, and a plurality of second bumps are formed on the active surface to respectively connect to the through-silicon plugs. A die, so that the through-silicon plugs are respectively connected to the first bumps; a plurality of metal wires for connecting the second bumps to the contacts on the substrate; A third crystal grain has an active surface, a back surface opposite to the active surface, and a plurality of through-silicon crystal plugs, and the through-silicon crystal plugs penetrate the third crystal grain to make the gap between the active surface and the back surface are electrically connected to each other, and a plurality of third bumps are formed on the active surface to respectively connect to the through-silicon plugs, wherein the active surface of the third grain is bonded to the active surface of the second grain. The second crystal grain is such that the third bump is respectively connected to the metal wire and the second bump; A fourth crystal grain has an active surface and a back surface opposite to the active surface, a plurality of second pads are arranged on the active surface, a fourth bump is formed on the second pads, the first Four dies are bonded to the third die with the active surface facing the back face of the third die, so that the fourth bumps respectively correspond to the through-silicon plugs connected to the third die; and A colloid is used to cover the substrate, the first crystal grain, the second crystal grain, the third crystal grain, the fourth crystal grain and the metal wire. 5. The multi-die stacked package structure according to claim 4, wherein the first bonding pad is located at the central area of the active surface of the first die, and the second bonding pad is located at the first die The central area of the active surface of the four crystal grains and the through-silicon plugs are respectively arranged in the central areas of the second crystal grain and the third crystal grain. 6. The multi-die stacked package structure according to claim 4, further comprising a control die disposed in the groove and located between the first die and the substrate, the first The crystal grain is directly fixed on the control crystal grain through the back surface, and the control crystal grain is electrically connected with the substrate. 7. The multi-die stacked package structure according to claim 4, further comprising a control die disposed in the groove and between the first die and the substrate, the control die The die is covered by a cover layer, the first die is fixed on the cover layer, and the control die is electrically connected with the substrate. 8 . The multi-die stack package structure according to claim 4 , wherein at least one fifth bump is further disposed between the metal wire and the third bump. 9. A multi-die stack package structure, comprising: A substrate having an upper surface and a lower surface, the upper surface defines a die setting area and is configured with a plurality of contacts, and the contacts are located outside the die setting area; A first crystal grain has an active surface and a back surface opposite to the active surface, the first crystal grain is arranged in the crystal grain installation area with the back surface, and a plurality of first crystal grains are arranged on the peripheral area of the active surface a welding pad and a first bump is formed on the first welding pad; a plurality of metal wires for connecting the first bumps to the contacts on the substrate; A second crystal grain has an active surface and a back surface opposite to the active surface and a plurality of through-silicon crystal plugs, each of the through-silicon crystal plugs penetrates the second crystal grain to make the active surface and the back surface are electrically connected to each other, and each of the TSVs forms a first end on the active surface and a second end on the back surface, and at least part of the TSVs on the second A second bump is respectively formed on the end, wherein the second crystal grain is bonded to the first crystal grain with the back surface facing the active surface of the first crystal grain, so that the second bumps are respectively connected to the a metal wire and the first bump; A third crystal grain has an active surface, a back surface opposite to the active surface, and a plurality of through-silicon crystal plugs, each of which penetrates through the third crystal grain to make the active surface and the back surface are electrically connected to each other, and each of the TSVs forms a first end on the active surface and a second end on the back surface, and at least part of the TSVs on the second A third bump is respectively formed on the end, wherein the third crystal grain is bonded to the second crystal grain with the back face facing the active surface of the second crystal grain, so that the third bump of the third crystal grain blocks respectively corresponding to the first ends of the TSVs connected to the second die; and A colloid is used to cover the substrate, the first crystal grain, the second crystal grain, the third crystal grain and the metal wire. 10. The multi-die stacked package structure according to claim 9, wherein the second die further comprises a plurality of fourth bumps, each of the fourth bumps is formed on the second die The first end of the TSV, wherein the third bumps of the third die are electrically connected to the fourth bumps of the second die respectively. 11 . The multi-die stack package structure according to claim 9 , wherein at least one fifth bump is further disposed between the metal wire and the second bump. 12 . The multi-die stacked package structure according to claim 9 , wherein a groove is further formed in the die arrangement region, and the first die is disposed in the groove. 13 . 13. The multi-die stacked package structure according to claim 12, further comprising a control die disposed in the groove and located between the first die and the substrate, the first The crystal grain is directly fixed on the control crystal grain through the back surface, and the control crystal grain is electrically connected with the substrate. 14. The multi-die stacked package structure according to claim 12, further comprising a control die disposed in the groove and located between the first die and the substrate, the control die The die is covered by a cover layer, the first die is fixed on the cover layer, and the control die is electrically connected with the substrate.