CN102315155A - Shallow-trench isolation structure and forming method thereof as well as semiconductor structure and forming method thereof - Google Patents
Shallow-trench isolation structure and forming method thereof as well as semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN102315155A CN102315155A CN201110300726A CN201110300726A CN102315155A CN 102315155 A CN102315155 A CN 102315155A CN 201110300726 A CN201110300726 A CN 201110300726A CN 201110300726 A CN201110300726 A CN 201110300726A CN 102315155 A CN102315155 A CN 102315155A
- Authority
- CN
- China
- Prior art keywords
- layer
- insulating medium
- groove
- conductive layer
- medium layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000002955 isolation Methods 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 65
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 35
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 235000012239 silicon dioxide Nutrition 0.000 claims description 17
- 239000000377 silicon dioxide Substances 0.000 claims description 17
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 230000005855 radiation Effects 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 1
- LBDSXVIYZYSRII-IGMARMGPSA-N alpha-particle Chemical compound [4He+2] LBDSXVIYZYSRII-IGMARMGPSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Images
Landscapes
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a shallow-trench isolation structure, which comprises a semiconductor substrate, an insulating-medium layer and a conducting layer, wherein the inner part of the semiconductor substrate is provided with a groove; the insulating-medium layer is covered on the surface of the groove; and the conducting layer is positioned on the surface of the insulating-medium layer, and the conducting layer is filled in the groove. The invention also provides a method for forming the shallow-trench isolation structure. A semiconductor structure comprises a semiconductor substrate, an insulating-medium layer and a conducting layer, wherein the semiconductor substrate is provided with a groove and device areas which are positioned at both sides of the groove; the insulating-medium layer is covered on the surface of the groove; and the conducting layer is positioned on the surface of the insulating-medium layer, the conducting layer is filled in the groove, and the conducting layer is electrically connected with a low potential. The invention also provides a method for forming the semiconductor structure. Through the invention, the performance of a semiconductor device can be improved, and the generation of leakage current is avoided.
Description
Technical field
The present invention relates to semiconductor applications, particularly fleet plough groove isolation structure and forming method thereof, semiconductor structure and forming method thereof.
Background technology
(Shallow Trench Isolation STI) is a kind of isolation structure commonly used to fleet plough groove isolation structure.The principle that fleet plough groove isolation structure forms is the groove that the silicon substrate etching is corresponding with fleet plough groove isolation structure, and dielectric material is inserted in the said groove.
The active area isolation structure of MOS transistor also adopts fleet plough groove isolation structure mostly, in the patent No. is the United States Patent (USP) of US7112513, can also find more relevant informations about fleet plough groove isolation structure.
The formation method of existing nmos pass transistor comprises:
With reference to figure 1, Semiconductor substrate 100 is provided, said Semiconductor substrate 100 is silicon substrate or SOI substrate;
With reference to figure 2, in said Semiconductor substrate 100, form shallow trench 110, said shallow trench 110 is used to form the zone of nmos pass transistor around Semiconductor substrate;
With reference to figure 3, fill full said shallow trench 110 with dielectric material, form fleet plough groove isolation structure 120, the Semiconductor substrate that said fleet plough groove isolation structure 120 is centered on is mixed, form p type dopant well 130;
With reference to figure 4, in said p type dopant well 130, form source electrode 160, the drain electrode 170 of nmos pass transistor (not indicating), form grid structure 150 on p type dopant well 130 surfaces.
But in reality, find, good inadequately through the radiation resistance of the formed nmos pass transistor of said method, in radiation environment or after experiencing radiation, be easy to generate leakage current.
Summary of the invention
The problem that the present invention solves provides a kind of fleet plough groove isolation structure and forming method thereof; A kind of semiconductor structure and forming method thereof is provided, to solve existing nmos pass transistor is easy to generate leakage current in radiation environment or after the radiation problem.
For addressing the above problem, the present invention provides a kind of fleet plough groove isolation structure, comprising:
Semiconductor substrate has groove in the said Semiconductor substrate;
Cover the insulating medium layer of said groove surfaces;
Be positioned at the conductive layer of said dielectric laminar surface, said conductive layer is filled full said groove, and said conductive layer is electrically connected with electronegative potential.
Alternatively, the material of said insulating medium layer is a silicon dioxide.
Alternatively, said insulating medium layer comprises silicon dioxide layer, silicon nitride layer and the silicon dioxide layer that forms successively.
Alternatively, the width of said insulating medium layer is not less than 5nm.
Alternatively, the material of said conductive layer is a polysilicon.
Correspondingly, the present invention also provides a kind of fleet plough groove isolation structure formation method, comprising:
Semiconductor substrate is provided, has groove in the said Semiconductor substrate;
Form the insulating medium layer that covers said groove surfaces;
Form conductive layer at said dielectric laminar surface, said conductive layer is filled full said groove;
Be electrically connected said conductive layer and electronegative potential.
Alternatively, the width of said insulating medium layer is not less than 5nm.
The present invention also provides a kind of semiconductor structure, comprising:
Semiconductor substrate, said Semiconductor substrate has groove, and the device that is positioned at said groove both sides device region, and said device comprises nmos pass transistor;
Cover the insulating medium layer of said groove surfaces;
Be positioned at the conductive layer of said dielectric laminar surface, said conductive layer is filled full said groove;
Said conductive layer is electrically connected with electronegative potential.
Alternatively, the material of said insulating medium layer is a silicon dioxide.
Alternatively, said insulating medium layer comprises silicon dioxide layer, silicon nitride layer and the silicon dioxide layer that forms successively.
Alternatively, the width of said insulating medium layer is not less than 5nm.
Correspondingly, the present invention also provides a kind of semiconductor structure formation method, comprising:
Semiconductor substrate is provided, has groove in the said Semiconductor substrate, and the device region that is positioned at said groove both sides;
Form the insulating medium layer that covers said groove surfaces;
Form conductive layer at said dielectric laminar surface, said conductive layer is filled full said groove;
Be electrically connected said conductive layer and electronegative potential;
Form device at said device region, said device comprises nmos pass transistor.
Alternatively, the width of said insulating medium layer is not less than 5nm.
Compared with prior art, technical scheme of the present invention has the following advantages:
The fleet plough groove isolation structure that is provided comprises and is formed on the shallow trench surface successively, and fills the insulating medium layer and the conductive layer of full said shallow trench.In radiation environment, produce electron-hole pair in the fleet plough groove isolation structure.Wherein electrons spread is in Semiconductor substrate, and a hole part is positioned at conductive layer; Another part is positioned at insulating medium layer.The hole that is arranged in conductive layer is taken away by electronegative potential; Be accumulated in electric charge in the fleet plough groove isolation structure and only be positioned at the hole of insulating medium layer; Thereby reduced to be arranged in the quantity in the hole of fleet plough groove isolation structure; Avoided in fleet plough groove isolation structure, producing excessive electric charge accumulation, thereby avoided leakage current, said leakage current is caused by the electrical potential difference that said excessive electric charge accumulation forms;
Further, can reduce the thickness of insulating medium layer, thereby reduce the electric charge that accumulated through regulating the thickness distribution of insulating medium layer and conductive layer;
Further, the fleet plough groove isolation structure formation method technology that is provided is simple, and is integrated with existing semiconductor technology easily.
Description of drawings
Fig. 1 to Fig. 4 is the cross-sectional view of the forming process of existing nmos pass transistor;
Fig. 5 is the vertical view of existing nmos pass transistor;
Fig. 6 is the cross-sectional view of existing nmos pass transistor;
Fig. 7 is the structural representation of the fleet plough groove isolation structure that provides of embodiments of the invention;
Fig. 8 is the schematic flow sheet of the formation method of the fleet plough groove isolation structure that embodiments of the invention provided;
Fig. 9 to Figure 11 is the cross-sectional view of the fleet plough groove isolation structure forming process that provides of the embodiment of the invention;
Figure 12 is the structural representation of the semiconductor structure that provides of embodiments of the invention;
Figure 13 is the vertical view of the semiconductor structure that provides of present embodiment;
Figure 14 is the schematic flow sheet of the semiconductor structure formation method that provides of embodiments of the invention;
Figure 15 to Figure 17 is the cross-sectional view that the semiconductor structure that provides of the embodiment of the invention forms process.
Embodiment
Can know that by background technology the performance of existing nmos pass transistor in radiation environment is good inadequately, in radiation environment, produce leakage current easily.The inventor studies to the problems referred to above, thinks that the existing imperfect reason of nmos pass transistor performance is that (charged particles such as α particle, β particle, proton can directly cause material ionization in radiation; Particles such as X ray, γ photon and neutron are not charged, but with material do the time spent produce " secondary " thus make material ionization.All these phenomenons, the general designation ionising radiation is called for short radiation.The radiation meeting makes interior atom of the active area of MOS transistor and the atom generation ionization in the fleet plough groove isolation structure, produces a large amount of electron-hole pairs.The electronics that is created in the electron-hole pair in the active area can be extracted into high potential by external circuits; The hole can be extracted into electronegative potential by external circuits.Because fleet plough groove isolation structure is non-conductive, so the electronics-hole that is created in the fleet plough groove isolation structure can't be taken away through external circuits; Because electronics spreads soon,, and be extracted into high potential again in insulating medium layer through external circuits so the electronics in the electron-hole pair that is produced can be diffused in Semiconductor substrate or the active area; And the diffusion velocity in hole is slow, so can be accumulated in the insulating medium layer of fleet plough groove isolation structure, the hole that is accumulated causes leakage current.
Particularly; Fig. 5 is the nmos pass transistor shown in Figure 4 and the vertical view of fleet plough groove isolation structure, and is as shown in Figure 5, because fleet plough groove isolation structure 120 is around said nmos pass transistor; So be accumulated in the source electrode 160 of the hole meeting pair nmos transistor of fleet plough groove isolation structure, the p type dopant well generation high potential between the drain electrode 170; Make p type dopant well that transoid or weak transoid take place on the shallow trench sidewall, thereby cause the leakage current between the leakage of source, the direction shown in the arrow I is the possible direction of said leakage current among Fig. 5; The direction of said leakage current possibly be from the source electrode to the drain electrode, also possibly be from drain-to-source.
Fig. 6 is the nmos pass transistor that on the SOI substrate, the forms cross section along A-A line among Fig. 5; Said SOI substrate comprises bottom conductive layer 610; Buried oxide layer 620 and top silicon layer 630; Be formed with the fleet plough groove isolation structure 640 that is used to isolate nmos pass transistor in the said top silicon layer 630, said top silicon layer 630 surfaces are formed with the grid 650 of nmos pass transistor, and said leakage current occurs in the isolation structure 640 shown in Fig. 6 and top silicon layer 630 at the interface.
The inventor provides a kind of fleet plough groove isolation structure and forming method thereof in an embodiment of the present invention through further research.In order further to illustrate spirit of the present invention and essence, combine embodiment and accompanying drawing that the present invention is done detailed description hereinafter.
Fig. 7 is the structural representation of the fleet plough groove isolation structure that provides of embodiments of the invention, and the fleet plough groove isolation structure that embodiments of the invention provided comprises:
Cover the insulating medium layer 210 of said groove surfaces;
Be positioned at the conductive layer 220 on said insulating medium layer 210 surfaces, said conductive layer 220 is filled full said groove, and said conductive layer 220 links to each other with electronegative potential through the interconnection structure (not shown).
In the present embodiment, said Semiconductor substrate 200 is silicon substrate or SOI substrate, perhaps silicon-Germanium substrate.
In the present embodiment, the material of said insulating medium layer 210 is a silicon dioxide.Can carry out accommodation according to application or equipment disposition in other embodiments, such as ON (silicon dioxide-silicon nitride) or ONO (silicon dioxide-silicon nitride-silicon dioxide) structure etc.
The width d of said insulating medium layer 210 can regulate according to arts demand, and what need satisfy is that said insulating medium layer 210 can effectively be isolated the device that is formed on the groove both sides.In the present embodiment, the width d of said insulating medium layer 210 is not less than 5nm.If the width of said insulating medium layer 210 is too small, possibly can't effectively isolate the device that is formed on the groove both sides, perhaps in two devices that face mutually, produce excessive parasitic capacitance; The width of said insulating medium layer 210 is excessive, can increase the positive charge that accumulates in the fleet plough groove isolation structure.
The material of said conductive layer 220 can be polysilicon or other electric conducting materials.Said conductive layer is electrically connected through interconnection structure and electronegative potential, and in the present embodiment, said electronegative potential is an earth potential.
In the present embodiment, under radiation environment, in fleet plough groove isolation structure, can produce a large amount of electron-hole pairs, an electron-hole pair part that is produced is accumulated in insulating medium layer 210, and a part is accumulated in conductive layer 220.Wherein be accumulated in electrons spread in the conductive layer 220 in Semiconductor substrate 200, the hole that is accumulated in conductive layer 220 is through being pumped to outside electronegative potential; The electrons spread ability that is accumulated in the insulating medium layer 210 is relatively good, can be diffused in the Semiconductor substrate 200, because the diffusivity of hole in insulating medium layer 210 is poor, can be accumulated in the insulating medium layer of fleet plough groove isolation structure.The thickness of insulating medium layer is very little, can reduce so be accumulated in the quantity in the hole of fleet plough groove isolation structure but because in the present embodiment.
Particularly, in the present embodiment, because the existence of conductive layer 220; Make the thickness of insulating medium layer 210 reduce significantly; Particularly under the big situation of fleet plough groove isolation structure width, it is more obvious that the thickness of insulating medium layer 210 reduces amplitude, and can not accumulate positive charge in the conductive layer 220.Because the thickness of insulating medium layer 210 reduces, the positive charge number that is accumulated in the fleet plough groove isolation structure insulating medium layer 210 is reduced, thereby the leakage current that the fleet plough groove isolation structure two side that embodiments of the invention are provided produces reduce or disappear.
Correspondingly, the present invention also provides a kind of fleet plough groove isolation structure formation method, and Fig. 8 is the schematic flow sheet of the fleet plough groove isolation structure formation method that embodiments of the invention provided,
Comprise:
Step S101 provides Semiconductor substrate, has groove in the said Semiconductor substrate;
Step S102 forms the insulating medium layer that covers said groove surfaces;
Step S103 forms conductive layer at said dielectric laminar surface, and said conductive layer is filled full said groove;
Step S104 is electrically connected said conductive layer and electronegative potential.
Fig. 9 to Figure 11 is the cross-sectional view of the fleet plough groove isolation structure forming process that provides of the embodiment of the invention.
Please refer to Fig. 9; Semiconductor substrate 300 is provided; Said Semiconductor substrate 300 surfaces are formed with cushion oxide layer 340 and hard mask layer 350 successively, the said hard mask layer of etching 350, cushion oxide layer 340 and Semiconductor substrate 300 successively, formation groove 310 said Semiconductor substrate 300 in.
In the present embodiment, said Semiconductor substrate 300 is silicon substrate or SOI substrate, perhaps silicon-Germanium substrate.The width of said groove 310 and the degree of depth can be regulated according to arts demand.
Please refer to Figure 10, adopt chemical vapor deposition method to form the insulating medium layer 320 on the said groove of covering 310 surfaces, said insulating medium layer 320 also is formed on hard mask layer 350 surfaces.
In the present embodiment, the structure of said insulating medium layer 320 is ONO structures.It is that the dielectric constant of silicon nitride material is bigger, can under the situation of same dielectric dielectric layer 320 width, realize better insulation effect that said insulating medium layer 320 adopts the benefit of ONO structure.In other embodiments of the invention, the material of said insulating medium layer 320 can also be a silicon dioxide, perhaps other dielectric materials.The width of said insulating medium layer 320 can be regulated according to arts demand, and what need satisfy is that said insulating medium layer 320 can effectively be isolated the device that is formed on the groove both sides.In the present embodiment, the width of said insulating medium layer 320 is not less than 5nm.
With reference to Figure 11; Form the conductive layer 330 of filling full said groove on said insulating medium layer 320 surfaces; Then said conductive layer 330 is carried out planarization,, form the fleet plough groove isolation structure that constitutes by conductive layer 330 and insulating medium layer 320 until exposing said Semiconductor substrate 300.
The material of said conductive layer 330 can be selected any one electric conducting material.In the present embodiment; The material of said conductive layer 330 is polysilicons; Formation technology is chemical vapor deposition method, in subsequent technique, also comprises said conductive layer 330 is mixed, and said doping can be that the n type mixes; Also can be that the p type mixes, the concentration of doping can be regulated according to arts demand.
Because the existence of conductive layer 330 makes the thickness of insulating medium layer 320 reduce significantly, particularly under the big situation of fleet plough groove isolation structure width, it is more obvious that the thickness of insulating medium layer 320 reduces amplitude, and can not accumulate positive charge in the conductive layer 330.Because the thickness of insulating medium layer 320 reduces, the positive charge number that is accumulated in the fleet plough groove isolation structure insulating medium layer 320 is reduced, thereby the leakage current that the fleet plough groove isolation structure two side that embodiments of the invention are provided produces reduce or disappear.
After forming conductive layer 330, form the interconnection structure (not shown), conductive layer is electrically connected with electronegative potential through said interconnection structure on said conductive layer 330 surfaces.
In the present embodiment, said electronegative potential is an earth potential.
The fleet plough groove isolation structure formation method technology that the embodiment of the invention provided is simple, and efficient is high.
The present invention also provides a kind of semiconductor structure, and Figure 12 is the structural representation of the semiconductor structure that provides of embodiments of the invention,
Comprise:
Cover the insulating medium layer 410 of said groove surfaces;
Be positioned at the conductive layer 420 on said insulating medium layer 410 surfaces, said conductive layer 420 is filled full said groove, and said conductive layer 420 is electrically connected with electronegative potential.
In the present embodiment, said insulating medium layer 410 is ONO structures, comprises the silicon dioxide layer, silicon nitride layer and the silicon dioxide layer that form successively.
Among other embodiment, the material of said insulating medium layer 410 can also be a silicon dioxide.
The width d of said insulating medium layer 410 is not less than 5nm.
Said conductive layer 420 is electrically connected with outside electronegative potential through interconnection structure.
In the present embodiment, said device region B is formed with the nmos pass transistor (not shown), and Figure 13 is the vertical view of the semiconductor structure that provides of present embodiment.Under the effect of radiation; Can be at nmos pass transistor; And form electron-hole pair in the fleet plough groove isolation structure of forming by insulating medium layer 410 and conductive layer 420, and wherein being created in the interior electronics of nmos pass transistor and being extracted into high potential by external circuits, the hole is extracted into electronegative potential by external circuits.Electrons spread in the fleet plough groove isolation structure is to Semiconductor substrate 400; Hole part in the fleet plough groove isolation structure is positioned at conductive layer 420; Another part is positioned at insulating medium layer 410, and the hole that is positioned at conductive layer 420 is pumped to electronegative potential through interconnection structure.Because the existence of conductive layer 420; The thickness of insulating medium layer 410 reduces significantly; Particularly under the big situation of fleet plough groove isolation structure width, it is more obvious that the thickness of insulating medium layer 410 reduces amplitude, because the thickness of insulating medium layer 410 reduces; The positive charge number that is accumulated in the fleet plough groove isolation structure insulating medium layer 410 is reduced, thereby the interior leakage current of semiconductor structure that embodiments of the invention are provided reduce or disappear.
In other embodiments of the invention, the device that is formed on device region A and device region B can also be other semiconductor device.
Correspondingly, the present invention also provides a kind of semiconductor structure formation method, and Figure 14 is the schematic flow sheet of the semiconductor structure formation method that provides of embodiments of the invention, comprising:
Step S201 provides Semiconductor substrate, has groove in the said Semiconductor substrate, and the device region that is positioned at said groove both sides;
Step S202 forms the insulating medium layer that covers said groove surfaces;
Step S203 forms conductive layer at said dielectric laminar surface, and said conductive layer is filled full said groove;
Step S204 is electrically connected said conductive layer and electronegative potential;
Step S205 forms device at said device region, and said device comprises nmos pass transistor.
Figure 15 to Figure 17 is the cross-sectional view that the semiconductor structure that provides of the embodiment of the invention forms process.
With reference to Figure 15; Semiconductor substrate 500 is provided; Form cushion oxide layer 540 and hard mask layer 550 successively on said Semiconductor substrate 500 surfaces; The said hard mask layer of etching 550, cushion oxide layer 540 and Semiconductor substrate 500 form groove 510 in Semiconductor substrate 500 successively, and the device region C and the device region D that are positioned at said groove 510 both sides.
Said Semiconductor substrate 500 is existing silicon substrate or SOI substrate, and said groove 510 is used to form fleet plough groove isolation structure.
With reference to Figure 16, adopt chemical vapor deposition method to form the insulating medium layer 520 on the said groove of covering 510 surfaces.
In the present embodiment, the structure of said insulating medium layer 520 is ONO structures, and the width d of said insulating medium layer 520 is not less than 5nm.Said edge dielectric layer 520 is used to isolate the device that is formed on groove 510 both sides.
With reference to Figure 17; Adopt chemical vapor deposition method to form the conductive layer 530 of filling full said groove on said insulating medium layer 520 surfaces; And said conductive layer 530 carried out planarization; Until exposing said Semiconductor substrate 500, form the fleet plough groove isolation structure that constitutes by said conductive layer 530 and insulating medium layer 520.
In the present embodiment, the material of said conductive layer 530 is polysilicons.
Said insulating medium layer 520 constitutes fleet plough groove isolation structure with conductive layer 530.
After forming fleet plough groove isolation structure, form the interconnection structure (not shown) on conductive layer 530 surfaces, conductive layer 530 connects electronegative potential through said interconnection structure, such as earth potential.
Device region C and device region D in said fleet plough groove isolation structure both sides form device.
Formed device can be selected according to arts demand, and in the present embodiment, formed device comprises nmos pass transistor.
To sum up, technical scheme of the present invention has the following advantages:
The fleet plough groove isolation structure that provides comprises and is formed on the shallow trench surface successively, and fills the insulating medium layer and the conductive layer of full said shallow trench.In radiation environment, produce electron-hole pair in the fleet plough groove isolation structure.Wherein electrons spread is in Semiconductor substrate, and a hole part is positioned at conductive layer; Another part is positioned at insulating medium layer.The hole that is arranged in conductive layer is taken away by electronegative potential; Be accumulated in electric charge in the fleet plough groove isolation structure and only be positioned at the hole of insulating medium layer; Thereby reduced to be arranged in the quantity in the hole of fleet plough groove isolation structure; Avoided in fleet plough groove isolation structure, producing excessive electric charge accumulation, thereby avoided leakage current, said leakage current is caused by the electrical potential difference that said excessive electric charge accumulation forms;
Further, can reduce the thickness of insulating medium layer, thereby reduce the electric charge that accumulated through regulating the thickness distribution of insulating medium layer and conductive layer;
Further, the fleet plough groove isolation structure formation method technology that is provided is simple, and is integrated with existing semiconductor technology easily.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (13)
1. fleet plough groove isolation structure, comprising: Semiconductor substrate has groove in the said Semiconductor substrate; It is characterized in that, also comprise:
Cover the insulating medium layer of said groove surfaces;
Be positioned at the conductive layer of said dielectric laminar surface, said conductive layer is filled full said groove, and said conductive layer is electrically connected electronegative potential.
2. according to the described fleet plough groove isolation structure of claim 1, it is characterized in that the material of said insulating medium layer is a silicon dioxide.
3. according to the described fleet plough groove isolation structure of claim 1, it is characterized in that said insulating medium layer comprises silicon dioxide layer, silicon nitride layer and the silicon dioxide layer that forms successively.
4. according to the described fleet plough groove isolation structure of claim 1, it is characterized in that the width of said insulating medium layer is not less than 5nm.
5. according to the described fleet plough groove isolation structure of claim 1, it is characterized in that the material of said conductive layer is a polysilicon.
6. a fleet plough groove isolation structure formation method is characterized in that, comprising:
Semiconductor substrate is provided, has groove in the said Semiconductor substrate;
Form the insulating medium layer that covers said groove surfaces;
Form conductive layer at said dielectric laminar surface, said conductive layer is filled full said groove;
Be electrically connected said conductive layer and electronegative potential.
7. according to the described fleet plough groove isolation structure of claim 6 formation method, it is characterized in that the width of said insulating medium layer is not less than 5nm.
8. semiconductor structure comprises: Semiconductor substrate, and said Semiconductor substrate has groove, and the device that is positioned at said groove both sides device region, and said device comprises nmos pass transistor; It is characterized in that, also comprise:
Cover the insulating medium layer of said groove surfaces;
Be positioned at the conductive layer of said dielectric laminar surface, said conductive layer is filled full said groove, and said conductive layer is electrically connected with electronegative potential.
9. according to the described semiconductor structure of claim 8, it is characterized in that the material of said insulating medium layer is a silicon dioxide.
10. according to the described semiconductor structure of claim 8, it is characterized in that said insulating medium layer comprises silicon dioxide layer, silicon nitride layer and the silicon dioxide layer that forms successively.
11., it is characterized in that the width of said insulating medium layer is not less than 5nm according to the described semiconductor structure of claim 8.
12. a semiconductor structure formation method is characterized in that, comprising:
Semiconductor substrate is provided, has groove in the said Semiconductor substrate, and the device region that is positioned at said groove both sides;
Form the insulating medium layer that covers said groove surfaces;
Form conductive layer at said dielectric laminar surface, said conductive layer is filled full said groove;
Be electrically connected said conductive layer and electronegative potential;
Form device at said device region, said device comprises nmos pass transistor.
13. the semiconductor structure formation method according to claim 12 is characterized in that the width of said insulating medium layer is not less than 5nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110300726.3A CN102315155B (en) | 2011-09-28 | 2011-09-28 | Fleet plough groove isolation structure and forming method thereof, semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110300726.3A CN102315155B (en) | 2011-09-28 | 2011-09-28 | Fleet plough groove isolation structure and forming method thereof, semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102315155A true CN102315155A (en) | 2012-01-11 |
| CN102315155B CN102315155B (en) | 2016-06-08 |
Family
ID=45428179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110300726.3A Active CN102315155B (en) | 2011-09-28 | 2011-09-28 | Fleet plough groove isolation structure and forming method thereof, semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102315155B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9584744B2 (en) * | 2015-06-23 | 2017-02-28 | Semiconductor Components Industries, Llc | Image sensors with voltage-biased trench isolation structures |
| CN107731732A (en) * | 2017-11-03 | 2018-02-23 | 上海新储集成电路有限公司 | A kind of deep trench isolation structure |
| CN108511476A (en) * | 2018-05-25 | 2018-09-07 | 德淮半导体有限公司 | Back side illumination image sensor and forming method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59150465A (en) * | 1983-01-31 | 1984-08-28 | Toshiba Corp | Semiconductor device and its manufacturing method |
| KR100568028B1 (en) * | 2003-09-30 | 2006-04-05 | 동부아남반도체 주식회사 | Semiconductor device isolation structure and method |
| CN101013708A (en) * | 2006-01-31 | 2007-08-08 | 精工爱普生株式会社 | Semiconductor device and manufacturing method thereof |
| CN101170074A (en) * | 2007-11-13 | 2008-04-30 | 北京大学 | A Method of Improving the Anti-irradiation Characteristics of Ultra-deep Submicron MOSFET |
-
2011
- 2011-09-28 CN CN201110300726.3A patent/CN102315155B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59150465A (en) * | 1983-01-31 | 1984-08-28 | Toshiba Corp | Semiconductor device and its manufacturing method |
| KR100568028B1 (en) * | 2003-09-30 | 2006-04-05 | 동부아남반도체 주식회사 | Semiconductor device isolation structure and method |
| CN101013708A (en) * | 2006-01-31 | 2007-08-08 | 精工爱普生株式会社 | Semiconductor device and manufacturing method thereof |
| CN101170074A (en) * | 2007-11-13 | 2008-04-30 | 北京大学 | A Method of Improving the Anti-irradiation Characteristics of Ultra-deep Submicron MOSFET |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9584744B2 (en) * | 2015-06-23 | 2017-02-28 | Semiconductor Components Industries, Llc | Image sensors with voltage-biased trench isolation structures |
| CN107731732A (en) * | 2017-11-03 | 2018-02-23 | 上海新储集成电路有限公司 | A kind of deep trench isolation structure |
| CN108511476A (en) * | 2018-05-25 | 2018-09-07 | 德淮半导体有限公司 | Back side illumination image sensor and forming method thereof |
| CN108511476B (en) * | 2018-05-25 | 2021-01-01 | 德淮半导体有限公司 | Backside illuminated image sensor and method of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102315155B (en) | 2016-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7666751B2 (en) | Method of forming a high capacitance diode and structure therefor | |
| CN101312211B (en) | Semiconductor device and manufacturing method thereof | |
| US7521741B2 (en) | Shielding structures for preventing leakages in high voltage MOS devices | |
| CN203205426U (en) | Lateral transistor | |
| US7928508B2 (en) | Disconnected DPW structures for improving on-state performance of MOS devices | |
| US5557135A (en) | Semiconductor device with field shield isolation structure and a method of manufacturing the same | |
| US9865716B2 (en) | System and method for a vertical tunneling field-effect transistor cell | |
| US20230207463A1 (en) | Semiconductor structure and method for forming same | |
| JP7383760B2 (en) | semiconductor equipment | |
| US8921202B2 (en) | Semiconductor device and fabrication method thereof | |
| CN102804376A (en) | Charging protection device | |
| US10283622B1 (en) | Extended drain transistor on a crystalline-on-insulator substrate | |
| JP2014203851A (en) | Semiconductor device and manufacturing method of the same | |
| CN108288645A (en) | High voltage device and method for manufacturing the same | |
| CN102315155B (en) | Fleet plough groove isolation structure and forming method thereof, semiconductor structure and forming method thereof | |
| CN103022131A (en) | Semiconductor device | |
| JP4232645B2 (en) | Trench lateral semiconductor device and manufacturing method thereof | |
| US9231081B2 (en) | Method of manufacturing a semiconductor device | |
| CN102299152A (en) | Double-conduction semiconductor assembly and manufacturing method thereof | |
| CN104425344A (en) | Semiconductor structure and forming method thereof | |
| CN102208449A (en) | Silicon-on-insulator (SOI) body contact metal oxide semiconductor (MOS) transistor and forming method thereof | |
| Cham et al. | A study of the trench surface inversion problem in the trench CMOS technology | |
| CN117747612B (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN107731732A (en) | A kind of deep trench isolation structure | |
| JP2008016726A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140408 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140408 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |