CN102299710A - Phase Locked Loop with Improved Phase Detection Mechanism - Google Patents

Abstract

The invention discloses a phase-locked loop (PLL) with an improved phase detection mechanism, which comprises a Phase Frequency Detector (PFD), a controller, a digital-to-analog conversion (D2A) module and a voltage control oscillator/current control oscillator (VCO/ICO), wherein the PFD has a reference signal input and an input of an output signal from the VCO/ICO and is connected to the controller, then the controller is further connected to a D2A module, and the D2A module converts a control signal from the controller into an analog voltage to control the frequency and the phase of the VCO/ICO. It is noted that the PFD of the present invention has a novel phase detection mechanism, so that the phase detection does not require edge alignment. In addition, the improved phase detection mechanism also provides for an elastic reference signal input as a fixed external source relative to, for example, a crystal.

Description

Phase Locked Loop with Improved Phase Detection Mechanism

technical field

The invention relates to a phase-locked loop, in particular to a phase-locked loop with an improved phase detection mechanism.

Background technique

Phase-locked loop (PLL) is a frequency control system, generally used in a wide range of circuit design, including clock generation, clock recovery, spread spectrum, de-skew, clock distribution, jitter and noise reduction , frequency synthesis, etc. The operation of the PLL is based on the phase difference between the input signal and the feedback from a voltage controlled oscillator (VCO). PLL is widely used as a clock generator in electronic devices, and supports high-speed transmission protocols, such as USB 2.0, as an important component for synchronization of data transmission. Figure 1 shows a schematic diagram of a conventional PLL. As shown in FIG. 1 , a conventional PLL includes a phase frequency detector (phase frequency detector, PFD) 101 , a loop filter 102 , a VCO 103 and a divider 104 . As shown in FIG. 1, the PFD 101 receives a reference signal 110 and a feedback signal 104a from the divider 104, and outputs a control signal 101a. The control signal 101a indicates whether the feedback signal lags or leads the reference signal. The loop filter 102 converts the control signal 101a into a voltage signal 102a for use by the VCO 103 as a bias voltage. The VCO 103 oscillates faster or slower according to the voltage signal 102a to generate an output signal 103a. The output signal 103a is also fed into the divider 104 to become the feedback signal 104a before being fed into the PFD 101. In this way, PLLs can generate stable output signals, which is why PLLs are widely used as clock generators, among other applications. In the clock generator, the output signal 103a is the clock provided to the remaining circuits in the electronic device to further control and synchronize the operation of the electronic device.

However, in a conventional PLL, the reference signal 110 usually comes from a fixed external source, such as a crystal capable of generating a clock, as shown in FIG. 1 . The final output signal 103a is typically the signal at the resonant frequency of the external crystal. For example, for a PLL used in a USB 2.0 application, a 480MHz clock rate can be generated by using a 12MHz crystal as the source of the reference signal 110 .

Generally, the phase-frequency detectors commonly used in conventional PLL designs rely on the relative timing, ie, phase, of the edges of the feedback signal and the reference signal. At this time, when the two signals are of the same frequency, a fixed output proportional to the phase difference is produced. On the other hand, using a gate-based phase detector in a PLL provides the advantage of quickly forcing the VCO to synchronize to the reference signal even if the reference signal is substantially different from the initial output frequency of the VCO. Figure 2 shows the traditional phase detection mechanism based on edge alignment. This edge alignment imposes limitations on certain applications, such as high speed applications.

Another limitation of traditional phase-frequency detectors is the need for a fixed external source. This not only increases the cost of the electronic device, but also hinders the flexibility of the design. Therefore, it would be advantageous to create an improved phase detection mechanism for flexible PLL design and reduced manufacturing cost.

Contents of the invention

The present invention has been used to overcome the disadvantages of conventional PLL designs described above. The main purpose of the present invention is to provide an improved phase detection mechanism which can make the phase detection flexible and applicable to high speed applications.

Another object of the present invention is to provide a PLL with an improved phase detection mechanism to provide flexible reference signals and eliminate separate reference signal sources, thereby reducing manufacturing cost and complexity.

To achieve the above object, the present invention provides a PLL with an improved phase detection mechanism, including a phase frequency detector (PFD), a controller, a digital-to-analog conversion (D2A) module, and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO) , where the PFD has a reference signal input and an input from the VCO/ICO output signal, and is connected to the controller, and then the controller is further connected to the D2A module, and the D2A module converts the control signal from the controller into an analog voltage to control the VCO/ICO ICO frequency and phase.

The beneficial effect of the present invention is that the PFD of the present invention has an improved phase detection mechanism, so that the phase detection does not depend on edge alignment. In addition, the improved phase detection mechanism also provides a flexible reference signal input as relative to a fixed external source, such as a crystal.

The above and other objects, characteristics, characteristics and advantages of the present invention will become better understood by carefully studying the following detailed description and referring to the accompanying drawings as appropriate.

Description of drawings

Figure 1 shows a schematic diagram of a conventional phase-locked loop (PLL);

Figure 2 shows a schematic diagram of a traditional phase detection based on edge alignment;

FIG. 3 shows a schematic diagram of a first exemplary waveform of improved phase detection according to the present invention;

FIG. 4 shows a schematic diagram of a second exemplary waveform of improved phase detection according to the present invention; and

Figure 5 shows a schematic diagram of a phase-locked loop (PLL) with an improved phase detection mechanism.

Wherein, the reference signs are explained as follows:

101 Phase Frequency Detector (PFD)

101a control signal

102 loop filter

102a voltage signal

103 Voltage Controlled Oscillator (VCO)

103a output signal

104 divider

104a feedback signal

110 reference signal

501 Phase Frequency Detector (PFD)

502 controller

503 digital-to-analog conversion (D2A) module

504 Voltage Controlled Oscillator/Current Controlled Oscillator (VCO/ICO)

504a output signal

510 reference signal input

A signal

Ad delay signal

B1 signal

B2 signal

Detailed ways

The PLL of the present invention uses an improved phase detection mechanism. As mentioned above, conventional phase-frequency detectors often use a fixed external source, such as a crystal, as a reference signal. The final output signal of the PLL is usually the resonance of the reference signal. For example, in USB 2.0, a 480MHz clock rate can be obtained from a fixed external 12MHz crystal as a reference clock source.

The improved phase detection mechanism does not require a fixed external source. Instead, according to the phase detection mechanism of the PLL of the present invention, the reference signal and the VCO output signal are analyzed before generating the control signal to the controller. The final output signal is related to the reference signal, but not necessarily a resonance of the frequency of the reference signal. How to analyze the reference signal and the output signal in the phase detection according to the present invention will be described below.

FIG. 3 shows a schematic diagram of a first exemplary waveform for improving phase detection according to the present invention. For simplicity, the waveform used in this exemplary embodiment is a regular periodic waveform, ie a series of 1, 0, 1, 0, 1, 0, . . . . As shown in FIG. 3 , the first waveform is marked as A, ie, signal A, and the second waveform is a delayed signal Ad, ie, a waveform having the same phase as signal A but with a delayed phase. A third waveform, shown as signal B1, has a frequency that is higher than half the frequency of signal A. For simplicity, signal A can be considered as the signal observed by signal B by the observer. As shown in Figure 3, if both the signal A and the delayed signal Ad are sampled at the rising edge of the signal B1, four different pairs of numbers can be observed, namely (1, 1), (1, 0), (0 , 0) and (0, 1), wherein the first item in each pair is the level of the signal A, and the second item is the level of the delayed signal Ad. Furthermore, it can be observed that (1,1)->(1,0), (1,0)->(0,0), (0,0)->(0,1), (0,1)- >(1,1) transition. That is, when the observer frequency is higher than half of the observed frequency, any combination of the above four transitions can be observed, that is, (1,1)->(1,0), (1,0)-> (0, 0), (0, 0) -> (0, 1), (0, 1) -> (1, 1). Similarly, the fourth waveform shows that signal B2 has a frequency lower than half the frequency of signal A. If both the signal A and the delayed signal Ad are sampled on the rising edge of the fourth waveform (that is, the signal B2), then four different pairs of numbers can be observed, namely (1,1), (1,0), ( 0, 0), (0, 1), where the first item in each pair is the level of the signal A, and the second item is the level of the delayed signal Ad. Furthermore, it can be observed that (1,1)->(0,1), (0,1)->(0,0), (0,0)->(1,0), (1,0)- >(1,1) transition. That is, when the observer frequency is less than half of the observed frequency, any combination of the above four transitions can be observed, that is, ((1,1)->(0,1), (0,1)- >(0,0), (0,0)->(1,0), (1,0)->(1,1). The observation of the demonstration waveform shows that (1,1)->(1,0 ), (1, 0) -> (0, 0), (0, 0) -> (0, 1), (0, 1) -> (1, 1) transitions imply that the frequency of the observer, such as Signal B1 is faster than half of the observed frequency, such as signal A, and (1,1)->(0,1), (0,1)->(0,0), (0,0)- The transition of >(1,0), (1,0)->(1,1) implies that the frequency of the observer, such as signal B2, is slower than half of the observed frequency, such as signal A.

FIG. 4 shows a schematic diagram of a second exemplary waveform for improving phase detection according to the present invention. The exemplary waveforms are generalized to show that observations of the transition pattern of FIG. 3 can also be extended to irregular or non-periodic observer waveforms, namely signal B1 and signal B2. As shown in FIG. 4, the first waveform is the signal A, and the second waveform is the delayed signal Ad. The third waveform shows that the observer signal B1 has a frequency higher than half that of signal A. If both the signal A and the delayed signal Ad are sampled on the rising edge of the observer signal B1, it can be observed that (1, 0), (0, 0), (0, 1), (1, 1), (1, 0), (0, 0)... a sequence. Again, four different types of transitions can be observed at different positions in the sequence of observed pairs, namely (1,1)->(1,0), (1,0)->(0, 0), (0, 0) -> (0, 1), (0, 1) -> (1, 1). Similarly, the fourth waveform shows that observer signal B2 has a frequency less than half that of signal A. If both the signal A and the delayed signal Ad are sampled on the rising edge of the fourth waveform (that is, the observer signal B2), it is observed that (1,1), (0,1), (0,0), (1, 0), (1, 1), (0, 1).... And similarly, four different types of transitions can be observed at different positions in the above-mentioned sequence of observed pairs, that is, (1,1)->(0,1), (0,1)->(0 , 0), (0, 0) -> (1, 0), (1, 0) -> (1, 1). Thus, even when the observer signal has a non-periodic and irregular waveform, the occurrence of transitions can be used to indicate the relative frequency between the observed signal and the observer signal.

The result summarized from the above two examples is that the relationship between the observed signal and the observer signal can be detected by observing the transitions found in the train of observed signal pairs. When the observer frequency is higher than half of the observed frequency, such as B1>A in the above example, four different types of transitions can be found in the series of observed pairs, that is, (1,1)->( 1,0), (1,0)->(0,0), (0,0)->(0,1), (0,1)->(1,1). On the other hand, when the observer frequency is lower than half of the observed frequency, such as B2<A in the above case, four different types of transitions can be found in the series of observed pairs, namely (1, 1)->(0,1), (0,1)->(0,0), (0,0)->(1,0), (1,0)->(1,1). All other transitions, such as (1,1)->(0,0), (1,0)->(0,1), or vice versa, can be safely discarded without affecting the detection mechanism .

This detection of the transition pattern of the observed signal and the relationship between the observer and the relative frequency of the observed signal has two important implications. The first implication is that phase detection is no longer required to align the edges of the difference signal between the reference signal and the VCO/ICO output signal prior to comparison. This is very important because edge alignment imposes a difficult constraint on phase detection for high speed applications. A second implication is that the reference signal no longer needs to be a fixed external source, such as a crystal. Instead, the reference signal can be any series of digital signals, and the improved phase detection mechanism can perform the necessary phase detection operations for the PLL. Using the improved phase detection mechanism, the PFD can easily output a signal representing the relationship between the observed frequency and the observer frequency according to the transition pattern found in the observed signal pair train.

Therefore, FIG. 5 shows a schematic diagram of a phase-locked loop (PLL) with an improved phase detection mechanism according to the present invention. As shown in FIG. 5 , the PLL of the present invention includes a phase frequency detector (PFD) 501 , a controller 502 , a digital-to-analog conversion (D2A) module 503 and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO) 504 . PFD 501 has a reference signal input 510 and an input of output signal 504a from VCO/ICO 504 and is connected to controller 502. Then the controller 502 is further connected to the D2A module 503, and the D2A module 503 converts the control signal from the controller 502 into an analog voltage or current to control the frequency and phase of the VCO/ICO 504. It is worth noting that the PFD 501 of the present invention has an improved phase detection mechanism based on the exemplary waveforms of FIGS. 3 and 4 . Thus, PFD 501 compares VCO output signal 504a with reference signal 510 to generate a signal indicative of whether the VCO output signal is faster or slower in frequency than the reference signal. According to the signal received from the PFD 501, the controller 502 controls the D2A module 503 to output analog voltage or current, and then controls the frequency and phase of the output signal 504a of the VCO/ICO 504.

It is worth noting that when the reference signal 510 stops or disappears, the controller 502 will maintain the original signal before stopping the reference signal 510, that is, keep the control signal sent to the D2A module 503, so that the D2A module 503 will not The analog voltage/current output to the VCO/ICO is changed to change the frequency and phase of the output signal 504a. In other words, the output signal 504a is maintained, ie locked, until the reference signal 510 occurs again. In this way, the PFD can switch to a different reference signal as the basis for phase detection comparison. An exemplary embodiment to implement "locking" is to implement the D2A module 503 with a counter or any equivalent mechanism that can be incremented and decremented so that signals representing faster or slower frequencies can be Increase or decrease the value. When the reference signal 510 disappears, the counter or any equivalent mechanism holds the value such that no increment or decrement operation is performed to change the held value.

The main application of the PLL with improved phase detection mechanism of the present invention is an electronic device such as USB 2.0, which can use the data stream from a host computer such as a personal computer (PC) as a reference signal for synchronization.

It is also worth noting that the improved phase detection mechanism can be further extended to include more than one delay signal in order to speed up convergence when the difference between the observer frequency and the observed frequency is very large. For example, a second delayed signal A' with a slight phase delay, a third delayed signal A" with a greater phase delay, etc., can be added so that the observed signal set (A, A', A"... ) is recorded in the improved phase detection mechanism to speed up the convergence at different frequencies.

While the invention has been described with reference to preferred embodiments, it is to be noted that the invention is not limited to the details shown. Various substitutions and modifications have been suggested in the above description, and others will occur to those skilled in the art. Accordingly, all such substitutions and modifications are intended to be embraced within the scope of the present invention as defined by the appended claims.

Claims (12)

1. A phase-locked loop with an improved phase detection mechanism, comprising: A phase frequency detector has a first input and a second input, and generates a signal according to the relative frequency of the first input and the second input, indicating whether the frequency of the second input is faster or slower than the frequency of the first input; a controller, connected to the phase frequency detector, for receiving the signal from the phase frequency detector and generating a control signal; a digital-to-analog conversion module connected to the controller for receiving the control signal and generating an analog voltage/current output; and a voltage-controlled oscillator connected to the digital-to-analog conversion module for receiving the analog voltage/current output and adjusting an output signal accordingly, Wherein the first input of the phase frequency detector is connected to a reference signal, and the second input is connected to the output signal of the VCO. 2. The phase-locked loop as claimed in claim 1, wherein the voltage-controlled oscillator can be replaced by a current-controlled oscillator. 3. The phase-locked loop as claimed in claim 1, wherein the phase-frequency detector compares the first input, the second input and a delayed second input, the delayed second input having a waveform identical to the a second input with a phase delay, the second input and a delayed occurrence of transitions of the first group of transition patterns of the second input to indicate that the frequency of the first input is higher than the frequency of the second input quick. 4. The phase-locked loop as claimed in claim 1, wherein the phase-frequency detector compares the first input, the second input and a delayed second input, the delayed second input having a waveform identical to the a second input with a phase delay, the second input and a delayed occurrence of transitions of a second group of transition patterns of the second input to indicate that the frequency of the first input is higher than the frequency of the second input slow. 5. The PLL as claimed in claim 1, wherein the reference signal comes from an external crystal. 6. The PLL as claimed in claim 1, wherein the reference signal is digital data from a host. 7. The phase-locked loop as claimed in claim 3, wherein the first group of transition patterns of the second input and a delayed second input comprises (1,1)->(1,0), ( 1,0)->(0,0), (0,0)->(0,1), (0,1)->(1,1), the first item of each pair is the second input, and the second term is the observed level of the second input for this delay. 8. The phase-locked loop as claimed in claim 4, wherein the second input and a second group of transition patterns of a delayed second input comprise (1, 1)->(0, 1), ( 0,1)->(0,0), (0,0)->(1,0), (1,0)->(1,1), the first item of each pair is the second input, and the second term is the observed level of the second input for this delay. 9. The phase-locked loop according to claim 1, wherein when the reference signal stops or disappears, the digital-to-analog conversion module maintains the original control signal value before the reference signal stops, so that the digital-to-analog The conversion module will change the frequency and phase of the output signal without changing the analog voltage/current output to the VCO/CCO. 10. The phase-locked loop as claimed in claim 9, wherein the digital-to-analog conversion module is realized by a counter or an equivalent mechanism capable of increasing or decreasing. 11. The PLL as claimed in claim 3, wherein the improved phase detection mechanism uses a plurality of the delayed second inputs, and each of the delayed second inputs has the same waveform and different phases. 12. The PLL as claimed in claim 4, wherein the improved phase detection mechanism uses a plurality of the delayed second inputs, and each of the delayed second inputs has the same waveform and different phases.

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