CN102299178B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN102299178B CN102299178B CN201010215167.1A CN201010215167A CN102299178B CN 102299178 B CN102299178 B CN 102299178B CN 201010215167 A CN201010215167 A CN 201010215167A CN 102299178 B CN102299178 B CN 102299178B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000002360 preparation method Methods 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims description 16
- 150000001875 compounds Chemical class 0.000 claims description 10
- 238000005265 energy consumption Methods 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 5
- 239000011810 insulating material Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 9
- 238000000151 deposition Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明提出了一种半导体结构，包括：衬底；形成在所述衬底之上的源区和漏区；形成在所述衬底之上的栅极接触区；和形成在所述衬底之上位于所述源区和漏区之间的堆叠结构，所述堆叠结构包括至少一个单元，所述单元包括第一栅极、第二栅极以及形成在所述第一栅极和第二栅极之间的沟道。通过这种堆叠型FET器件的结构，能够有效缩小器件尺寸，增强沟道控制能力，使低能耗高速度的22nm及以下的新一代VLSI技术得以实现。
The present invention proposes a semiconductor structure, comprising: a substrate; a source region and a drain region formed on the substrate; a gate contact region formed on the substrate; and a gate contact region formed on the substrate A stacked structure located between the source region and the drain region, the stacked structure includes at least one unit, and the unit includes a first gate, a second gate, and a gate formed between the first gate and the second gate. channel between the gates. Through the structure of this stacked FET device, the size of the device can be effectively reduced, the channel control ability can be enhanced, and a new generation of VLSI technology of 22nm and below with low energy consumption and high speed can be realized.
Description
Technical field
The present invention relates to semiconductor design and manufacture field thereof, particularly structure of a kind of stacked field-effect transistor (stacking FET) and preparation method thereof.
Background technology
Along with the development of semiconductor technology, especially in VLSI (very lagre scale integrated circuit (VLSIC)) technical field, do not reducing on the basis of device performance, further dwindling chip size and reducing its energy density becomes current research trend.High mobility due to III-V compounds of group, compare with the Si MOSFET (mos field effect transistor) of standard, possesses the high advantage driving of low energy consumption, therefore in recent years to its research again heat up (with reference to M.Radosavlgevic etc., " Advanced High-K Gate Dielectric for High-Performance Short-Channel In
0.7ga
0.3as Quantum Well Field Effect Transistors on Silicon Substrate for Low Power Logic Applications ", IEDM2009,319-322 page).And the research and development for VLSI chip of future generation by III-V compound material, when reducing energy consumption raising speed, are also challenges to the requirement of chip size.
Summary of the invention
Object of the present invention is intended at least one of solve the problems of the technologies described above, and particularly proposes a kind of stacked FET structure, effective reduction of device size, and can realize this structure by the VLSI technology below 22nm.
For achieving the above object, one aspect of the present invention proposes a kind of semiconductor structure, comprising: substrate; Be formed on source region and drain region on described substrate; Be formed on the gate contact region on described substrate; And be formed on the stacked structure between described source region and drain region on described substrate, and described stacked structure comprises at least one unit, described unit comprises first grid, second grid and is formed on the raceway groove between described first grid and second grid.
On the other hand, the present invention proposes a kind of preparation method who forms above-mentioned semiconductor structure, comprises the following steps: substrate is provided; On described substrate, form stacked structure, described stacked structure comprises at least one unit, described unit comprises first grid, second grid and is formed on the raceway groove between described first grid and second grid, and described in each first grid and second grid along the first insulating barrier forming on the sidewall of first direction; On described substrate, form source region and drain region, described source region contacts with described stacked structure on described first direction with drain region; Along forming the second insulating barrier on the sidewall of second direction raceway groove described in each; Along described second direction in formation gate contact region, the both sides of described stacked structure.
The present invention is by proposing a kind of stacked FET semiconductor structure, effectively reduction of device size: on the one hand, the size that control and the thin channel layer structure by double gate (dual gate) realizes orientation is dwindled; On the other hand, the size that realizes channel width dimension by multiple raceway groove stacked structure (multiple stack) is dwindled.The combination of above two aspect characteristics, becomes the key of the high-speed 22nm of low energy consumption and following VLSI technological break-through of new generation.
The aspect that the present invention is additional and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or the additional aspect of the present invention and advantage will become from the following description of the accompanying drawings of embodiments and obviously and easily understand, and accompanying drawing of the present invention is schematically, does not therefore draw in proportion.Wherein:
The semiconductor structure schematic diagram that Fig. 1-3 propose for the embodiment of the present invention;
Fig. 4-26 are preparation method's the intermediate steps schematic diagram of the semiconductor structure of the embodiment of the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are for the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
As Figure 1-3, be the semiconductor structure schematic diagram that the embodiment of the present invention proposes, wherein Fig. 1 is vertical view, Fig. 2 and Fig. 3 are respectively along the profile of AA ' in vertical view and BB '.This structure comprises: substrate 100, substrate 100 can preferably include a resilient coating 101, be formed on stacked structure 200,300He drain region, source region 400 and gate contact porose area 500 on resilient coating 101.Wherein, resilient coating 101 at least consists of the material that comprises a kind of III-V compounds of group.300He drain region, source region 400 is positioned at stacked structure 200 along the both sides of AA ' direction, and gate contact region 500 is positioned at stacked structure 200 along the both sides of BB ' direction.Between each gate contact porose area 500, by insulating material 109, isolated.Stacked structure 200 at least comprises a unit 001, preferably, comprises the repeatedly stacking of a plurality of unit, and source region, drain region and stacked structure are substantially equal, to realize the size of device in channel width dimension, dwindles.As shown in Figure 2, unit 001 comprise first grid 102-1, second grid 102-2 and be formed on first grid 102-1 and second grid 102-2 between raceway groove 103, between raceway groove 103 and first grid 102-1, be formed with respectively gate dielectric layer 104 between raceway groove 103 and second grid 102-2.First grid 102-1 and second grid 102-2 form double gate (dual gate), and the structure by double gate realizes the size of device in orientation and dwindles.For convenience of describing, comprise follow-up preparation method's part below, the orientation of device is defined as to first direction (AA ' direction in each figure), channel width dimension is defined as second direction (BB ' direction in each figure).First grid 102-1 and second grid 102-2 comprise the first insulating barrier 1 in a first direction, to isolate source region and drain region.Raceway groove 103 comprises the second insulating barrier 106 in second direction, with isolation channel with gate contact porose area 500.Should be noted, the orlop of stacked structure 200 and the superiors are gate dielectric layer 104, and the shared grid of two adjacent cells 001, and for example, the first grid of certain unit is the second grid of an adjacent cells on it simultaneously.In a preferred embodiment, the thickness of gate dielectric layer 104 is 1-3nm, and the thickness of grid layer 102 is 2-10nm, and the thickness of channel layer 103 is 2-10nm.
On the one hand, the thin channel layer structure between double gate and double gate can effectively reduce short-channel effect, thereby can realize device, along the size of orientation, dwindles; On the other hand, the effective width of device is to be determined by the developed width of channel region and stacking two factors of number of raceway groove, the present invention carries high drive current by increasing the stacking number of raceway groove, without the developed width that increases channel region, can obtain larger effective width, thereby can realize device, along the size of channel width dimension, dwindle.
Further, the present invention proposes to form the preparation method of above-mentioned semiconductor structure, as shown in Fig. 4-26, is the intermediate steps schematic diagram of the method.Below, with reference to these accompanying drawings, each step of the embodiment of the present invention is described in detail.
Steps A: Semiconductor substrate 100 is provided.In embodiments of the present invention, substrate 100 be take body silicon as example, but in practical application, substrate can comprise any applicable semiconductor substrate materials, can be specifically but be not limited to silicon, germanium, SiGe, SOI (silicon-on-insulator), carborundum, GaAs or any III/V compound semiconductor etc.For example, according to the known designing requirement of prior art (p-type substrate or N-shaped substrate), substrate 100 can comprise various doping configurations.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen the property.
Preferably, substrate 100 surfaces comprise resilient coating 101.A kind of III-V compounds of group on resilient coating 101 comprises, as GaAS.Resilient coating can adopt conventional depositing technics to form, for example sputter, PLD, MOCVD, ALD, PEALD or other suitable methods.
Step B: form stacked structure 200 on substrate.Particularly, first on resilient coating 101 from deposit gate dielectric layer 104, grid layer 102, gate dielectric layer 104, channel layer 103, gate dielectric layer 104, grid layer 102, gate dielectric layer 104 successively on lower, so alternately repeat some unit, take gate dielectric layer 104 as stop-layer.As shown in Fig. 4-5, wherein Fig. 4 is vertical view, and Fig. 5 is the profile along AA ' in Fig. 4.Wherein, gate dielectric layer 104, grid layer 102, channel layer 103 include III-V compounds of group, and still, gate dielectric layer 104 is wide bandgap material, and as InAlAs, grid layer 102 and channel layer 103 are low bandgap material, as are respectively InAs, InGaAs.In the preferred embodiment of the invention, the thickness of gate dielectric layer 104 is 1-3nm, and the thickness of grid layer 102 is 2-10nm, and the thickness of channel layer 103 is 2-10nm.The deposit of layers of material can adopt conventional depositing technics to form, for example sputter, PLD, MOCVD, ALD, PEALD or other suitable methods.
Then graphical stacked structure 200, etches away the stack layer outside channel region.For example by photoetching and anisotropic rie (RIE), realize, the undermost gate dielectric layer 104 of take is stop-layer.As shown in Fig. 6-8, wherein Fig. 6 is vertical view, and Fig. 7 and Fig. 8 are respectively along the profile of AA ' in Fig. 6 and BB '.
Then selectivity over etching grid layer 102, makes it to form opening with the gate dielectric layer 104 of its levels, and as shown in Fig. 9-11, wherein Fig. 9 is vertical view, and Figure 10 and Figure 11 are respectively along the profile of AA ' in Fig. 9 and BB '.
Last deposition insulating material one, and carry out anisotropy RIE, the sidewall of gate dielectric layer 104 of take is stop-layer, makes insulating material one fill above-mentioned opening to form the first insulating barrier 105.As shown in Figure 12-14, wherein Figure 12 is vertical view, and Figure 13 and Figure 14 are respectively along the profile of AA ' in Figure 12 and BB '.Described insulating material comprises silicon dioxide, silicon nitride, for example silicon dioxide.Deposition insulating material can adopt ald (ALD) or molecular layer deposition (MLD) or other applicable method.
Step C: form 300He drain region, source region 400 on substrate.Particularly, can be by epitaxial growth metal or semiconductor layer 107, the InGaAs for example adulterating.Should be noted, this metal or semiconductor layer 107 form low ohm contact with raceway groove 103 sidewalls.Then carry out planarization, for example chemico-mechanical polishing (CMP), take gate dielectric layer 104 surfaces of the superiors is stop surface.As shown in Figure 15-17, wherein Figure 15 is vertical view, and Figure 16 and Figure 17 are respectively along the profile of AA ' in Figure 15 and BB '.
Then anisotropy RIE metal or semiconductor layer 107 are to form 300He drain region, patterned source region 400, simultaneously at BB ' direction over etching raceway groove 103, make raceway groove 103 darker than the over etching of grid layer 102 at the over etching of BB ' direction, as 5-20nm, thereby make raceway groove 103 and the gate dielectric layer 104 of its levels form opening, as shown in Figure 18-20, as shown in Figure 18-20, wherein Figure 18 is vertical view, and Figure 19 and Figure 20 are respectively along the profile of AA ' in Figure 18 and BB '.
Step D: form the second insulating barrier 106 along BB ' direction on the sidewall of each raceway groove 103.Comprise particularly: deposition insulating material two, then this insulating material is carried out to anisotropy RIE, make the opening forming in its filling step C to form insulating barrier 2 106.As shown in Figure 21-23, wherein Figure 21 is vertical view, and Figure 22 and Figure 23 are respectively along the profile of AA ' in Figure 21 and BB '.Insulating material two comprises silicon dioxide, silicon nitride, for example silicon nitride.Deposition insulating material two can adopt the applicable method of ALD or MLD or other.
Then, with respect to second insulating barrier 106 selective etch the first insulating barriers 105, follow epitaxial growth metal or semi-conducting material, the InAs for example adulterating, be connected to form grid extension area 108 with the grid layer 102 in stacked structure 200, then carry out planarization, for example chemico-mechanical polishing (CMP), take gate dielectric layer 104 surfaces of the superiors is stop surface.As shown in Figure 24-26, wherein Figure 24 is vertical view, and Figure 25 and Figure 26 are respectively along the profile of AA ' in Figure 24 and BB '.
Step e: along BB ' direction in formation gate contact region, the both sides of stacked structure 200 500, particularly, can anisotropy RIE grid extension area 108 to form gate contact region 500, then deposition insulating material 109, and carrying out planarization (as CMP), to take the superiors' gate dielectric layer 104 surfaces be stop-layer.Insulating material 109 comprises silicon dioxide, silicon nitride, for example silicon dioxide.As Figure 1-3, wherein Fig. 1 is vertical view, and Fig. 2 and Fig. 3 are respectively along the profile of AA ' in Fig. 1 and BB '.
The present invention proposes semiconductor structure of a kind of stacked FET and preparation method thereof, on the one hand, by control and the thin channel layer Structure Decreasing short-channel effect of double gate, thereby the size that realizes orientation is dwindled; On the other hand, by multiple raceway groove stacked structure, increase the effective width of FET device, thereby the size that realizes channel width dimension is dwindled.And, by dual-gate structure, improve the raceway groove control ability of III-V family device, be that device dwindles ability, by stacked structure, increased effective width and reduced random fluctuation, these characteristics become the key of the high-speed 22nm of low energy consumption and following VLSI technological break-through of new generation.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.
Claims (16)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5567959A (en) * | 1993-12-27 | 1996-10-22 | Nec Corporation | Laminated complementary thin film transistor device with improved threshold adaptability |
| US5780327A (en) * | 1996-03-05 | 1998-07-14 | International Business Machines Corporation | Vertical double-gate field effect transistor |
| JP2005079283A (en) * | 2003-08-29 | 2005-03-24 | Seiko Epson Corp | Thin film semiconductor device and manufacturing method thereof, electro-optical device, and electronic apparatus |
| WO2009060052A1 (en) * | 2007-11-09 | 2009-05-14 | Commissariat A L'energie Atomique | Sram memory cell equipped with transistors having a vertical multi-channel structure |
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| JP3289535B2 (en) * | 1995-02-08 | 2002-06-10 | カシオ計算機株式会社 | Photoelectric conversion device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5567959A (en) * | 1993-12-27 | 1996-10-22 | Nec Corporation | Laminated complementary thin film transistor device with improved threshold adaptability |
| US5780327A (en) * | 1996-03-05 | 1998-07-14 | International Business Machines Corporation | Vertical double-gate field effect transistor |
| JP2005079283A (en) * | 2003-08-29 | 2005-03-24 | Seiko Epson Corp | Thin film semiconductor device and manufacturing method thereof, electro-optical device, and electronic apparatus |
| WO2009060052A1 (en) * | 2007-11-09 | 2009-05-14 | Commissariat A L'energie Atomique | Sram memory cell equipped with transistors having a vertical multi-channel structure |
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