CN102291073B - Multi-axis stepper motor interpolation controller and multi-axis stepper motor motion control card - Google Patents

Abstract

The invention discloses a multi-axis stepping motor interpolation controller and a motion control card. The interpolation controller includes a register file unit and a task logic unit, and the task logic unit includes a programmable frequency divider, a multi-axis digital integrator module, an end point judgment module and a state machine module. The motion control card includes a stepping motor power drive module and the interpolation controller, and also includes a minimum system based on NiosII and its peripheral devices, and a SPWM subdivision driver; the input terminal of the SPWM subdivision driver is connected to the interpolation controller The output ends are connected, and the output ends are connected with the input ends of the stepping motor power drive module. Because the interpolation controller and the SPWM subdivision driver as the main components of the motion control card are all realized by FPGA, that is: its difference compensation algorithm and subdivision driver are all realized by hardware, so compared with the prior art , the motion control card has obvious advantages in design structure, system upgrade, real-time performance, control accuracy and reliability.

Description

Multi-axis stepper motor interpolation controller and multi-axis stepper motor motion control card

technical field

The invention relates to the control of stepping motors, more specifically to a multi-axis stepping motor interpolation controller and a multi-axis stepping motor motion control card.

Background technique

With the rapid development of modern processing and manufacturing industries, ordinary three-axis CNC machine tools can no longer meet people's requirements for processing parts. Multi-axis CNC machine tools can process special-shaped and complex parts surfaces, so in modern processing and manufacturing industries, especially in It has been widely used in aerospace, aviation, and military industries. Therefore, research on high-precision, high-performance multi-axis CNC machine tools has become the research focus of the entire machine tool industry. The multi-axis motion control card is an important component of the multi-axis CNC machine tool. As the lower control unit of the CNC machine tool, it forms a master-slave control structure with the PC, and can perform complex logic processing, speed control, and linkage control on the stepping motor. . The common way for computer to control the stepper motor is to install a motion control card inside the computer. The output plug of the motion control card is connected with the stepper motor drive circuit to control the operation of the stepper motor.

The interpolation controller is the basic unit of the CNC system of the machine tool, which is used to complete the fitting of the motion trajectory. With the increase in the complexity of the structure of the processed parts, there are higher requirements for the performance of the interpolation controller of the CNC system. Not only the interpolation controller is required to have high precision and high speed, but also the multi-axis linkage control function is required to facilitate Processing complex curved surface parts. At present, interpolation controllers with five-axis linkage linear interpolation functions are widely used. However, most of the current CNC systems use software interpolators, and the interpolation calculation of the trajectory of CNC commands is performed by the CPU through software calculations for each axis. The pulse amount and speed are directly sent by the software interpolator to control the drive of each axis by the pulse command signal. Since the calculation is usually realized by the software counting interrupt service routine, the more axes the machine tool has, the longer the program line will be. Usually a three-axis interrupt interpolation service program needs dozens of lines. Considering the instruction cycle of the CPU, each interpolation cycle will be longer, which limits the expansion of the number of axes and the improvement of the interpolation speed. However, the newly appeared multi-axis motion control card based on DSP+FPGA design structure, its DSP and FPGA are completely separated, the design is complicated, and the development cost is high.

Contents of the invention

In view of the above situation, the first purpose of the present invention is to provide a multi-axis stepper motor interpolation controller based on digital integration algorithm (DDA) with high speed, high precision, strong real-time performance and high cost performance.

The second purpose of the present invention is to provide a multi-axis stepping motor motion control card capable of complex logic processing, speed control, linkage control, cost-effective, and applicable to multi-axis complex numerical control systems.

1. The technical solution of the multi-axis stepper motor interpolation controller of the present invention is:

The multi-axis stepping motor interpolation controller of the present invention, its signal input terminal is directly or indirectly connected with the upper computer, and its signal output terminal is directly or indirectly connected with the stepping pulse input terminal of the stepping motor power drive module; its particular The advantage is that the interpolation controller includes a register file unit and a task logic unit;

(1) The register file unit is a data channel between the task logic unit and the host computer, and is used to store the processing data and control signals sent by the host computer and the operating state of the interpolation controller sent by the task logic unit The signal includes a frequency division factor register, each axis coordinate register, a status register, a total step number register, and a control register; the frequency division factor register is used to store the programmable division of the task logic unit sent by the host computer The frequency division factor of the frequency converter is used to adjust and control the interpolation speed of the interpolator; the coordinate registers of each axis are respectively used to store the coordinate values of the end point of motion of the stepper motors of each axis, and are used as the digital integrator for this time. For the integrand, if the coordinate value of a certain axis is larger, it means that the moving distance of the axis is farther, so the digital integrator should generate more step pulses per unit time; the state register is used to register and indicate that the interpolation Complementing the current "idle" or "busy" running state signal of the controller, which can be expressed by high or low level; the total step number register is used to store the sum of the total number of steps that each stepper motor will take ; The control register is used to store multiple control information of the stepper motor, including a pause control signal, a start signal and a rotation direction control signal of each stepper motor;

(2) The task logic unit is used to realize the linkage control and speed control of the multi-axis stepper motor, including a programmable frequency divider, a multi-axis digital integrator module, an end point judgment module and a state machine module;

The programmable frequency divider includes a system clock signal input terminal, a frequency division factor data input terminal and a frequency division signal output terminal; the frequency division factor data input terminal and the frequency division factor register in the register file unit The data output terminal is connected, and the frequency division signal output terminal is connected to the working clock input terminal of the multi-axis digital integrator module, so as to divide the frequency of the system clock according to the frequency division factor value stored in the frequency division factor register, providing the working clock to the multi-axis digital integrator module, thereby realizing the speed control of the stepping motor;

The multi-axis digital integrator module is composed of a plurality of mutually independent digital integrators, and each stepping motor motion axis corresponds to a digital integrator, which is used to generate the linkage stepping pulse signal of each axis stepping motor; each digital The integrator includes an adder and a remainder register: the two data input ends of the adder are respectively connected with the data output end of the remainder register and the data output end of the corresponding axis coordinate register in the register file unit; the adder It also has an addition operation enabling input connected to the stepper motor control enabling output of the state machine module; the output of the adder is connected to the data input of the remainder register; the data of each remainder register The highest bit of the output terminal is the step pulse signal output terminal of the interpolation controller, which is connected directly or through the subdivision drive circuit of the subsequent stage to the step pulse input terminal of the power drive module of the stepping motor to output the corresponding axis The stepping pulse signal of stepper motor, in addition, this highest position is also connected with the stepping pulse signal input end of described terminal judging module as the counting pulse of described terminal judging module; This adder and remainder register also There is a working clock input terminal, which is connected to the frequency division signal output terminal of the programmable frequency divider; the remainder register also has a clear input terminal, which is connected to the state machine module. The clearing enables the output terminal to be connected; the working principle of this module: the coordinate value registers store the coordinate value of the end point of this interpolation as the integrand function of the digital integrator. Before interpolation, clear the input terminal to clear the contents of the remainder register. After the interpolation starts, under the control of the working clock, the digital integrator of each axis performs digital calculation of the integrand function (value in the coordinate register) of each axis. Integral operation (that is: the adder performs an addition operation on the value of the coordinate register and the value of the remainder register, and stores the operation result in the remainder register), because this program uses the highest bit of the remainder register as the stepper for driving the stepping motor Pulse, so as to continuously generate stepping pulse signals of the stepping motors of each axis, control the movement speed of the stepping motors of each axis, and realize the linkage control of each axis

The end point judging module is used to judge whether the stepper motor has moved to the end point, including the input end of the step pulse signal of each axis, the input end of the total step data, the input end of the control signal for reading the total step data, and the end signal of the difference compensation output terminal; the input terminals of the step pulse signals of each axis are respectively connected to the output terminals of the step pulse signals of the corresponding axes of the multi-axis digital integrator module, and the input terminals of the total step data are connected to the register file unit The data output end of the total step number register is connected, the control signal input end of the read total step data is connected with the read total step number control enable output end of the state machine module, and the end signal output of the difference compensation is terminal is connected with the input end of the notification signal of the end of the state machine module; the end point judgment of this module works: this end point judgment module counts the step pulses of each axis output by each digital integrator, and the result of the count Compared with the corresponding value stored in the total step number register, if they are equal, it means that the end point has been reached, and a notification signal of the end of this interpolation is sent to the state machine.

The state machine module is the coordination control center of the multi-axis stepping motor motion control card, which is used to generate various timing control signals and coordinate the work of the multi-axis digital integrator and the terminal determination module; the state machine module includes: The pause control signal input end and the start signal input end connected to the control register output end in the register file unit, the interpolation end notification signal input end connected to the interpolation end signal output end of the end point determination module, and the The control signal input terminal of reading the total step data of the end point judgment module is connected to the read total step number control enable output end for notifying the end point judgment module to read the value of the total step number register, and the multiple Each adder addition operation of the axis digital integrator module can enable the stepper motor control output end connected to the input end of the multi-axis digital integrator module. Can output end, and, be connected with described state register, be used for indicating that this interpolation controller is in " idle " or " busy " state running state signal output end at present; And, this state machine can be set to have following Three working states:

Before the interpolation controller is started, the state machine operates in the "idle" state: in this state, the state machine sets the state signal output terminal to output an interpolation controller operation state signal meaning "idle";

After the start signal input end receives the start signal sent by the control register, the state machine enters the data initialization state: in this state, the state machine module sets the output meaning of the state signal output end as "busy" The interpolation controller running status signal, in addition, also generates a clear signal and a read signal: the clear signal clears the contents of the register through the enable output to each remainder register of the digital integrator The content is cleared, and the read signal enables the output terminal to notify the terminal judgment module to read the value of the total step number register through the read total step number control; and then,

Under clock control, the state machine unconditionally enters the stepper motor control state: in this state, the state machine module sends a stepper motor control signal to the multi-axis digital integrator module through the stepper motor control enable output terminal. Control the enable signal, start the multi-axis digital integrator module to start the integral operation, and generate the pulse signal of the stepping motor of each axis;

When the input terminal of the notification signal of the end of the difference compensation receives the notification signal of the end of the difference compensation sent by the terminal judging module, the state machine exits the stepping motor control state and enters the "idle" state again.

In the above solution, the principle of using the programmable frequency divider to control the rotation speed of the stepping motor is: the frequency division factor of the frequency divider becomes larger, and the frequency obtained by the frequency division of the system clock by the frequency divider becomes smaller, thus, the digital The working clock of the integrator becomes smaller, the operation speed of the digital integrator becomes slower, and the speed of the stepping motor becomes smaller; on the contrary, the frequency division factor of the frequency divider becomes smaller, the output frequency of the frequency divider becomes larger, and the multi-axis digital integrator The calculation speed becomes faster, and the speed of the stepping motor becomes faster.

In the multi-axis stepper motor interpolation controller of the above scheme, its signal input terminal can also be directly or indirectly connected to the host computer through an interface unit; the interface unit connects the task logic unit through the register file unit , directly or indirectly connected to the data bus of the host computer to realize the communication between the task logic unit and the host computer.

As an optimization of the above-mentioned multi-axis stepper motor interpolation controller, in order to reduce the I/O port occupancy rate of FPGA, reduce the difficulty of programming, improve the speed control and real-time linkage control performance of multiple stepper motors, the inventors The interpolation controller is designed as a hardware interpolation control IP core, which is directly connected to the Avalon data bus. The interface unit is an Avalon interface unit. Because of the digital integrator, the interpolation controller can be realized by hardware at this time. Therefore, this controller has the advantages of fast speed, high precision and strong real-time performance, and is easy to be applied to multi-axis complex numerical control systems.

2. The technical scheme of the multi-axis stepper motor motion control card of the present invention is:

The multi-axis stepping motor motion control card of the present invention includes a multi-axis stepping motor interpolation controller and a stepping motor power drive module; the signal input end of the multi-axis stepping motor interpolation controller is directly or indirectly connected with The host computer is connected, and its signal output terminal is directly or indirectly connected to the stepping pulse input terminal of the stepper motor power drive module; the output terminal of the power drive module is connected to the stepper motor; its special feature is: the multi-axis The stepping motor interpolation controller adopts the multi-axis stepping motor interpolation controller of the above technical solution.

As a further optimization of the above-mentioned scheme, the multi-axis stepper motor motion control card of the present invention also includes a minimum system based on Nios II, peripheral devices based on the minimum system of Nios II, and a SPWM subdivision driver; the SPWM subdivision Driver, its signal input end is connected with the signal output end of described interpolation controller, and its signal output end is connected with the stepping pulse signal input end of described stepper motor power drive module; Described minimum system based on Nios II, Include Avalon data bus, and, Nios II processor and multiple peripheral device interface controllers that are connected with Avalon data bus; Described peripheral device interface controller includes UART controller, JTAG controller, EPCS controller, SDRAM control device and LCD controller; the peripheral devices of the minimum system based on Nios II include USB interface unit, EPCS memory, SDRAM memory, LCD display; at this time, the interpolation controller is designed as hardware interpolation control IP core form, and the design includes the Avalon interface unit, and is integrated on the same FPGA with the minimum system based on Nios II; the signal input end of the interpolation controller of the stepping motor is connected to the Avalon data bus ; Each peripheral device of the minimum system based on Nios II is connected with the corresponding peripheral device interface controller through the I/O port of the FPGA, and through the Avalon data bus and Nios II through the corresponding peripheral device interface controller Processor carries out data exchange; Described Avalon interface unit, described task logic unit is connected on the described Avalon data bus by described register file unit, realizes the communication of described task logic unit and described Nios II processor; Upper position The stepper motor motion control command signal output end of the machine is connected with the USB interface unit of the motion control card.

As a further improvement to the above scheme, the multi-axis stepper motor motion control card of the present invention can also integrate the stepper motor interpolation controller, the SPWM subdivision driver and the minimum system based on Nios II in the same On a piece of FPGA. Specifically, the SPWM subdivision driver can be designed to adopt a two-phase hybrid stepper motor SPWM subdivision driver, including an address generator for generating ROM addresses, a ROM that stores excitation current data, a PWM modulator, and a data converter , PI regulator, digital phase converter; the ROM is a dual-port ROM; the address generator, dual-port ROM, data converter, PI regulator, PWM modulator, digital phase converter and stepping motor double H-bridge power The drive circuits are connected sequentially;

The address generator, its input signal terminal receives the step pulse signal, direction control signal and pause signal transmitted directly or indirectly from the host computer, and adds the step pulse signal according to the direction control signal and pause signal. 1 or minus 1, and pause counting; the counting result is used as the A and B phase input addresses of the dual-port ROM respectively, and the phase difference between them is π/2; the address generator also sends to the rear stage The data converter and digital phase converter provide polarity signals of phase A and phase B;

The dual-port ROM includes two sets of mutually independent input and output ports, and the ROM stores a cycle of exciting current data that changes according to a sine step wave;

The data converter, according to the polarity signals of phase A and phase B sent by the address generator, converts the sinusoidal data of one cycle output from the dual ports of the dual port ROM into phase A symmetrical to the x axis Two channels of sinusoidal data and phase B are sent to their respective PI regulators;

The two PI regulators perform PI regulation respectively according to the difference between the above-mentioned sinusoidal data of this channel and the feedback voltage signal of the sampling winding of the stepper motor, and output corresponding PI regulation control to the respective PWM modulators Signal;

The two PWM modulators perform PWM modulation on the PI adjustment control signal values transmitted from the aforementioned PI regulator, and output two PWM control signals with different duty ratios to the digital phase converter;

The digital phase converter, according to the phase A and phase B polarity signals sent by the address generator, performs phase-changing processing on the output signals of the aforementioned two PWM modulators, from the AH, BH, AL and BL ports to the subsequent stage The stepper motor double H-bridge power drive circuit provides PWM subdivision drive signals with direction changes.

The digital phase changer in the above scheme can adopt PWM modulator output signal phase change processing circuit:

When 0～π, AH and BH are connected to their respective PWM modulation signals, AL and BL are grounded; when π～2π, AL and BL are connected to their respective PWM modulation signals, and AH and BH are grounded; or,

When 0～π, AL and BL are connected to their respective PWM modulation signals, AH and BH are grounded; when π～2π, AH and BH are connected to their respective PWM modulation signals, and AL and BL are grounded.

The above solution is a multi-axis motor motion control card based on NiosII and FPGA designed by using a large module field programmable logic gate array (FPGA). The NiosII soft-core CPU is embedded in the FPGA, and the embedded NiosII The soft-core CPU is used to run some simple programs, and the FPGA is used to implement the differential compensation algorithm and subdivision drive. Therefore, this motion control card has obvious advantages in design structure, system upgrade, reliability, real-time performance, and cost performance.

The test shows that the above-mentioned SPWM subdivision driver uses the sine wave pulse width modulation (SPWM) subdivision drive technology, which can effectively overcome the disadvantages of low-frequency vibration, large noise, high-frequency out-of-step and low resolution of the non-subdivision drive of the stepping motor. , greatly improving the motion performance of the stepping motor; the power drive module of the stepping motor amplifies the power of the driving signal of the stepping motor, so that it can meet the power requirement of effectively driving the stepping motor.

The test results show that, in addition to the unique respective advantages of the interpolation controller mentioned above and the SPWM subdivision driver, compared with the prior art, the multi-axis stepper motor motion control card of the present invention designed by field programmable gate array , due to the adoption of the NiosII soft-core CPU+FPGA hardware design scheme, that is, to use the NiosII soft-core CPU to run the control program, and to use the FPGA to realize the digital difference compensation algorithm and subdivision drive of the linkage control with high real-time requirements, and at the same time adopt the Digital integration algorithm and sine wave pulse width modulation subdivision drive technology, therefore, this motion control card has the advantages of high integration, high control precision, high cost performance, fast speed, strong real-time performance, good reliability, and strong anti-interference ability.

Description of drawings

Fig. 1 is a schematic block diagram of the composition principle of the hardware system of an embodiment of the multi-axis stepping motor motion control card of the present invention.

FIG. 2 is a schematic diagram of a NiosII-based SOPC hardware platform of an embodiment of the multi-axis stepping motor motion control card of the present invention.

Fig. 3 is a functional block diagram of the hardware design of an embodiment of the multi-axis stepping motor interpolation controller IP core of the present invention.

Fig. 4 is a hardware functional block diagram of an embodiment of the digital integrator of the present invention.

Fig. 5 is a hardware system schematic diagram of an embodiment of the SPWM subdivision driver of the multi-axis stepping motor motion control card of the present invention.

FIG. 6 is a test waveform diagram of the output signal of the five-axis digital integrator of an embodiment of the multi-axis stepping motor motion control card of the present invention.

Detailed ways

Taking the drawings and specific implementation of a five-axis stepping motor motion control card as an example, the multi-axis stepping motor interpolation controller and the multi-axis stepping motor motion control card of the present invention and their use will be further described.

1. Hardware system composition

Fig. 1 is a schematic block diagram of the composition principle of the hardware system of an embodiment of the multi-axis stepping motor motion control card of the present invention. It can be seen from the schematic block diagram of the principle that the motion control card is composed of a large-scale field programmable logic gate array (in the dotted line box), a stepper motor power drive module and some peripheral components.

As can be seen from Figure 1, in this field programmable logic gate array (FPGA), not only the UART controller, JTAG controller, NiosII processor, EPCS controller, SDRAM control, LCD controller, timing controller, The Avalon data bus also integrates a five-axis stepper motor interpolation controller and a SPWM subdivision driver. The UART controller and the peripheral CP2101 bridge conversion chip constitute a USB communication system to ensure that the control card can communicate with the upper PC; the EPCS controller controls the peripheral EPCS4 storage chip for storing FPGA configuration files and program codes; The LCD display displays the status of the motion control card and the current coordinates of each axis in real time; the JTAG controller is connected to the upper PC through the JTAG interface to realize the functions of program download and JTAG online debugging; the five-axis stepping motor inside the FPGA The interpolation controller completes the interpolation calculation and speed control functions of the stepping motor, and generates the stepping pulse of the motor; in addition, a SPWM subdivision driver is also integrated inside the FPGA. The stepping pulse signal output end of the SPWM subdivision driver is connected with the stepping pulse signal input end of the stepping motor power drive module. When in use, the processing data and control command signals are transmitted from the USB port of the host computer to the five-axis stepper motor control card, and the CP2101 bridge control chip converts the USB data stream into a UART data stream, and then NiosII writes these data to the multi-axis Stepping motor interpolation controller.

The motion control card FPGA hardware platform of the present embodiment selects and adopts the Cyclone series EP1C6Q240C8 chip of Altera Company, and utilizes the professional software QuartusII8.0 of Altera Company to design the hardware platform, including SOPC hardware system design based on NiosII, multi-axis stepping Motor interpolation controller design and SPWM subdivision driver design three major modules:

(1) SOPC hardware platform based on Nios II

This motion control control card uses NiosII soft-core CPU of Altara Company as the controller, and embeds this CPU into FPGA to form a NiosII-based SOPC system. NiosII soft-core CPU is a general-purpose 32-bit RISC embedded processor of Altera Company, and this processor has been optimized in the company's FPGA, with high cost performance. In the QuartusII software, SOPC Builder also provides three soft cores: economical Nios II, standard Nios II and fast Nios II. In addition, this software also provides a large number of free commonly used peripheral control IP cores. Designers can configure these IP cores as peripheral interfaces according to their own design needs, and design a SOPC hardware oriented to user needs. system, and more importantly, the SOPCBuider of this software is an open system, which allows designers to add their own designed IP cores to the IP library of SOPC Buider to enrich the content of this IP library and realize IP reuse, as shown in Figure 1 The design of an interpolation controller for a five-axis stepper motor in is a design example. Figure 2 shows the NiosII-based SOPC hardware platform developed using the SOPC Builder development tool. This platform includes NiosII soft-core processors, UART controllers, JTAG controllers, EPCS controllers, SDRAM controllers, LCD controllers, timing controllers, Avalon data bus.

(2) Five-axis stepper motor interpolation controller

The five-axis stepper motor interpolation controller is one of the key modules of this motion control card, which can realize the speed control and real-time linkage control functions of five stepper motors. In order to reduce the I/O port occupancy rate of the FPGA and reduce programming difficulty, this embodiment designs the interpolation controller as a hardware interpolation control IP core form, which is directly connected to the Avalon data bus, as shown in FIG. 1 .

Figure 3 is a block diagram of the hardware design of the IP core of the interpolation controller. It can be seen from the figure that the IP core is divided into three modules: Avalon interface unit, register file unit and task logic unit:

1) The Avalon interface unit is the interface unit for the NiosII soft-core CPU to communicate with the motion control card. It is directly connected to the Avalon data bus inside the FPGA.

In the QuartusII 8.0 software, the SOPC Builder tool provides 6 different interface types and signals. The designer can select the interface according to the design needs, and specify the Avalon signal type for various signals of the task logic. Table 1 is used in this design embodiment. interface unit information.

Table 1 Avalon interface information table

2) In order to achieve the purpose of communication, a group of registers (register file unit) is designed in this interpolation controller, and these registers are used to store processing data, control signals and the operating status of the controller. The register file unit includes a speed parameter register, an X-axis coordinate register, a Y-axis coordinate register, a Z-axis coordinate register, a B-axis coordinate register, a C-axis coordinate register, a status register, a total step number register, and a control register; Register for a brief introduction:

The frequency division factor register is used to register the frequency division factor of the frequency divider so as to control the rotation speed of the stepping motor; the X-axis coordinate register, the Y-axis coordinate register, the Z-axis coordinate register, the B-axis coordinate register and the C-axis coordinate The registers store the coordinates of the end point of the stepper motors of the X-axis, Y-axis, Z-axis, B-axis and C-axis respectively, as the integrand function of the digital integrator this time. If the coordinate value of a certain axis is larger, it means that the The farther the axis moves, the more stepping pulses the digital integrator generates in unit time; the status register is used to store the running status signal indicating that the interpolation controller is currently "idle" or "busy". High or low level; the total step number register is used to store the sum of the total number of steps to be taken by five stepper motors; the control register stores various control information, including 1-bit pause control signal, 1-bit Start signal and 5-bit stepper motor rotation direction control signal.

Table 2 below lists the name, relative address, read and write direction, bit width and functional description of these registers. Each register corresponds to a different address, and the reading and writing direction and bit width are also different.

Table 2 Register group definition and address allocation

3) Task logic unit, the most important module of this IP core, is used to realize the linkage and speed control functions of five stepper motors, including a five-axis digital integrator module, an end point judgment module, a programmable frequency divider and a state machine Module Four functional modules:

The five-axis digital integrator is composed of five mutually independent digital integrators, and each coordinate axis corresponds to a digital integrator. Its principle block diagram is shown in Figure 4. As shown in the figure, each digital integrator includes an adder and a remainder register: the two data input ends of the adder are respectively connected to the data output end of the remainder register and the data output end of the corresponding axis coordinate register in the register file unit; The adder also has an addition enable input end connected to the stepping motor control enable output end EN of the state machine module; the output end of the adder is connected with the data input end of the remainder register; The highest bit of the data output end of each remainder register is the stepping pulse signal output end of the interpolation controller to the stepping motor of each axis, which is input through the SPWM subdivision drive circuit of the subsequent stage and the stepping pulse signal of the stepping motor power drive module Connected to the end, used to output the stepping pulse signal of the corresponding shaft stepping motor, in addition, this highest bit is also used as the counting pulse of the end point judgment module, connected with the stepping pulse signal input end of the end point judgment module ; This adder and remainder register also have working clock input end CLK, and it links to each other with the frequency division signal output end of described programmable frequency divider; Described remainder register also has clearing input end CLR, and this clearing input end is connected with The clearing and enabling output terminals of the state machine module are connected to each other. After the interpolation is started, under the control of the CLK clock, the digital integrator of each axis performs digital integral operation on the integrand (the value in the coordinate register) of each axis, and continuously generates the stepping pulse of the stepping motor of each axis The signal controls the movement speed and linkage function of the stepping motors of each axis, and realizes the linkage control of each axis.

The end point judgment module is used to judge whether this interpolation operation has reached the end point: it counts the step pulses output by each axis, and compares the counting result with the value of the total step number register. If they are equal, it means that the end point has been reached , use the over signal to notify the state machine to indicate the end of the differential compensation; it includes the input terminal of the step pulse signal of each axis, the input terminal of the total step data, the control signal input terminal RD for reading the total step data, and the output signal of the end of the differential compensation terminal over; the input terminals of the step pulse signals of each axis are respectively connected with the output terminals of the step pulse signals of the corresponding axes of the multi-axis digital integrator module, and the input terminals of the total step data are connected with the input terminals of the register file unit The data output terminal of the total step number register is connected, the control signal input terminal RD of the read total step data is connected with the read total step number control enable output end of the state machine module, and the difference compensation end signal The output terminal over is connected to the input terminal of the notification signal of the completion of the interpolation of the state machine module.

The state machine module is the coordination control center of the task logic unit, which is used to generate various timing control signals to make the five-axis digital integrator and the end point judgment module work in coordination; the state machine module includes a control register that is compatible with the register file unit The pause control signal input terminal pause and the start signal input terminal start connected to the output terminal, the differential compensation end notification signal input terminal connected to the differential compensation end signal output terminal over of the end point judgment module, and the read total of the end point judgment module The control signal input end RD of the step data is connected to be used for notifying the read total step number control enable output end of the value of the total step number register read by the terminal judging module, and the multi-axis digital integrator module The stepper motor control enable output end EN connected to the addition operation enable input end of each adder, and the register content clear enable output end connected to the remainder register clear input end CLR of the multi-axis digital integrator module, And, the running status signal output terminal state connected to the status register and used to indicate that the interpolation controller is currently in the "idle" or "busy" state; and, the state machine can be set to have the following three jobs: state:

Before the interpolation controller is not started, the state machine is always in the "idle" state s0, and at this time, the state signal output terminal state sends an interpolation controller operation status signal meaning "idle";

When the start signal input end start receives the start signal sent by the control register, the state machine enters the data initialization state s1: in this state, the state signal output end state sends a "busy" state signal, except In addition, this state machine module sends a content clearing signal to each remainder register of the digital integrator through the clearing enable output terminal, and controls the enabling output terminal to the end point through the reading total step number control. The judgment module sends a read signal to read the value of the total number of steps register; and then,

Under clock control, the state machine unconditionally enters the stepper motor control state s2: in this state, the state machine module sends a step to the multi-axis digital integrator module through the stepper motor control enable output terminal EN. Enter the motor control enable signal, start the multi-axis digital integrator module to start the integral operation, and generate the pulse signal of the stepping motor of each axis;

When the input terminal of the notification signal of the end of the difference compensation receives the notification signal of the end of the difference compensation sent by the terminal determination module, the state machine module exits the stepping motor control state s2 and enters the "idle" state s0 again, the state The signal output state signals the "idle" state.

The programmable frequency divider is actually a programmable frequency division controller, including a system clock signal input terminal, a frequency division factor data input terminal and a frequency division signal output terminal; the frequency division factor data input terminal and the register The data output end of the frequency division factor register in the file unit is connected, and the frequency division signal output end is connected with the working clock input end of the multi-axis digital integrator module. The frequency divider can divide the system clock according to the frequency division factor and then provide the working clock to the multi-axis digital integrator module, so that the five-axis digital integrator can obtain working clocks of different frequencies, thereby realizing the speed of the stepping motor control.

The working process of this interpolation controller: Before interpolation, read the value in the status register to know the working status of the system. If it is in the "idle" state, NiosII will write the coordinates of the end point of this linear interpolation into the corresponding register. Then, calculate the total number of stepping pulses according to the length of the straight line in space and the stepping distance of the stepping motor, and write it into the total stepping number register. Finally, after setting the direction control bit of the control register according to the direction of linear interpolation, start the interpolation controller.

(3) SPWM subdivision driver

In order to overcome the shortcomings of low-frequency vibration, high noise, high-frequency out-of-step and low resolution, and effectively improve the performance of the stepper motor, this control card uses a sine wave pulse width modulation (SPWM) subdivision drive. Figure 5 is a The functional block diagram of the subdivision driver design of the two-phase hybrid stepping motor, including address generator, dual-port ROM, data converter, PI regulator, PWM modulator and digital phase converter and other modules.

The address generator is essentially a counter, which can count up or down the step pulse signal according to the level of the direction control signal: when the level is high, the counter adds 1, and the addresses of A and B phases increase by 1 correspondingly. When it is low level, the counter is decremented by 1, and the A and B phase addresses are decremented by 1 accordingly, but the A and B phase address values are not equal, and the phase difference between them is π/2. In order to improve the resolution of the subdivision drive of the stepping motor, in the dual-port ROM, a cycle (total 1024 points) of sine wave data is continuously stored, and each point of data corresponds to a different address. With the increase of the address, the sine wave data Wave data are read out one by one. Non-negative polarity signals are stored in the dual-port ROM. In order to obtain a constant and uniform rotational torque, the data of the dual-port ROM must be converted. The data data converter is to realize this function: it can convert a cycle of sinusoidal data into sinusoidal data symmetrical to the x axis according to the polarity signals of phase A and phase B. In order to effectively control the current in the excitation winding of the stepping motor, a PI regulator is designed in the circuit. The PI regulator performs PI regulation according to the difference between the given sinusoidal data and the sampling winding feedback voltage signal, so that the system The dynamic response time becomes faster. The PWM modulator controls the duty cycle of the output signal according to the value of the input control signal to complete PWM modulation. The digital commutator, according to the polarity signals of phase A and phase B, performs phase-changing processing on the PWM output signal (changes the current direction): when 0~π, the PWM modulation signal is output from AH, when π~2π, the PWM modulation signal Output from AL.

The system software design of the multi-axis stepping motor motion control card of the present invention can be divided into two major parts, the PC programming of the upper computer and the programming of the lower computer based on the Nios II soft-core CPU. The upper computer adopts the Delphi 7.0 software development platform, and the lower computer adopts NiosII8.0 IDE software development platform. In order to reduce the burden of the lower computer, most of the work is done by the upper computer PC. The upper computer program design is divided into man-machine interface module, initialization module, parameter setting module, status display module, program running, program pause, COM port communication module and other modules. The programming of the lower computer is divided into two parts, the main program and the serial port interrupt service program. For the more specific content of the system software design, reference may be made to the prior art, and no further details will be given here.

2. Test results:

The motion control card of the above embodiment has been successfully applied in a certain prototype, in which the field programmable logic gate array is selected from Altera's EP3C25Q240C8N, and the stepping motor is selected from Leetro's two-phase stepping motor DM4250C. The test results show that the motion control card works stably, the controlled stepping motor works smoothly, the interpolation operation speed is fast, and the control precision is high. Figure 6 is the output signal waveform of the five-axis digital integrator tested by the QuartusII embedded logic analyzer (SigalTap II Logic Analyzer): xp, yp, zp, bp and cp are the X-axis, Y-axis, Z-axis, B-axis and C-axis step pulse output, each rising edge of the signal indicates that the stepping motor takes a step. It can be seen from the figure that the number of steps (rising edges) between them is exactly 2 times the relationship, indicating that the five-axis stepping motor It has a good linkage relationship, which effectively verifies the correctness of this design.

Claims (8)

1. The signal input end of the multi-axis stepping motor interpolation controller is directly or indirectly connected with an upper computer, and the signal output end of the multi-axis stepping motor interpolation controller is directly or indirectly connected with the stepping pulse input end of the stepping motor power driving module; the method is characterized in that: the interpolation controller comprises a register file unit and a task logic unit;

(1) the register file unit is a data channel between the task logic unit and the upper computer, is used for registering processing data and control signals sent by the upper computer and interpolation controller running state signals sent by the task logic unit, and comprises a frequency division factor register, axis coordinate registers, a state register, a total stepping number register and a control register; the frequency division factor register is used for registering the frequency division factor of the programmable frequency divider of the task logic unit sent by the upper computer; the axis coordinate registers are respectively used for registering the coordinate values of the motion end points of the stepping motors of the axes; the state register is used for registering an operation state signal indicating that the interpolation controller is currently in idle or busy; the total stepping number register is used for registering the total stepping number sum to be stepped by each stepping motor; the control register is used for registering various control information of the stepping motors, including pause control signals, starting signals and rotation direction control signals of all the stepping motors;

(2) the task logic unit is used for realizing linkage control and speed control of the multi-axis stepping motor and comprises a programmable frequency divider, a multi-axis digital integrator module, an end point judgment module and a state machine module;

the programmable frequency divider comprises a system clock signal input end, a frequency division factor data input end and a frequency division signal output end; the frequency division factor data input end is connected with the data output end of a frequency division factor register in the register file unit, and the frequency division signal output end is connected with the working clock input end of the multi-axis digital integrator module;

the multi-axis digital integrator module consists of a plurality of mutually independent digital integrators, and each moving axis corresponds to one digital integrator and is used for generating linkage stepping pulse signals of stepping motors of all axes; each digital integrator comprises an adder and a remainder register: two data input ends of the adder are respectively connected with the data output end of the remainder register and the data output end of the corresponding axis coordinate register in the register file unit; the adder is also provided with an addition operation enabling input end connected with a stepping motor control enabling output End (EN) of the state machine module; the output end of the adder is connected with the data input end of the remainder register; the highest bit of the data output end of each remainder register is used as a stepping pulse signal output end of the interpolation controller and is connected with a stepping pulse input end of the stepping motor power driving module directly or through a subsequent subdivision driving circuit; the adder and remainder register also has a working clock input terminal (CLK) connected to the frequency-divided signal output terminal of the programmable frequency divider; the remainder register is also provided with a zero clearing input end (CLR) which is connected with a zero clearing enabling output end of the state machine module;

the end point judging module comprises shaft stepping pulse signal input ends, total stepping data input ends, a control signal input end (RD) for reading total stepping data and a difference compensation finishing signal output end (over); the step pulse signal input ends of the shafts are respectively connected with the step pulse signal output ends of the corresponding shafts of the multi-shaft digital integrator module, the total step data input end is connected with the data output end of a total step number register in the register file unit, the control signal input end (RD) for reading total step data is connected with the control enabling output end for reading total step number of the state machine module, and the over-compensation ending signal output end (over) is connected with the over-compensation ending notification signal input end of the state machine module;

the state machine module is used for generating various time sequence control signals and coordinating the work of the multi-axis digital integrator and the terminal point judging module; the state machine module comprises a pause control signal input end (pause) and a start signal input end (start) which are connected with the output end of a control register in the register file unit, a difference compensation ending notification signal input end connected with the difference compensation ending signal output end (over) of the end point judging module, a total step number reading control enabling output end connected with a total step data reading control signal input end (RD) of the end point judging module, a stepping motor control enabling output End (EN) connected with the addition operation enabling input ends of adders of the multi-axis digital integrator module, a register content zero clearing enabling output end connected with the residue register zero clearing input ends (CLR) of the multi-axis digital integrator module, and, an operation state signal output end (state) which is connected with the state register and is used for indicating the current idle state or busy state of the interpolation controller; and,

before the interpolation controller is started, the state machine operates in an idle state (s 0): in the state, the state machine sets and outputs the state signal output end (state) to an interpolation controller running state signal meaning idle;

when the start signal input end (start) receives the start signal sent by the control register, the state machine enters a data initialization state (s 1): in this state, the state machine module sets the state signal output terminal (state) to output the interpolation controller operation state signal meaning "busy", in addition to generating a clear signal and a read signal: the zero clearing signal is output through the register content zero clearing enabling output end and is used for clearing the content of each remainder register of the digital integrator; the reading signal is output through the read total stepping number control enabling output end and is used for informing the end point judging module to read the value of the total stepping number register; and further, in the above-described manner,

under clock control, the state machine unconditionally enters a stepper motor control state (s 2): in the state, the state machine module sends out a stepping motor control enabling signal to the multi-axis digital integrator module through the stepping motor control enabling output End (EN), starts the multi-axis digital integrator module to start integration operation, and generates pulse signals of the stepping motors of all axes;

when the input end of the difference compensation ending notification signal receives the difference compensation ending notification signal sent by the terminal point judging module, the state machine exits the stepping motor control state (s2) and enters the idle state again (s 0).

2. The multi-axis stepper motor interpolation controller of claim 1, wherein: the signal input end of the signal input end is directly or indirectly connected with an upper computer through an interface unit; the interface unit connects the task logic unit to the data bus of the upper computer directly or indirectly through the register file unit, and realizes the communication between the task logic unit and the upper computer.

3. The multi-axis stepper motor interpolation controller of claim 2, wherein: the multi-axis stepping motor interpolation controller is designed as a hardware interpolation control IP core; the interface unit is an Avalon interface unit.

4. The multi-axis stepping motor motion control card comprises a multi-axis stepping motor interpolation controller and a stepping motor power driving module; the signal input end of the multi-axis stepping motor interpolation controller is directly or indirectly connected with an upper computer, and the signal output end of the multi-axis stepping motor interpolation controller is directly or indirectly connected with the stepping pulse input end of the stepping motor power driving module; the output end of the power driving module is connected with a stepping motor; the method is characterized in that: the multi-axis stepping motor interpolation controller is the multi-axis stepping motor interpolation controller according to any one of claims 1 to 3.

5. The multi-axis stepper motor motion control card of claim 4, wherein: the multi-axis stepping motor interpolation controller adopts the multi-axis stepping motor interpolation controller as claimed in claim 3; besides, the motion control card also comprises a minimum system based on Nios II, a peripheral device of the minimum system based on Nios II and an SPWM subdivision driver; the signal input end of the SPWM subdivision driver is connected with the signal output end of the interpolation controller, and the signal output end of the SPWM subdivision driver is connected with the stepping pulse signal input end of the stepping motor power driving module;

the Nios II-based minimum system comprises an Avalon data bus, a Nios II processor and a plurality of peripheral device interface controllers, wherein the Nios II processor and the plurality of peripheral device interface controllers are connected with the Avalon data bus; the peripheral device interface controller comprises a UART controller, a JTAG controller, an EPCS controller, an SDRAM controller and an LCD controller;

the peripheral device of the minimum system based on Nios II comprises a USB interface unit, an EPCS memory, an SDRAM memory and an LCD display;

the stepping motor interpolation controller and the Nios II-based minimum system are integrated on the same FPGA; the signal input end of the stepping motor interpolation controller is connected to the Avalon data bus; each peripheral device of the minimum system based on Nios II is connected with a corresponding peripheral device interface controller through an I/O port of the FPGA, and exchanges data with the Nios II processor through an Avalon data bus through the corresponding peripheral device interface controller; the Avalon interface unit is used for connecting the task logic unit to the Avalon data bus through the register file unit so as to realize the communication between the task logic unit and the NiosII processor;

and the motion control command signal output end of the stepping motor of the upper computer is connected with the USB interface unit of the motion control card.

6. The multi-axis stepper motor motion control card of claim 5, wherein: the step motor interpolation controller, the SPWM subdivision driver and the Nios II-based minimum system are integrated on the same FPGA.

7. The multi-axis stepper motor motion control card of claim 6, wherein: the SPWM subdivision driver is a two-phase hybrid stepping motor SPWM subdivision driver and comprises an address generator for generating a ROM address, a ROM storing exciting current data, a PWM modulator, a data converter, a PI regulator and a digital phase converter; the ROM is a double-port ROM; the address generator, the double-port ROM, the data converter, the PI regulator, the PWM modulator, the digital phase converter and the double-H-bridge power driving circuit of the stepping motor are sequentially connected;

the input signal end of the address generator receives a stepping pulse signal, a direction control signal and a pause signal which are directly or indirectly transmitted from an upper computer, and adds 1 or subtracts 1 and pauses counting to the stepping pulse signal according to the direction control signal and the pause signal; the counting result is respectively used as the A phase input address and the B phase input address of the dual-port ROM, and the phase difference between the A phase input address and the B phase input address is pi/2; the address generator also provides polarity signals of A phase and B phase for a data converter and a digital phase converter of the later stage;

the double-port ROM comprises two sets of mutually independent input and output ports, and excitation current data which changes according to sinusoidal step waves in one period are stored in the ROM;

the data converter converts sinusoidal data of one period output from the double ports in the double-port ROM into two paths of sinusoidal data of the A phase and the B phase which are symmetrical with an x axis according to polarity signals of the A phase and the B phase sent by the address generator, and respectively sends the sinusoidal data to respective PI regulators;

the two PI regulators respectively carry out PI regulation according to the difference value between the two paths of sine data and the feedback voltage signal of the sampling winding of the current phase of the stepping motor, and output corresponding PI regulation control signals to respective PWM modulators;

the two PWM modulators respectively perform PWM modulation on the PI regulation control signal values transmitted by the two PI regulators and respectively output two PWM control signals with different duty ratios to the digital phase converter;

and the digital phase converter is used for carrying out phase conversion treatment on output signals of the two PWM modulators according to the A-phase and B-phase polarity signals sent by the address generator, and providing PWM subdivision driving signals with changed directions to a rear-stage stepping motor double H-bridge power driving circuit from AH, BH, AL and BL ports.

8. The multi-axis stepper motor motion control card of claim 7, wherein: the digital phase converter is a PWM modulator output signal phase conversion processing circuit:

when the amplitude is 0-pi, AH and BH are connected with respective PWM modulation signals, AL and BL are grounded; when pi is equal to 2 pi, AL and BL are connected with respective PWM modulation signals, and AH and BH are grounded; or,

when the voltage is 0-pi, AL and BL are connected with respective PWM modulation signals, and AH and BH are grounded; when pi-2 pi, AH and BH receive respective PWM modulation signals, and AL and BL are grounded.

Images