CN102290096A

CN102290096A - decoding and logic control circuit of static random access memory

Info

Publication number: CN102290096A
Application number: CN2010102026811A
Authority: CN
Inventors: 黄效华
Original assignee: Individual
Current assignee: Individual
Priority date: 2010-06-18
Filing date: 2010-06-18
Publication date: 2011-12-21

Abstract

An internal control signal, an address line and a read small bit line data signal of a high-speed static random access memory are generated by one clock signal. A differential amplifier enabling signal of the small bit line signal is generated by the address line through logic matched with a bit line. When the parameters, such as process, temperature, voltage and the like, are changed, the delay change of the read differential amplifier enabling signal of the small bit line data signal is the same as that of the address line and the small bit line data signal.

Description

The decoding of static RAM and logic control circuit

Technical field

Technical field is the design of storer.Especially, technical field is to have the decoding of high speed high reliability static RAM and the design of control logic circuit.

Background technology

Semiconductor RAM is made chip application separately in electronic equipment.Semiconductor RAM can be the part of chip also, is applied to CPU and system integrated chip, is used for storing data.Random access memory comprises storage unit, memory cell array, address decoding logic, the function logic of storage data write and read.In order to make random access memory realize writing data and function of reading data, need the function time sequence control logic, control the operation that concrete data write and read.

According to different application, random access memory is divided into different capacity densities and different power consumption and speed again.The present invention is the decoding and the logic control circuit of high speed static RAM.

Summary of the invention

The high speed static RAM comprises the address input of read and write, clock signal, read and write enable control signal, reading of data output signal and write data input signal; The high speed static RAM also comprises the memory cell array of being made up of row and column, the one-level decoding unit, the two-stage decode unit, data input cell, internal control signal generation unit and data read amplifier enable signal generation unit are exported and write to reading of data.Wherein control signal and address and data-signal are all produced by a clock signal, directly produce bit line small-signal difference amplifier enable signal by address wire.Control signal is aimed at automatically with address and data-signal.In technology, temperature, when parameters such as voltage changed, the delay of data-signal and control signal variation was consistent, and does not need to stay too much remaining sum between control signal and the data-signal.

Description of drawings

Shown in Figure 1 is a typical sram storage element.

Shown in Figure 1A is the schematic diagram of high-speed random access memory of the present invention.

Shown in Figure 2 is the example of an enforcement of high-speed random access memory of the present invention.

Concrete form of implementation

Shown in Figure 1A is the schematic diagram of a typical high-speed random access memory.Storage array I103 comprises that 64 row and 128 array storage units are used for storing data.Typical sram storage element as shown in Figure 1.Random access memory shown in Figure 1A comprises single level address decoding unit I101 and two-level address decoding unit I102, data read amplifying circuit and data write circuit I105, the control signal generation circuit I104 of data read sense amplifier (the abbreviation SA of Sense Amplifier).

The data read principle of work of high-speed random access memory: clock signal, the address of reading of data is an input signal with reading to control enable signal; With the address of reading of data with after reading to control enable signal and latching, one-level decoding is carried out in 101 pairs of addresses of module I at clock, and 64 row address lines need 6 inputs, and one-level is decoded as 3 groups of 2:4 decodings or 2 groups of 3:8 decodings.Two-stage decode module I 102 be 3 inputs with door (corresponding 3 groups of 2:4 one-level decoding) or be 2 inputs with door (the one-level decodings of corresponding 2 groups of 3:8).Produce 64 address wires after finishing two-stage decode, corresponding a kind of 6 bit address input of each address wire combination.With another kind of saying is corresponding each 6 input combinations, has only the current potential of an address wire to be uprised by low, opens the storage unit to going.The current potential of address line WL101 is uprised by low as shown in Figure 1, and the switching tube M105 and the M106 of storage unit open, and differential bit line BL101 and BL101B are connected to the node N1101 and the N1102 of storage data and complementary data.Because 128 array storage units are arranged, thus there are 128 pairs of differential bit line to be used for reading data in every capable corresponding stored unit, and each bit line connects 64 (64 row) storage unit.Usually before reading of data, all bit lines all are charged to noble potential, when some address wires changed to noble potential by electronegative potential, the switching tube of the storage unit of this row was opened, and the back end of its storage and complementary data node are connected to corresponding bit lines and paratope line.The node of data and complementary data node are respectively low (height) current potential and height (low) current potential, and the bit line or the paratope line that connect the electronegative potential node will be discharged, and the current potential of bit line slowly descends from noble potential.The line number of storage array is many more, and the storage unit that each bit line connects is many more, and the load capacitance on the bit line is just big more, and the speed that the switching tube discharge by a storage unit of opening descends the bit line current potential is just slow more.Module I 105 comprises that little signal difference sense amplifier is shown in the I209 of Fig. 2, the differential input end mouth of each little signal difference sense amplifier connects one group of bit line and paratope line respectively, the current potential difference of pairs of bit line and paratope line is amplified, little signal is zoomed into the digital signal of corresponding noble potential and electronegative potential, finish data read.

The data of high-speed random access memory write principle of work: similar with data read, clock signal is the latch address signal simultaneously, write control signal and the data-signal that will write.Address signal behind the two-stage decode, has the current potential of an address wire to be uprised by low through one-level, opens the storage unit to going.The current potential of address line WL101 is uprised by low as shown in Figure 1, and the switching tube M105 and the M106 of storage unit open, and differential bit line BL101 and BL101B are connected to the node N1101 and the N1102 of storage data and complementary data.In decoding, write data circuit among the I105 writes differential bit line BL101 (BL101B) and BL101B (BL101) respectively with data and complementary data, make it be in digital noble potential and electronegative potential respectively, switching tube M105 by the storage unit opened and M106 finish the node N1101 and the N1102 of storage data and complementary data in the current potential write storage unit of bit line and paratope line data and write.

In data read process, when open the difference sense amplifier, does it is started working amplify the little signal of the potential difference (PD) on the differential bit line? if that opens is too early, bit line (paratope line) does not have enough discharge times, potential difference (PD) on the differential bit line is less than the resolution of difference sense amplifier, and result amplified may be wrong.If that opens is late excessively, bit line (paratope line) has enough discharge times, and the current potential difference on the differential bit line is much larger than the resolution of difference sense amplifier, guarantee that result amplified is correct, but wasted the time, made the data read overlong time of random access memory, speed is slack-off.So produce the enable signal of difference sense amplifier, make it at the current potential difference of differential bit line resolution threshold greater than sense amplifier, surpass threshold value again and open sense amplifier when too many and make it begin amplification work, could guarantee quick correctly reading of data the current potential difference of differential bit line.

It is complicated that actual data read process, situation are also wanted.When address and read control signal are latched by clock signal, through firsts and seconds decoding, the current potential of an address wire is uprised by low, open the storage unit pairs of bit line (paratope line) that go is discharged, the potential difference (PD) of differential bit line and paratope line is reached and, open the enable signal of sense amplifier then greater than the resolution threshold of sense amplifier.The potential difference (PD) that is latched into differential bit line and paratope line by clock signal from address and read control signal reach and greater than the time delay of the resolution threshold of sense amplifier with manufacturing process, the voltage difference of temperature and high electronegative potential different and changing.Thereby the enable signal of desirable sense amplifier is with manufacturing process, the voltage difference of temperature and high electronegative potential different and the delay that causes change should be reach with the above-mentioned potential difference (PD) that is latched into differential bit line and paratope line by clock signal from address and read control signal and greater than the time delay of the resolution threshold of sense amplifier with manufacturing process, the voltage difference of temperature and high electronegative potential different and variation that cause is consistent.

Fig. 2 is the example of the specific implementation of Figure 1A of the present invention.Clock signal clock produces internal control signal clk1 and clk2 by time sequence control logic module I 206.Input Address A0 is latched to I205 by latch I201 by signal clk1 to A5, begins the decoding logic function by signal clk2 then.N3 and N4 realize one-level decoding, and N1 and N2 realize two-stage decode.Address wire w1 opens storage unit that should row address line is discharged to differential bit line bl or blb.By I207, N5 and N6 produce the enable signal SAEN of sense amplifier SA by wl.

The generation unit of the enable signal of sense amplifier of the present invention (Sense Amplifier abridge SA) such as the I104 among Figure 1A and the I207 among Fig. 2 are driven by the address wire signal.So the delay of the wl from clock signal clock to bit line of address signal such as Fig. 2 is identical (because shared decoding scheme) with the delay of the drive signal wl of the generation unit I207 of the enable signal of (sense amplifier abridge SA) from clock signal clock to sense amplifier.And with manufacturing process, it also is identical that the voltage difference of temperature and high electronegative potential different and delay that cause change.I207 Module Design among Fig. 2 is to make the delay of this module from wl to dbl with manufacturing process, the voltage difference of temperature and high electronegative potential different and the variation that causes with from wl to bit line bl and blb form time delay greater than the resolution threshold of sense amplifier with manufacturing process, the voltage difference of temperature and high electronegative potential different and variation that cause is consistent.And the time delay from wl to SAEN greater than from wl to sal and the voltage difference of salb greater than the time delay of the resolution threshold of sense amplifier.Thereby guarantee that the data that sense amplifier reads are correct.The design of I104 among Figure 1A is identical with I207 Module Design among Fig. 2.

Although the illustrative implementation of this reference the decoding of high speed high reliability static RAM and the design of control logic circuit, the present invention is equally applicable to the design of other storer, as addressable memory, the design of triple addressable memories and dynamic storage (DRAM).And for those of ordinary skill in the art, obviously can carry out various deformation, the present invention openly is intended to cover its all distortion.

Claims

1. storer comprises:

The address signal of read and write, clock signal, reading of data output signal and write data input signal;

By the memory cell array that row and column is formed, the address decoder unit, data input cell, internal control signal generation unit are exported and write to reading of data;

Address wire, differential bit line; With

Sense amplifier, the enable signal generation unit of the enable signal of sense amplifier and the sense amplifier that drives by address wire.

2. storer according to claim 1, wherein the enable signal of address decoder unit is clock signal or is produced by the internal control signal generation unit by clock signal, the address decoder unit comprises level decode unit and secondary decoding unit, and the address decoder unit produces address wire.

3. storer according to claim 1, wherein each row of the memory cell array of being made up of row and column is connected by address wire, and each row is connected by differential bit line, and each connects sense amplifier to differential bit line.

4. storer according to claim 1, the enable signal generation unit of the sense amplifier that its address wire drives produces the enable signal of sense amplifier.

5. storer according to claim 1, wherein the time delay that produced of the enable signal generation unit of sense amplifier is with manufacturing process, the variation of the voltage difference of temperature and high electronegative potential and the variation that causes with from the address wire to the differential bit line and paratope line form time delay greater than the current potential difference of the resolution threshold of sense amplifier with manufacturing process, the variation of the voltage difference of temperature and high electronegative potential and the variation that causes is identical or consistent.

6. storer according to claim 1, wherein the time delay from the enable signal generation unit of address wire signal by sense amplifier to the enable signal of sense amplifier is greater than discharge makes the time delay of the input voltage difference of sense amplifier greater than the resolution threshold of sense amplifier to differential bit line by storage unit from the address wire signal.