CN102280411A - Method for manufacturing semiconductor device structure - Google Patents
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- CN102280411A CN102280411A CN2010102038289A CN201010203828A CN102280411A CN 102280411 A CN102280411 A CN 102280411A CN 2010102038289 A CN2010102038289 A CN 2010102038289A CN 201010203828 A CN201010203828 A CN 201010203828A CN 102280411 A CN102280411 A CN 102280411A
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Abstract
The invention discloses a method for manufacturing a semiconductor device structure, which comprises the following steps of: providing a substrate with an ion trap, wherein a grid structure corresponding to the ion trap is formed above the substrate; forming a first clearance wall structure consisting of a first side wall layer structure, a first offset side wall layer structure and a first pad oxide layer structure from outside to inside in sequence on the periphery of the grid structure; forming an epitaxial region on the substrate; removing the first side wall layer in the first clearance wall structure; forming a lightly doped region at a position which is positioned at the inner side of the epitaxial layer in the substrate and is closely adjacent to the epitaxial region, wherein part of the lightly doped region is positioned below the first offset side wall layer structure; and forming a second side wall layer structure at the outer side of the first offset side wall layer structure, and forming a source/drain region in the substrate to obtain the semiconductor device structure. According to the method disclosed by the invention, an LDD (Lightly Doped Drain) region and the epitaxial region are coincided less, and the epitaxial film loss of the grid structure, generated when the first offset side wall layer structure is formed, can be reduced.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of method of making semiconductor device structure.
Background technology
Along with being showing improvement or progress day by day of semiconductor integrated circuit manufacturing process, the size of grid is more and more littler, and conducting channel is also shorter and shorter, and the PN junction leakage current of formation is also more and more obvious to the Effect on Performance of semiconductor device structure.If do not change the constituent or the structure of semiconductor device, only simple scaled semiconductor device can become infeasible because of its drain saturation current (IDSS) is excessive, reduces IDSS so semiconductor device can change the composition or the structure of some members in scaled.Typical semiconductor device structure can be complementary metal oxide (CMOS) device architecture.This cmos device structure comprises grid, source electrode and drain electrode.Zone in source electrode (S) and the close gate bottom of drain electrode (D) also is formed with lightly doped region (LDD district).
Light doping section comprises the lightly doped drain injection, and (described light doping section is used to define source/drain (S/D) expansion area of cmos device structure for Lightly Doped Drain, LDD) district and pocket type district (Pocket) ion implanted region.LDD impurity is positioned at the grid below and is close to the channel region edge, and Pocket impurity is positioned at below, LDD district and is close to the channel region edge, is the S/D district impurity concentration gradient is provided.
PMOS zone with semiconductor device structure is that example is elaborated below, and particularly, the method for the S/D expansion area in preparation PMOS zone can be as follows: at first, form grid structure on the Semiconductor substrate with N trap.Then, both sides at this grid structure form the clearance wall structure, and wherein, described clearance wall structure comprises successively that from the outside to the inboard (with the grid structure is the center for oxygen pad layer structure and side wall layer structure, away from grid structure be the outside, near grid structure be the inboard).Secondly, in the both sides of above-mentioned clearance wall structure and be close on the substrate of clearance wall structure and form the epitaxial region, moreover remove the side wall layer structure that described clearance wall structure comprises.Between epitaxial region on the substrate and above-mentioned oxygen pad layer structure, form light doping section (LDD district) then.Form the needed side wall layer structure of clearance wall structure at last once more, and form the source/drain in PMOS zone by the heavy doping mode near the substrate of shallow channel isolation area.The epitaxial region in above-mentioned PMOS zone is to be used to guide stress to channel region, and foreign ion reduces along conducting channel direction concentration gradient in the described LDD district, and is used for reducing the PN junction leakage current of the semiconductor device structure of formation.
Yet the problem that above-mentioned technology occurs is: LDD district and epitaxial region in the PMOS zone of preparation often overlap.Thus, cause epitaxial region and LDD district mutual restriction, cause the effects of strain of epitaxial region to reduce, make described LDD district can not reduce the leakage current and the electromotive force above the depletion layer of the actual PMOS of being applied to zone of the PMOS zone PN junction of formation simultaneously, and then can't reduce the power consumption of semiconductor device structure, can not get the semiconductor device structure of realistic technology.Therefore, in the preparation semiconductor device structure, how avoiding the LDD district of regions and source to overlap with the epitaxial region becomes the current technical issues that need to address.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order effectively to address the above problem, the present invention proposes a kind of method of making semiconductor device structure, comprise the following steps:
One substrate with ion trap is provided, and this substrate top is formed with grid structure that should ion trap;
Form the first clearance wall structure in the periphery of described grid structure, this first clearance wall structure comprises the first side wall layer structure, the first skew side wall layer structure and the first oxygen pad layer structure from outside to inside successively;
The position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate forms the epitaxial region;
Remove the first side wall layer structure in the described first clearance wall structure;
The position that is positioned at the inboard of described epitaxial region and is in close proximity to described epitaxial region in described substrate forms light doping section, and the part of this light doping section is positioned at the below of the described first skew side wall layer structure; And
The outside in the described first skew side wall layer structure forms the second side wall layer structure, and in described substrate formation source/drain region, obtain described semiconductor device structure.
Further, when described ion trap was the N trap, described epitaxial region was the SiGe epitaxial region;
When described ion trap was the P trap, described epitaxial region was the silicon carbide epitaxy district.
Further, the position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate forms the epitaxial region and further comprises:
When described ion trap was the N trap, the position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate formed groove, and in described groove, fill germanium, silicon atom forms the SiGe epitaxial region;
When described ion trap was the P trap, the position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate formed groove, and in described groove, fill carbon, silicon atom forms the silicon carbide epitaxy district.
Further, the generation type of the described first oxygen pad layer structure is that furnace oxidation method, rapid thermal oxidation method or original position steam produce oxidizing process;
The generation type of the described first skew side wall layer structure, described the first side wall layer structure and the described second side wall layer structure is low-pressure chemical vapor deposition, medium-sized air pressure chemical vapour deposition (CVD) or plasma activated chemical vapour deposition.
Further, described periphery at described grid structure forms the first clearance wall structure and further comprises:
Form the described first oxygen pad layer structure in the outside of described grid structure; Then the upper surface in described substrate and the described first oxygen pad layer structure deposits first skew side wall layer and the first side wall layer successively, and etching described first is offset side wall layer and described the first side wall layer successively, obtains described first skew side wall layer structure and the first side wall layer structure.
Further, described periphery at described grid structure forms the first clearance wall structure and further comprises:
Form the described first oxygen pad layer structure in the outside of described grid structure;
In the upper surface deposition first skew side wall layer of described substrate and the described first oxygen pad layer structure, this first skew side wall layer of etching obtains the described first skew side wall layer structure; And
At the upper surface deposition the first side wall layer of described substrate and the described first skew side wall layer structure, this first side wall layer of etching obtains described the first side wall layer structure.
Further, described grid structure comprises: the gate insulator and the gate metal layer that is positioned at described gate insulator top that are positioned at described substrate top.
Further, the material of the described first oxygen pad layer structure, the described first skew side wall layer structure, described the first side wall layer structure and the described second side wall layer structure is oxide, nitride or both compositions.And employing gas is SiH
4, TEOS, O
2And O
3Mist to prepare material be the described first skew side wall layer structure of oxide, described the first side wall layer structure and the described second side wall layer structure; Employing gas is DCS, SiH
4And NH
3Mist to prepare material be the described first skew side wall layer structure of nitride, described the first side wall layer structure and the described second side wall layer structure.
Further, when described ion trap was the N trap, the impurity of described light doping section was boron or BF
2
When described ion trap was the P trap, the impurity of described light doping section was phosphorus or arsenic.
According to the method for preparing semiconductor device structure of the present invention, before forming the epitaxial region, form the clearance wall structure earlier, this clearance wall structure comprises the first oxygen pad layer structure, first skew side wall layer structure and the first side wall layer structure from inside to outside, then remove described the first side wall floor structure and form the LDD district, promptly prepare the S/D expansion area of semiconductor device structure.The technology of the semiconductor device structure by the inventive method preparation can make less the overlapping in LDD district and epitaxial region, loses but also can reduce at the epitaxial film (the first oxygen pad layer structure) that forms first grid structure that produces when being offset the side wall layer structure.In addition,, the formation in LDD district injects because being offset a certain angle by ion, and thus can be so that the LDD district more approaches the below of the grid structure in the layout design.Further, reduced the IDSS (leakage current) of the semiconductor device structure that forms by method of the present invention, and the power consumption that has reduced semiconductor device structure, and improved the breakdown characteristics of semiconductor device structure, and then improved the performance of the semiconductor device structure of preparation.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A is the generalized section for preparing semiconductor device structure according to embodiments of the invention to Fig. 1 J;
Fig. 2 A and Fig. 2 B are the SEM figure of the semiconductor device structure for preparing in the prior art;
Fig. 2 C and Fig. 2 D are the SEM figure according to the semiconductor device structure of embodiments of the invention preparation;
Fig. 3 is the process chart of the semiconductor device structure of method preparation according to an embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that how explanation the present invention improves the technology of making semiconductor device structure to solve the problems of the prior art.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
Method among the present invention can be implemented on the PMOS zone of semiconductor device structure or nmos area territory, or implements simultaneously on PMOS zone and nmos area territory, and the present invention does not limit it, and sets according to the process requirements of reality.Following embodiment describes with single PMOS zone.
Shown in Figure 1A, provide to include the Semiconductor substrate 101 of shallow trench isolation from (STI) structure 102 and ion trap, described Semiconductor substrate can be silicon, germanium, GaAs or silicon Germanium compound.When described ion trap was the N trap, these Semiconductor substrate 101 zones belonged to PMOS zone 103, and when described ion trap was the P trap, described Semiconductor substrate 101 zones belonged to the nmos area territory.Below be that example describes with PMOS zone 103, the ion in the described N trap can be a phosphorus, the energy of injection can be 250KeV to 300KeV, dosage is 3e
13Atom/cm
2
Above described Semiconductor substrate 101, be formed with first grid structure 104; this first grid structure 104 comprises the first grid insulating barrier 105 of substrate 101 tops and is positioned at the first grid metal level 106 of described first grid insulating barrier 105 tops; preferably, can above getting, this first grid metal level 106 be formed for protecting the mask layer of grid.Described first grid insulating barrier 105 can be HfO
2Or the material of other insulating properties, and described first grid insulating barrier 105 can be by chemical vapour deposition (CVD) formation or plasma gas phase deposition formation, and its thickness is preferably between 5 dust to 20 dusts.Described first grid metal level 106 can be hafnium (K is a dielectric constant), or the metal oxide materials of other easy conductive, its thickness range can be 5 dust to 30 dusts, the generation type of this first grid metal level 106 can be implemented by aumospheric pressure cvd or low-pressure chemical vapor deposition, or implements by plasma activated chemical vapour deposition or atomic layer deposition method.
Then, shown in Figure 1B, form the first pad oxide structure 107 ' in the outside of described first grid structure 104, the material of this first oxygen pad layer structure 107 ' can be oxide or nitride, as being silicon nitride, silicon oxynitride or above-mentioned composition etc.In addition, the formation method of this first oxygen pad layer structure 107 ' can produce oxidizing process for furnace oxidation method, rapid thermal oxidation method or original position steam, and its gas of selecting for use is oxygen, nitrogen, NO, N
2O and H
2The mist of O etc.The thickness of the first oxygen pad layer structure 107 ' of described first grid structure 104 outer surfaces is approximately 1～4 nanometer.
Shown in figure 1C to 1E, form first skew side wall layer 108 and the first side wall layer 109 successively at the structure upper surface shown in Figure 1B, and etching or graphical described first skew side wall layer 108 and the first side wall layer 109, make the clearance wall structure of its formation shown in Fig. 1 E.The etching mode of described first skew side wall layer 108 and the first side wall layer 109 is the dry etching mode, and its corresponding etching gas can be CF
4, HBr, He and O
2Deng mist.Clearance wall structure shown in Fig. 1 E comprises the first side wall layer structure 109 ', the first skew side wall layer structure 108 ' and the first oxygen pad layer structure 107 ' successively from the outside to the inboard.In the present embodiment, be the center with first grid structure 104, be the outside away from first grid structure 104, be inboard near first grid structure 104.Need to prove that form in the process of clearance wall structure in etching, the protective layer directly over the described first grid structure 104 i.e. first oxygen pad layer structure 107 ' is not etched.
Especially, the material of described first skew side wall layer structure 108 ' and the first side wall layer structure 109 ' can be oxide or nitride, as being silicon nitride, silicon oxynitride or above-mentioned combination etc.Wherein, the generation type of the first skew side wall layer 108 and the first side wall layer 109 can adopt low-pressure chemical vapor deposition, medium-sized air pressure chemical vapour deposition (CVD) or plasma activated chemical vapour deposition etc., and the deposit thickness of the described first skew side wall layer 108 is between 5～15 nanometers, and the deposit thickness of the first side wall layer 109 is between 10～25 nanometers.When described first was offset the material selection oxide of side wall layer structure 108 ' and the first side wall layer structure 109 ', the gas that deposits described first skew side wall layer 108 and the first side wall layer 109 can be SiH
4, TEOS, O
2And O
3Deng mist; When described first was offset the material selection nitride of side wall layer structure 108 ' and the first side wall layer structure 109 ', the gas that deposits described first skew side wall layer 108 and the first side wall layer 109 can be DCS, SiH
4And NH
3Deng mist.
Shown in figure 1E, described clearance wall structure is positioned at the outer surface of described first grid structure 104.The generation type of described clearance wall structure can be to form the first oxygen pad layer structure 107 ' earlier in the outside of first grid structure 104, after forming first skew side wall layer 108 and the first side wall layer 109 by the inboard successively to the outside again, etching/graphical described first skew side wall layer 108 and the first side wall layer 109 make it form first skew side wall layer structure 108 ' and the first side wall layer structure 109 ' and then obtain above-mentioned clearance wall structure simultaneously.Alternatively; clearance wall structure shown in Fig. 1 E can also be to form the first oxygen pad layer structure 107 ' earlier; secondly the upper surface in described substrate 101 and the described first oxygen pad layer structure 107 ' forms the first skew side wall layer 108; this first skew side wall layer 108 of etching; obtain the described first skew side wall layer structure 108 '; then the upper surface in described substrate 101 and the described first skew side wall layer structure 108 ' forms the first side wall layer 109; etching the first side wall layer 109; obtain described the first side wall layer structure 109 ', the clearance wall structure that this mode is obtained also should be noted that the i.e. first oxygen pad layer structure 107 ' of the protective layer that can not etch away directly over the above-mentioned first grid structure 104.This protective layer can be first oxygen pad layer structure 107 ' or the mask layer, and in the present embodiment, described protective layer is the first oxygen pad layer structure 107 '.Certainly, the preparation technology of this first skew side wall layer structure 108 ' or the first side wall layer structure 109 ' can carry out in different etching apparatuss successively, also can original position carry out in same etching apparatus.When the preparation first clearance wall structure in same equipment, the described adjacent first oxygen pad layer structure 107 ', the first skew side wall layer structure 108 ' are different with the first side wall layer structure 109 ' selected material.
Then, shown in figure 1F, the position that is positioned at the outside of described the first side wall layer structure 109 ' and is in close proximity to described the first side wall layer structure 109 ' on described Semiconductor substrate 101 forms epitaxial region 110, and this epitaxial region 110 is in close proximity to described the first side wall layer structure 109 '.Preferably can make this epitaxial region 110 between described clearance wall structure and sti structure.Particularly, in the Semiconductor substrate 101 that is in close proximity to described the first side wall layer structure 109 ', form groove, promptly in the outside that is positioned at described the first side wall layer structure 109 ' and the substrate location that is in close proximity to described the first side wall layer structure 109 ' form groove, groove formation method such as can be at tropism and/or anisotropic dry etching, its degree of depth is the 0-1000 dust, is preferably the 250-650 dust.Then in described groove, fill germanium, silicon atom, its extension reaction is formed have the SiGe that can produce compression, for use in the carrier mobility that improves source/drain electrode in this PMOS zone.The silicon source precursor gas that described SiGe epitaxial region adopts can be SiH
4Or SiH
2Cl
2, corresponding flow can be 30～300sccm, germanium source precursor gas can be GeH
4, HCl, hydrogen etc. mist, corresponding GeH
4Flow is 5～500sccm, preferred GeH
4Flow is 5～50sccm, and the flow of HCl gas is 50～200sccm, and the flow of hydrogen can be 5～50slm.Preferably above-mentioned silicon source precursor gas and germanium source precursor gas are blended in the cavity the inside and react, form SiGe in the groove with compressive strain thereby be implemented in.The SiGe epitaxial region can cause compression at channel region usually, therefore can strengthen the carrier mobility in PMOS zone in the semiconductor device structure.
Secondly, with reference to figure 1G shown in, the first side wall layer structure 109 ' in the removal clearance wall structure, the protective layer of removing simultaneously directly over the described first grid structure is the first oxygen pad layer structure 107 '.The removing method at this place can adopt the wet etching mode, and its selected solution can be hot phosphoric acid, and HF or RCA etc. select the process requirements configuration of the concentration of solution according to reality for use.
Follow again, shown in figure 1H, the position that is positioned at the inboard of described epitaxial region 101 and is in close proximity to described epitaxial region 101 in described Semiconductor substrate 101 forms light doping section 111, and part light doping section 111 is positioned at the below of the described first skew side wall layer structure 108 '.It mainly is to form light dope (LDD) district 111 by the ion injection mode in Semiconductor substrate 101.The ion injection direction in described LDD district can be with vertical direction inclination miter angle or tilt greater than miter angle, preferred angular range is that 30 degree are to 75 degree, so that make the LDD district be positioned at as much as possible the described first skew side wall construction 108 ' under, reduce and the overlapping of epitaxial region 110.The impurity that the ion that described LDD district is injected promptly mixes can be boron or BF
2Deng, implantation dosage can be 1e
13～3e
15Atom/cm
2Alternatively, the position that is positioned at the inboard of described epitaxial region 110 and is in close proximity to described epitaxial region 110 in described substrate 101 forms a plurality of light doping sections 111, and these a plurality of light doping sections partly are positioned at the below of the described first skew side wall layer structure 108 '.
Shown in figure 1I, the outside in the described first skew side wall layer structure 108 ' forms the second side wall layer structure 112, the generation type of the described second side wall layer structure 112 is similar to the generation type of the first side wall layer structure 109 ', and the material of this second side wall layer structure 112 also can be nitride, oxide or both combinations etc.
Last with reference to shown in the figure 1J, the position that is positioned at the outside of the described second side wall layer structure 112 and is in close proximity to the second side wall layer structure 112 in described Semiconductor substrate 101 forms heavily doped region, this heavily doped region is between described second side wall layer structure 112 and sti structure 102, formation is corresponding to the source/drain electrode 113 in PMOS zone, and then obtains the needed PMOS of semiconductor device structure zone.Described heavily doped ion can be boron, BF
2Deng, dosage can be 1e
13～3e
15Atom/cm
2
The method in the PMOS zone of Zhi Bei semiconductor device structure to sum up, this PMOS zone has and the 110 less LDD districts 111 that overlap, epitaxial region, make the epitaxial region 110 in this PMOS zone can improve the mobility of charge carrier rate preferably, and the drain saturation current that described LDD district 111 can reduce in the semiconductor device structure, method of the present invention thus can improve the electric property of the semiconductor device structure of preparation.
According to a further aspect in the invention, the method in the PMOS zone of above-mentioned preparation semiconductor device structure also goes for the preparation process in nmos area territory.S/D district for preparation nmos area territory also can adopt above-mentioned mode, and its difference is, forms the silicon carbide epitaxy district by filling carbon atom in the groove in described nmos area territory, and this silicon carbide epitaxy district is used to provide tensile stress.In addition, the impurity that mixes for the LDD district in nmos area territory can be phosphorus and arsenic etc., and corresponding dosage can be 1e
13～3e
15Atom/cm
2Particularly, at first, on semiconductor substrate region, form the second grid structure with P trap, and the outside in this second grid structure forms and above-mentioned similar clearance wall structure, and this clearance wall structure comprises the first side wall layer structure 109 ', the first skew side wall layer structure 108 ' and the first oxygen pad layer structure 107 ' successively from the outside to the inboard.Then, the position that is positioned at the outside of described the first side wall floor structure 109 ' and is in close proximity to described the first side wall floor structure 109 ' on the Semiconductor substrate in nmos area territory forms the silicon carbide epitaxy district, particularly, the position that is positioned at the outside of described the first side wall layer structure 109 ' and is in close proximity to described the first side wall layer structure 109 ' on described substrate forms groove, and in described groove, fill carbon, silicon atom forms the silicon carbide epitaxy district.Then, remove the first side wall layer structure 109 ' in the above-mentioned clearance wall structure, the substrate in described nmos area territory is carried out light dope, form light doping section, this light doping section is positioned at the inboard of described epitaxial region and is in close proximity to the position of described epitaxial region.Then form the second side wall layer structure 112 again in the outside of the described first skew side wall layer structure 108 ', and the substrate in nmos area territory carried out heavy doping, obtain the source/drain in nmos area territory, described heavily doped region is between this second side wall layer structure 112 and sti structure 102, the impurity of heavily doped region can make phosphorus, arsenic etc., and dosage is 1e
13～5e
15Atom/cm
2
Preferably, zone of the PMOS in the described semiconductor device structure and nmos area territory can be carried out simultaneously.Particularly, when a certain operation in preparation PMOS zone, as " the etching first skew side wall layer ", " etching the first side wall layer ", " formation groove structure " or " epitaxial region " etc., can adopt mask or photoresist that the nmos area territory of semiconductor device structure is covered.Accordingly, when the nmos area territory is operated, can adopt mask or photoresist to cover described PMOS zone.Certainly, the nmos area territory of above-mentioned preparation semiconductor device structure and PMOS zone still are to be prepared at single zone simultaneously, and it mainly is to select according to actual process equipment.
Shown in figure 2A and Fig. 2 B, Fig. 2 A and Fig. 2 B are respectively the SEM figure of the semiconductor device structure for preparing in the prior art.The generation type in the LDD district of the example shown in Fig. 2 A is after forming oxygen pad layer structure and side wall layer structure earlier, to form the epitaxial region again, and then remove described side wall layer structure, then forms skew side wall layer structure and LDD district.As can be seen from the figure, the more quilt in described LDD district and epitaxial region overlaps, and makes the SiGe of epitaxial region lost 5nm at least.
Be compared to Fig. 2 C and Fig. 2 D, Fig. 2 C and Fig. 2 D are the SEM figure according to the semiconductor device structure of embodiments of the invention preparation.By the foregoing description obtain the less coincidence in described LDD district and epitaxial region that shows among the SEM figure of semiconductor device structure.Thus, be pre-formed clearance wall structure in the present invention with the first side wall layer, form the epitaxial region again, remove described the first side wall layer structure afterwards, the method that then forms light doping section can make the less coincidence in LDD district and epitaxial region in finally prepd PMOS zone, and then make the epitaxial region play the effect of compression preferably to the source/drain electrode in PMOS zone, the electromotive force on LDD district leakage current that can also effectively reduce PN junction and the depletion layer that is applied to the PMOS zone simultaneously, and then reduced the power consumption of semiconductor device structure.Leakage current according to the semiconductor device structure of the present invention preparation is less, has improved the electric property of semiconductor device structure.
With reference to shown in Figure 3, Fig. 3 is the process chart of the semiconductor device structure of method preparation according to an embodiment of the invention, and concrete steps comprise:
Step 301: a substrate with ion trap is provided, and this substrate top is formed with grid structure that should ion trap;
Step 302: form the first clearance wall structure in the periphery of described grid structure, this first clearance wall structure comprises the first side wall layer structure, the first skew side wall layer structure and the first oxygen pad layer structure from outside to inside successively;
Step 303: the position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate forms the epitaxial region;
Step 304: remove the first side wall layer structure in the described first clearance wall structure;
Step 305: the position that is positioned at the inboard of described epitaxial region and is in close proximity to described epitaxial region in described substrate forms light doping section, and the part of this light doping section is positioned at following ten thousand of the described first skew side wall layer structure; And
Step 306: the outside in the described first skew side wall layer structure forms the second side wall layer structure, and forms source/drain region in described substrate and in the outside of the second side wall layer structure, obtains described semiconductor device structure.
In addition, when described ion trap was the N trap, the position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate formed groove, and filled germanium atom form the SiGe epitaxial region in described groove;
When described ion trap was the P trap, the position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate formed groove, and filled carbon atom form the silicon carbide epitaxy district in described groove.
Semiconductor device structure according to aforesaid embodiment manufacturing can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio-frequency devices or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
It is pointed out that each structure in the cutaway view only shows with schematic form, does not represent the proportionate relationship between each structure.A certain zone described in the invention or certain one deck structure " on ", " top ", " upper surface ", mean corresponding to directly over this zone or this one deck structure, and do not comprise the part of top of other zone or layer structure.
The present invention is illustrated by the foregoing description, but should be understood that, the foregoing description just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to the foregoing description, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. a method of making semiconductor device structure is characterized in that, described method comprises the following steps:
One substrate with ion trap is provided, and this substrate top is formed with grid structure that should ion trap;
Form the first clearance wall structure in the periphery of described grid structure, this first clearance wall structure comprises the first side wall layer structure, the first skew side wall layer structure and the first oxygen pad layer structure from outside to inside successively;
The position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate forms the epitaxial region;
Remove the described the first side wall layer structure in the described first clearance wall structure;
The position that is positioned at the inboard of described epitaxial region and is in close proximity to described epitaxial region in described substrate forms light doping section, and the part of this light doping section is positioned at the below of the described first skew side wall layer structure; And
The outside in the described first skew side wall layer structure forms the second side wall layer structure, and in described substrate formation source/drain region, obtain described semiconductor device structure.
2. the method for claim 1 is characterized in that, when described ion trap was the N trap, described epitaxial region was the SiGe epitaxial region;
When described ion trap was the P trap, described epitaxial region was the silicon carbide epitaxy district.
3. the method for claim 1 is characterized in that, the position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate forms the epitaxial region and further comprises:
When described ion trap was the N trap, the position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate formed groove, and in described groove, fill germanium, silicon atom forms the SiGe epitaxial region;
When described ion trap was the P trap, the position that is positioned at the outside of described the first side wall layer structure and is in close proximity to described the first side wall layer structure on described substrate formed groove, and in described groove, fill carbon, silicon atom forms the silicon carbide epitaxy district.
4. the method for claim 1 is characterized in that, the generation type of the described first oxygen pad layer structure is that furnace oxidation method, rapid thermal oxidation method or original position steam produce oxidizing process;
The generation type of the described first skew side wall layer structure, described the first side wall layer structure and the described second side wall layer structure is low-pressure chemical vapor deposition, medium-sized air pressure chemical vapour deposition (CVD) or plasma activated chemical vapour deposition.
5. the method for claim 1 is characterized in that, described periphery at described grid structure forms the first clearance wall structure and further comprises:
Form the described first oxygen pad layer structure in the outside of described grid structure; Then the upper surface in described substrate and the described first oxygen pad layer structure deposits first skew side wall layer and the first side wall layer successively, and etching described first is offset side wall layer and described the first side wall layer successively, obtains described first skew side wall layer structure and the first side wall layer structure.
6. the method for claim 1 is characterized in that, described periphery at described grid structure forms the first clearance wall structure and further comprises:
Form the described first oxygen pad layer structure in the outside of described grid structure;
In the upper surface deposition first skew side wall layer of described substrate and the described first oxygen pad layer structure, this first skew side wall layer of etching obtains the described first skew side wall layer structure; And
At the upper surface deposition the first side wall layer of described substrate and the described first skew side wall layer structure, this first side wall layer of etching obtains described the first side wall layer structure.
7. the method for claim 1 is characterized in that, described grid structure comprises: the gate insulator and the gate metal layer that is positioned at described gate insulator top that are positioned at described substrate top.
8. the method for claim 1 is characterized in that, the material of the described first oxygen pad layer structure, the described first skew side wall layer structure, described the first side wall layer structure and the described second side wall layer structure is oxide, nitride or both compositions.
9. method as claimed in claim 8 is characterized in that,
Employing gas is SiH
4, TEOS, O
2And O
3Mist to prepare material be the described first skew side wall layer structure of oxide, described the first side wall layer structure and the described second side wall layer structure;
Employing gas is DCS, SiH
4And NH
3Mist to prepare material be the described first skew side wall layer structure of nitride, described the first side wall layer structure and the described second side wall layer structure.
10. the method for claim 1 is characterized in that, when described ion trap was the N trap, the impurity of described light doping section was boron or BF
2
When described ion trap was the P trap, the impurity of described light doping section was phosphorus or arsenic.
11. an integrated circuit that comprises the semiconductor device structure of making by the method for claim 1, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
12. an electronic equipment that comprises the semiconductor device structure of making by the method for claim 1, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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