CN102279899B - Method for optimizing simplified standard unit library - Google Patents
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Abstract
本发明公开了一种对精简标准单元库进行优化的方法，该方法包括：选择实现所需电路功能的基本单元，该基本单元至少包括反相器、缓冲器、基本门单元、混合门单元、运算单元和时序单元；在精简标准单元库中增加延迟单元、上拉/下拉单元、填充单元、电容填充单元、衬底链接以及天线效应抑制单元；采用逻辑分解方式选择多输入逻辑；以及采用驱动分解方式实现多驱动能力。本发明在电路的性能和实现复杂度上面做折中，减少了版图图形形状的个数，有利于光刻友好，使可分辨率增强，提高了电路的可制造性和实现的高效性，又在一定程度上保证了电路的性能。
The invention discloses a method for optimizing a simplified standard cell library. The method includes: selecting a basic unit for realizing required circuit functions, the basic unit at least including an inverter, a buffer, a basic gate unit, a mixed gate unit, Operation unit and sequential unit; add delay unit, pull-up/pull-down unit, filling unit, capacitor filling unit, substrate link and antenna effect suppression unit in the streamlined standard cell library; use logic decomposition to select multi-input logic; and use drive The decomposition method realizes multiple drive capabilities. The present invention makes a compromise between the performance of the circuit and the implementation complexity, reduces the number of layout graphic shapes, is conducive to photolithography friendliness, enhances the resolution, improves the manufacturability and high efficiency of the implementation of the circuit, and To a certain extent, the performance of the circuit is guaranteed.
Description
Technical field
The present invention relates to 65 nanometer integrated circuit fabrication process and layout design technical field, be specifically related to a kind of method that is optimized simplifying standard cell lib.
Background technology
Standard cell lib is the necessary condition of LSI/VLSI the Automation Design, realizes supporting whole the Automation Design flow process from the front end functional simulation to the rear end domain.When the characteristic dimension of integrated circuit dropped to 65 nanometer, the IC manufacturing technology had run into unprecedented challenge, because design scale is increasing, complexity is more and more higher.Manufacturability has become a significant consideration of integrated circuit (IC) design, and from existing design cycle, the designing technique of 65 nanometer standard blocks also faces significant challenge.Standard cell lib carried out optimization is the step of a most critical for manufacturability.
The principle of setting up of traditional standard cell library is to wish to select abundant as far as possible cell type, so that the circuit synthesis instrument has more selection in combined process, realizes satisfying the various constraint conditions such as speed, power consumption and area with the cost of minimum.But, such standard cell lib so that during nanoprocessing the graph data pattern loaded down with trivial details, data processing amount is huge, is unfavorable for the circuit photoetching, makes the manufacturability problem face more complicated challenge, directly the impact efficient of producing.
In fact, in containing 400 standard cell libs more than the unit, be not each unit for the realization of logic function be essential.In general, the unit of high driving ability is that many input blocks then are in order to reduce area for satisfied nervous sequential requirement.For power consumption, generally each unit is designed with the low-power consumption type in the standard cell lib, the driving force of this unit generally is minimum, and for the use of this unit certain skill is arranged, and generally is obsolete not having in the special low power dissipation design requirement situation.And the consistent view of industry is, the design of the following scale of millions of doors is not need low power dissipation design, so the utilization rate of low-power consumption unit is lower.And a standard cell lib must comprise which unit does not have a definite standard, all designs by experience, and the function of most of unit can realize with elementary cell.
Therefore, when the scale down of a standard cell lib arrived to a certain degree, it was in speed, and power consumption, area aspect still are acceptables, will simplify the manufacturability problem like this, reduce data processing amount, have improved significantly production efficiency.
Summary of the invention
The technical matters that (one) will solve
Design and manufacturability problem in order to solve advanced ASIC digital circuit in the prior art the invention provides a kind of method that is optimized simplifying standard cell lib.
(2) technical scheme
In order to achieve the above object, the technical solution used in the present invention is:
A kind of method that is optimized simplifying standard cell lib, the method comprises:
Select to realize the elementary cell of required circuit function, this elementary cell comprises phase inverter, impact damper, Primitive gate, combination gates unit, arithmetic element and timing unit at least;
In simplifying standard cell lib, increase delay cell, draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit;
Adopt the logical breakdown mode to select many input logics; And
Adopt the driving is olation to realize many driving forces.
In the such scheme, described selection realizes the step of the elementary cell of required circuit function, be under the requirement that guarantees to realize required circuit function, to select the elementary cell that needs, by these elementary cells are carried out suitable logical combination, can travel through all complex logics.
In the such scheme, described delay cell, on draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit, be be used to the design requirement that satisfies the front and back end, guarantee to simplify the function that must realize in the standard cell lib and the functional unit that in simplifying standard cell lib, increases.
In the such scheme, described employing logical breakdown mode is selected in the step of many input logics, adopts by two 2 input logics for 4 input logics and realizes, perhaps adopts 13 input logic and 1 input logic to realize.
In the such scheme, described employing logical breakdown mode is selected in the step of many input logics, adopts by 2 input logics and 3 input logics for 5 input logics and realizes.
In the such scheme, described employing drives is olation and realizes in the step of many driving forces, for phase inverter and impact damper, has designed separately X4, X8 and X16, to alleviate the anxiety of sequential; Higher driving for other logic functions realizes that the mode that employing will have logic parallel connection or cascade now realizes the high logic that drives.
(3) beneficial effect
Compared with prior art, the beneficial effect of technical solution of the present invention generation is:
1, the present invention is by simplifying standard cell lib quantity, adopt unit the least possible, that really need to realize building of standard cell lib, reduced the number of domain graphics shape, be conducive to the photoetching close friend, distinguishable rate is strengthened, improved the manufacturability of circuit.
2, the utilization of the present invention thinking opposite with the traditional standard cell library, adopt unit the least possible, that frequently need to realize complicated as far as possible logic, thereby in the performance of circuit with do compromise above the implementation complexity, reduced the number of domain graphics shape, be conducive to the photoetching close friend, distinguishable rate is strengthened, improved the manufacturability of circuit and the high efficiency of realization, guaranteed to a certain extent again the performance of circuit.
Description of drawings
Fig. 1 is for simplifying the method flow diagram of standard cell lib according to the optimization of the embodiment of the invention;
Fig. 2 is for simplifying the synoptic diagram of standard cell lib unit list according to 65 nanometers of the embodiment of the invention;
Fig. 3 is for realizing the synoptic diagram of many driving forces according to the driving is olation of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
The present invention is in the situation that guarantees circuit performance, the unit kind that standard cell lib is comprised drops to a critical numerical value, namely adopt unit the least possible, that frequently need to travel through as far as possible all complex logics, thereby realize simplifying of cell library, simplify the manufacturability problem.
The method that is optimized simplifying standard cell lib provided by the invention comprises: select to realize the elementary cell of required circuit function, this elementary cell comprises phase inverter, impact damper, Primitive gate, combination gates unit, arithmetic element and timing unit at least; In simplifying standard cell lib, increase delay cell, draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit; Adopt the logical breakdown mode to select many input logics; And adopt the driving is olation to realize many driving forces.
Traditional standard cell lib comprises up to a hundred unit, yet a lot of unit performance impact to circuit when circuit synthesis is little.But, phase inverter for example, Sheffer stroke gate, the elementary cells such as rejection gate then often are used to, be make up circuit substantially must the unit.More complicated unit such as 8 input bonus point devices etc. seldom are used.The performance of circuit can not descend to some extent because of the minimizing of these unit.Because these complex unit utilization rates are very low, when really needing, the present invention can make up with basic simple unit, no matter be at circuit area, power consumption or sequential aspect, although with respect to complete standard cell lib loss is arranged like this, loss concentrates in this scope of 5%-10%, and being lost in the standard block zone in this scope is complete acceptable.Because reducing of characteristic dimension, in order to reduce the difficulty of manufacturability, the present invention expects to realize circuit function with the logical block of the least possible kind.Want to reach this target, must adopt certain method choice criteria unit.
The method that standard cell lib is optimized provided by the invention has been used the thinking opposite with the traditional standard cell library, and complicated as far as possible logic is realized in the unit of frequently need selecting, and specifically may further comprise the steps:
At first, realize under the requirement of all required circuit functions the elementary cell of need selecting guaranteeing, such as phase inverter, impact damper, Primitive gate, the combination gates unit, arithmetic element and timing unit, the suitable logical combination by these unit travels through all complex logics as far as possible.
Secondly, along with day by day dwindling of integrated circuit characteristic dimension, special process manufacturability problem has appearred in 65 nanometer nodes, as the standard cell lib of a practicality, the design requirement of consideration front and back end that must be complete, therefore the present invention introduces multiple special element, such as delay cell, on draw/drop-down unit, filler cells, the electric capacity filler cells, substrate link and antenna effect suppress the unit, to guarantee to simplify the function that must realize in the standard cell lib.
The 3rd, adopt logical breakdown mode (Decomposition) to select many input logics.For example, 4 input logics can be by two 2 input logics or 13 input logic and 1 an input logic realization, 5 input logics can be realized by 2 input logics and 3 input logics, so, more be optimization aspect the area for the many input logics role in cell library as 4 inputs and 5 are inputted, be and input square being directly proportional of number that therefore, high input logic gate generally has been negative interaction for postponing to optimize and gate delay is actual.And above-mentioned logical breakdown mode or highly effective can not introduced too many space wastage.
The 4th, adopt the driving is olation to realize many driving forces, in order to exceed the problem that solves driving force in the situation that increases the unit kind, the present invention takes following scheme: for phase inverter and impact damper, the present invention has designed separately X4, X8 and X16, its objective is the anxiety of alleviating sequential, higher driving for other logic functions realizes, the present invention is still in line with the principle that does not increase the unit kind as far as possible, the present invention adopts the mode that will have logic parallel connection or cascade now to realize the high logic that drives, this mode can be introduced must additional delay, but the transit time that can greatly improve output signal.And gate delay actual be all related with the transit time of output load and input signal, standard cell lib is the look-up table that the cell delay information in the .lib file done of EDA synthesis tool is made according to input signal transit time and two indexs of output load just.So, should cascade high driving ability phase inverter for whether and impact damper should be decided by synthesis tool.
The method of standard block library unit is simplified in optimization provided by the invention, the described standard cell lib of simplifying should comprise combinatorial logic unit, sequential logic unit and special applications unit, adopt logical breakdown mode (Decomposition) to select many input logics, adopt the driving is olation to realize many driving forces.Wherein, travel through whole design cell by combinatorial logic unit, the suitable combination in sequential logic unit and special applications unit, and effectively support the design of 65 nanometer special process circuit manufacturability.The method has reduced the number of domain graphics shape, is conducive to the photoetching close friend, and distinguishable rate is strengthened, and has improved the manufacturability of circuit and the high efficiency of realization.
Referring to Fig. 1, Fig. 1 is for simplifying the method flow diagram of standard cell lib according to the optimization of the embodiment of the invention, the method is the selection principle of analytical standard cell library elementary cell at first, and carry out the design of standard block as the basis take 65 nanometer SPICE MODEL of typical process manufacturer and DFM technical papers and other technical paperss.In the situation that guarantees circuit performance, the unit kind that standard cell lib is comprised drops to a critical numerical value, namely adopts unit the least possible, that frequently need to travel through as far as possible all complex logics.Thereby realize simplifying of cell library, simplify the manufacturability problem.
For the selection of simplifying the standard block library unit, phase inverter, impact damper, Sheffer stroke gate, rejection gate, XOR gate, trigger and latch often are used in the circuit design process, are basic necessary unit, in the necessary inclusive criteria cell library, as shown in Figure 2.Seldom be used when the circuit design for some complicated unit, the performance impact to circuit when circuit synthesis is little, and the performance of circuit can not descend to some extent because of the minimizing of these unit.When real needs they the time, the present invention makes up with basic simple unit, no matter be at circuit area, power consumption or sequential aspect, although with respect to complete standard cell lib loss is arranged like this, but loss concentrates in this scope of 5%-10%, and being lost in the standard block zone in this scope is complete acceptable.For many input logics, the present invention adopts logical breakdown mode (Decomposition) to select.For example, 4 input logics can be by two 2 input logics or 13 input logic and 1 an input logic realization, and 5 input logics can be realized by 2 input logics and 3 input logics.Above-mentioned logical breakdown mode or highly effective can not introduced too many space wastage.This has added basic logical block so that carry out logical breakdown, and the unit kind mainly contains: different and non-unit, XNOR unit, selected cell, AOI unit and inclusive NAND unit.And these unit substantially all are 2 input and 3 input blocks.The present invention simplifies in the standard cell lib driver element that has also designed X4, X8 and X16 for phase inverter and impact damper, its objective is in order to alleviate the anxiety of sequential.Referring to Fig. 3, higher driving for other logic functions realizes, the present invention is still in line with the principle that does not increase the unit kind as far as possible, the present invention adopts the mode that will have logic parallel connection or cascade now to realize the high logic that drives, although this many driving forces is olation can be introduced must additional delay, postpone fully within the acceptable range.Simultaneously, because special process manufacturability problem has appearred in day by day dwindling of characteristic dimension, 65 nanometer nodes, as the standard cell lib of a practicality, the design requirement of consideration front and back end that must be complete, therefore the present invention introduces multiple special element, such as delay cell, on draw/drop-down unit, filler cells, the electric capacity filler cells, substrate link and antenna effect suppress the unit, to guarantee to simplify the function that must realize in the standard cell lib.
Simplify cell library by adopting unit the least possible, that frequently need to realize complicated as far as possible logic, thereby in the performance of circuit with do compromise above the implementation complexity, reduced the number of domain graphics shape, effectively reduced the quantity of photoetching stage graphics process, be conducive to the photoetching close friend, distinguishable rate is strengthened, improved the manufacturability of circuit, guaranteed to a certain extent again the performance of circuit.
With the present invention design simplify standard cell lib and traditional standard cell lib is applied on a plurality of benchmark test circuit, comprehensively compare sequential, area and power consumption performance.The present invention finds, aspect circuit delay, the present invention's design simplify standard cell lib and complete standard cell lib gap very little, basic controlling is in 5%; Aspect circuit area, simplify standard cell lib and concentrate in this scope of 5%-10% with respect to the loss of complete standard cell lib; Aspect power consumption, simplify standard cell lib and substantially all be controlled in 5% than the loss of complete standard cell lib.So, optimization of the present invention simplify that standard cell lib has must practical value.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of making, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. a method that is optimized simplifying standard cell lib is characterized in that, described method is supported the design of 65 nanometer special process circuit manufacturability, and the method comprises:
Select to realize the elementary cell of required circuit function, this selection is to select the elementary cell that needs under the requirement that guarantees to realize required circuit function, by these elementary cells are carried out logical combination, travel through all complex logics, described elementary cell is phase inverter, impact damper, Primitive gate, combination gates unit, arithmetic element and timing unit;
In simplifying standard cell lib, increase delay cell, draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit, wherein, described delay cell, on draw/drop-down unit, filler cells, electric capacity filler cells, substrate link and antenna effect suppress the unit, be be used to the design requirement that satisfies the front and back end, guarantee to simplify the function that must realize in the standard cell lib and the functional unit that in simplifying standard cell lib, increases;
Complex unit makes up by elementary cell, and to improve the manufacturability of circuit, compared to complete standard cell lib, the area of circuit, power consumption and sequential are lost in 5%-10%;
Adopt the logical breakdown mode to select many input logics; And
Adopt the driving is olation to realize many driving forces, wherein, the mode that employing will have logic parallel connection or cascade now realizes the high logic that drives, cell delay information is according to input signal transit time and two indexs of output load and do look-up table, whether should cascade high driving ability phase inverter and impact damper, decided by the .lib file of EDA synthesis tool according to standard cell lib.
2. the method that is optimized simplifying standard cell lib according to claim 1, it is characterized in that, described employing logical breakdown mode is selected in the step of many input logics, adopt by two 2 input logics realizations for 4 input logics, perhaps adopt 13 input logic and 1 input logic to realize.
3. the method that is optimized simplifying standard cell lib according to claim 1 is characterized in that, described employing logical breakdown mode is selected in the step of many input logics, adopts by 2 input logics and 3 input logics for 5 input logics and realizes.
4. the method that is optimized simplifying standard cell lib according to claim 1, it is characterized in that described employing drives is olation and realizes in the step of many driving forces, for phase inverter and impact damper, X4, X8 and X16 have been designed separately, to alleviate the anxiety of sequential; Higher driving for other logic functions realizes that the mode that employing will have logic parallel connection or cascade now realizes the high logic that drives.
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| CN107784136B (en) * | 2016-08-24 | 2021-02-12 | 中国科学院微电子研究所 | Method and system for creating standard cell library |
| US10664565B2 (en) * | 2017-05-19 | 2020-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system of expanding set of standard cells which comprise a library |
| CN108846160B (en) * | 2018-05-03 | 2023-03-10 | 上海华虹宏力半导体制造有限公司 | Standard cell library circuit design method |
| CN112100158B (en) * | 2020-09-21 | 2022-11-22 | 海光信息技术股份有限公司 | Standard cell library establishing method and device, electronic equipment and storage medium |
| CN118278329B (en) * | 2024-06-03 | 2024-08-02 | 沐曦科技(成都)有限公司 | Method, electronic device and medium for optimizing trigger size in gate-level netlist |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101990671A (en) * | 2008-02-05 | 2011-03-23 | 纳恩盖特公司 | Optimization of integrated circuit design and library |
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Non-Patent Citations (6)
| Title |
|---|
| A design method for process design kit based on a SMIC 65 nm process;Luo Haiyan等;《Journal of Semiconductors》;20101031;第31卷(第10期);第115-120页 * |
| Luo Haiyan等.A design method for process design kit based on a SMIC 65 nm process.《Journal of Semiconductors》.2010,第31卷(第10期),第115-120页. |
| UMC 0. 18um异步电路标准单元库建库技术研究;高丽江;《微电子学》;20080630;第38卷(第3期);第349-352页，第357页 * |
| 宁涉洋.深亚微米标准单元库设计与优化.《中国优秀硕士学位论文全文数据库》.2010,第2章第2.1节. |
| 深亚微米标准单元库设计与优化;宁涉洋;《中国优秀硕士学位论文全文数据库》;20101215;第2章第2.1节 * |
| 高丽江.UMC 0. 18um异步电路标准单元库建库技术研究.《微电子学》.2008,第38卷(第3期),第349-352页，第357页. |
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