CN102270635B - Compound semiconductor device and manufacturing method thereof - Google Patents

Abstract

A compound semiconductor device and a method for manufacturing the same. The method for manufacturing the compound semiconductor device includes: providing a gallium arsenide substrate; forming a first element and a second element respectively positioned on the first part and the second part of the GaAs substrate; forming a first passivation layer on the GaAs substrate, the first device and the second device; partially removing the first protective layer on the first and second devices and on the GaAs substrate between the first and second devices; performing an etching process to form a trench in a portion of the GaAs substrate between the first and second elements using the first protective layer as an etching mask; forming electrodes on the first and second elements; and forming a second passivation layer conformally covering the first passivation layer, the electrode and the GaAs substrate exposed by the trench.

Description

Compound semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a compound semiconductor device formed by using a gallium arsenide substrate and a manufacturing method thereof, wherein components containing conductive materials have preferred electrical stress performance .

Background technique

Gallium arsenide material is one of many known compound semiconductor materials. It has high electron mobility (about six times that of traditional silicon materials), high saturation drift speed and semi-insulation, so it is suitable for the production of high-speed devices. In addition, gallium arsenide materials also have the characteristics of high output power, low power consumption, and low noise, so they are also suitable for the production of high-frequency communication components to replace known low-frequency silicon communication components and meet the needs of today's communications and local area networks. and other wireless communication applications.

Please refer to FIG. 1 , which shows a known compound semiconductor device 150 fabricated using a gallium arsenide substrate 100 . Here, for illustrative purposes, only a portion of the compound semiconductor device 150 is partially shown.

As shown in FIG. 1 , the compound semiconductor device 150 includes a circuit formed by proper arrangement of several distinct elements, similar to known silicon semiconductor devices fabricated using a silicon substrate. The components included in the compound semiconductor 150 are, for example, active components such as transistors and diodes, passive components such as resistors and capacitors, and other components such as conductive pads, all of which contain conductive materials.

For the purpose of illustration, only two adjacent elements A and B are shown in FIG. 1 , and the two elements A and B may be the same or different elements selected from the aforementioned elements, respectively.

Although the gallium arsenide substrate 100 is a semi-insulating substrate, the components A and B included in the compound semiconductor device 150 generally include a P-doped or N-doped channel layer (P-doped or N-doped Channel layer) and ohmic contact layer (ohmic contact layer) and other element film layers composed of conductive materials. Since it is in physical contact with the gallium arsenide substrate 100, during the manufacture or operation of the compound semiconductor device 150, conductive dopant impurities or metal components contained in the conductive material may be mixed into the arsenide through diffusion. In the Ga substrate 100 , an undesired interdiffusion phenomenon occurs, which causes the portions of the GaAs substrate 100 adjacent to the devices A and B to have undesired conductive properties.

In this way, if a momentary large current such as electrostatic discharge current (ESD currents) is passed from the device A and/or B, the momentary large current may flow along the surface of the gallium arsenide substrate 100 between the device A and B. The current path E1 (marked by a dotted line) spreads, thereby causing the electromigration (EM) of the adjacent elements A and B, which will cause the breakdown of the elements A and B, and make the compound semiconductor device 150 malfunction.

Therefore, in order to avoid the occurrence of the above-mentioned undesired breakdown of the device, the device A and B disposed on the GaAs substrate 100 must be separated by a pitch P1 to avoid the above-mentioned undesired electrotransition phenomenon. The pitch P1 can be determined depending on the manufacturing technology of the components A and B, and is generally 20-300 microns.

However, the pitch P1 between the devices A and B may limit the number of devices that can be disposed per unit area on the GaAs substrate 100 , which is not conducive to reducing the size of the compound semiconductor device 150 .

Please refer to FIGS. 2-5 , which respectively show schematic diagrams of known elements that may be used for the elements A and B formed on the GaAs substrate 100 in FIG. 1 .

Please refer to FIG. 2, which shows a known transistor 10, which mainly includes a channel layer 102, an ohmic contact layer 106, protective layers 110 and 116, a gate electrode 108 and a contact electrode 114 on a part of a gallium arsenide substrate 100. and other main components. Here, for the purpose of simplifying the drawings, the channel layer 102 is shown as a single film layer, which may actually include several stacked P-type and/or N-type doped and/or undoped layers. The sub-layers of gallium arsenide material. In addition, a source region, a drain region and a channel region (not shown) therebetween may be formed in a part of the channel layer 102 . The ohmic contact layer 106 can be respectively disposed on the source region and the drain region, and can include sub-layers such as a gold germanium (AuGe) layer, a nickel (Ni) layer, and a gold (Au) layer stacked together. The gate electrode 108 is disposed on a part of the channel region. The passivation layer 110 conformably covers part of the GaAs substrate 100 , the channel layer 102 , the ohmic contact layer 106 and the gate electrode 108 , and the contact electrode 114 is formed between the passivation layer 110 , the ohmic contact layer 106 and the gate electrode 108 superior. In addition, another passivation layer 116 partially covers the passivation layer 110 and the contact electrode 114 , and an opening 118 is formed in the passivation layer 116 to expose a part of the contact electrode 114 . In addition, please refer to FIG. 3 , which shows a cross-sectional situation along line 3 - 3 in FIG. 2 , which shows an implementation situation of a source region or a drain region.

Please refer to FIG. 4 and FIG. 5 , which respectively show a known capacitor 20 and a conductive pad 30 . As shown in FIGS. 4 and 5 , the capacitor 20 and the conductive pad 30 are composed of film layers similar to those of the transistor 10 shown in FIGS. 2-3 , and thus can be formed simultaneously during the fabrication process of the transistor 10 . In these drawings, the same reference numerals represent the same element film layers. The contact electrode 114 in the capacitor 20 shown in FIG. 4 serves as the top electrode, the protection layer 110 serves as the capacitor layer, and the gate electrode 108 and the ohmic contact layer 110 serve as the bottom electrode. The conductive pad 30 shown in FIG. 5 includes an ohmic contact layer 106 and a conductive electrode 114 electrically connected to the GaAs substrate 100 through the ohmic contact layer 106 .

Therefore, in order to improve the device integration of the compound semiconductor device 150 and reduce the chip size of the compound semiconductor device 150 , a novel layout design of the compound semiconductor device is required.

Contents of the invention

In view of this, the present invention provides a compound semiconductor device and a manufacturing method thereof.

According to an embodiment, the present invention provides a compound semiconductor device, comprising: a gallium arsenide substrate having a first protruding portion and a second protruding portion, wherein the first protruding portion is located on the first portion of the gallium arsenide substrate , and the second protruding portion is located on the second portion of the GaAs substrate; the first component is disposed on the first protruding portion; and the second component is disposed on the second protruding portion.

According to another embodiment, the present invention provides a method for manufacturing a compound semiconductor device, comprising: providing a gallium arsenide substrate; forming a first element and a second element respectively located at the first part and the second part of the gallium arsenide substrate portion; forming a first protection layer on the gallium arsenide substrate, the first element and the second element; partially removing the first element and the second element and the first element and the second element The first protective layer on the gallium arsenide substrate between the second elements; performing an etching process, using the first protective layer as an etching mask, and the first protective layer between the first element and the second element forming a trench in a portion of the gallium arsenide substrate; forming electrodes on the first element and the second element; and forming a second passivation layer to conformably cover the first passivation layer, the electrode, and the trench. exposed the GaAs substrate.

In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

FIG. 1 is a cross-sectional view showing a known compound semiconductor device;

Figure 2 is a cross-sectional view showing a known transistor;

Fig. 3 has shown the section situation along line segment 3-3 in Fig. 2;

Figure 4 is a cross-sectional view showing the known capacitance;

Figure 5 is a cross-sectional view showing a known conductive pad;

6 is a cross-sectional view showing a compound semiconductor device according to an embodiment of the present invention;

7 is a cross-sectional view showing a compound semiconductor device according to another embodiment of the present invention;

8 is a cross-sectional view showing a compound semiconductor device according to yet another embodiment of the present invention;

9a-9e are a series of cross-sectional views showing a method for manufacturing a compound semiconductor device according to an embodiment of the present invention;

Fig. 10 is a cross-sectional view showing a capacitor according to an embodiment of the present invention.

Explanation of reference signs

10～transistor; 20～capacitance;

30～conductive pad; 100～gallium arsenide substrate;

102～channel layer; 106～ohm contact layer;

108～gate electrode; 110, 116～protective layer;

112, 118～opening; 114～contact electrode;

150～compound semiconductor device; 200～gallium arsenide substrate;

200a, 200b～protrusion; 202～channel layer;

204～coating layer; 206～ohm contact layer;

208～gate electrode; 210, 240～protective layer;

212, 242～opening; 214～contact electrode;

246 ~ groove;

250, 250’, 250”～compound semiconductor device;

A, B, C, D, E, F, G, H～components;

P1, P2, P3, P4～the spacing between components;

E1, E2, E3, E4~ Conductive paths between components.

Detailed ways

Several embodiments of the present invention will be illustrated below in conjunction with the following and accompanying drawings such as FIGS. 6-8 , 9 a - 9 e , and 10 . In these drawings, the same reference numerals represent the same elements.

Please refer to FIG. 6 , which shows a compound semiconductor device 250 according to an embodiment of the present invention. For illustration purposes, only a part of the compound semiconductor device 250 is partially shown here.

As shown in FIG. 6 , the compound semiconductor device 250 mainly includes a GaAs substrate 200 with at least one trench 246 formed therein, thus defining a separated protrusion 200 a and a protrusion 200 b on the GaAs substrate 200 . The component C can be disposed on the protruding portion 200a, and the component D can be disposed on the protruding portion 200b. A passivation layer 240 is conformally formed on the GaAs substrate 200 , devices C and D, and the GaAs substrate 200 exposed by the trench 246 . An opening 242 is formed in the passivation layer 240 on a part of the devices C and D to partially expose a part of the devices C and D.

In an embodiment, elements C and D may be the same or different elements, which are respectively active elements such as transistors and diodes, passive elements such as resistors and capacitors, and other elements such as conductive pads, All of the above components contain conductive materials. In another embodiment, components C and D may use known components such as transistors, capacitors and conductive pads as shown in FIGS. 2-5 .

In an embodiment, the protection layer 240 includes a dielectric material such as silicon nitride, which not only serves as a dielectric layer for capacitors, but also provides protection functions such as moisture resistance and scratch resistance for each element in the compound semiconductor device 250 . In yet another embodiment, the trench 246 can be formed in the GaAs substrate 200 between the devices C and D through a patterning process, and has a depth of about 0.01-20 microns from the surface of the GaAs substrate 200 .

As shown in FIG. 6 , by setting the groove 246 in the gallium arsenide substrate 200, the distance P2 between the elements C and D can be further reduced, for example, to a distance of 2-30 microns. At this time, the distance between the elements C and D The conductive path E2 extending along the surface of the gallium arsenide substrate 200 in between is also arranged along the groove 246, so there will be several additional vertical portions perpendicular to the surface of the gallium arsenide substrate 200, so the conduction The overall length of the path E2 is not less than the known conductive path E1 shown in FIG. 1 . In this way, the compound semiconductor device 250 can reduce the distance P2 between the components C and D in it without causing electrical breakdown of the components C and/or D in it, thus helping to improve the internal performance of the compound semiconductor device 250. element integration and reduce the chip size of the compound semiconductor device 250 .

Please refer to FIG. 7, which shows a compound semiconductor device 250' according to another embodiment of the present invention. For illustrative purposes, only a portion of the compound semiconductor device 250' is partially shown.

In this embodiment, the compound semiconductor device 250' mainly includes a flat gallium arsenide substrate 200 without any trenches therein, and patterned channel layers ( channel layer) 202 and an optional cladding layer (capsulelayer) 204 located on the channel layer 202, the channel layer 202 can be the same as the channel layer 102 shown in FIGS. 2-3, and the cladding layer 204 is, for example It is a dielectric material layer of silicon nitride, which can provide protection functions such as anti-moisture and anti-scratch of the GaAs substrate 200 . In this way, the gallium arsenide substrate 200 is also defined on the surface of the gallium arsenide substrate 200. The separated first protrusions formed by the channel layer 202 and the cladding layer 204 on the surface of different parts (such as the channel located on the left side of the drawing layer 202 and cladding layer 204 ) and the second protrusion (such as composed of channel layer 202 and cladding layer 204 on the right side of the drawing). An element E may be arranged on the first protrusion, and a further element F may be arranged on the second protrusion. A protection layer 240 is formed on the gallium arsenide substrate 200, the channel layer 202, the cladding layer 204 and the elements E and F, and openings 242 are respectively formed in the protection layer 240 on a part of the elements E and F. Components E and F are partially exposed.

In this embodiment, the elements E and F can be the same or different elements, and based on the arrangement of the channel layer 202 and the cladding layer 204, the elements E and F are preferably passive elements such as resistors, capacitors, etc. other components such as conductive pads, rather than active components such as transistors, diodes, etc., so that the functions of these active components are not affected by the underlying channel layer 202 and cladding layer 204 . The components E and F can also use known components such as capacitors and conductive pads as shown in FIGS. 3-4 .

As shown in FIG. 7 , by forming a patterned channel layer 202 and a cladding layer 204 on different parts of the GaAs substrate 200 and disposing the elements E and F respectively thereon, the distance between the elements E and F can be further shortened. The pitch P3 is reduced to a distance of 2-30 microns, for example. At this time, the conductive path E3 between the elements E and F not only includes a part extending along the surface of the gallium arsenide substrate 200, but also includes a vertical ground Extending into other parts of the channel layer 202 and the cladding layer 204 , the overall length of the conductive path E3 is not less than the known conductive path E1 shown in FIG. 1 . In this way, the compound semiconductor device 250' can reduce the distance P3 between the elements E and F therein without causing electrical collapse of the elements E and/or F therein, thus helping to improve the compound semiconductor device 250' 'Integration of elements within' and reducing the chip size of the compound semiconductor device 250'.

Please refer to FIG. 8 , which shows a compound semiconductor device 250 ″ according to yet another embodiment of the present invention. For the purpose of illustration, only a part of the compound semiconductor device 250 ″ is partially shown here.

As shown in FIG. 8, the compound semiconductor device 250" mainly includes a gallium arsenide substrate 200, in which at least one groove 246 is formed, thus defining a separated first protrusion 200a and a second protrusion 200a on the gallium arsenide substrate 200. Two protruding portions 200b. In addition, as in the previous embodiment shown in FIG. Layer 204. Element G can be disposed on the first protruding portion 200a, and element H can be disposed on the channel layer 202 and cladding layer 204 on the second protruding portion 200b. On the gallium arsenide substrate 200, the element A protective layer 240 is conformally formed on the G and H, the channel layer 202, the cladding layer 204, and the GaAs substrate 200 exposed by the trench 246. In the protective layer 240 on a part of the devices G and H, Openings 242 are formed to partially expose the elements G and H.

In the embodiment, the elements G and H can be the same or different elements, but based on the arrangement of the channel layer 202 and the cladding layer 204, the element H can be passive elements such as resistors and capacitors and conductive pads other components instead of active components such as transistors, diodes, etc., so that the performance of component H is not affected by its lower channel layer 202 and cladding layer 204, and component G can be active components such as transistors, diodes, etc. Source components, passive components such as resistors, capacitors, etc., and other components such as conductive pads. Components G and H can use known components such as transistors, capacitors and conductive pads as shown in FIGS. 1-5 .

As shown in FIG. 8, through the arrangement of the trench 246 in the gallium arsenide substrate 200 and the arrangement of the channel layer 202 and the cladding layer 204 patterned on the second protruding portion 200b, the distance between the elements G and H can be made The pitch P4 is further reduced, for example, to a distance of 2-30 microns, and at this time, the conductive path E4 extending along the surface of the gallium arsenide substrate 200 located between the elements G and H is along the groove 246. Therefore, there are several additional vertical portions perpendicular to the surface of the GaAs substrate 200 . In addition, the conductive path E4 also includes other parts vertically extending in the channel layer 202 and the cladding layer 204 , so the overall length of the conductive path E4 is not less than the known conductive path E1 shown in FIG. 1 . In this way, the compound semiconductor device 250" can reduce the pitch P3 between the elements G and H therein without causing electrical breakdown of the elements G and/or H therein, thus helping to improve the compound semiconductor device 250. Integrating elements within "and reducing the chip size of the compound semiconductor device 250".

Please continue to refer to FIGS. 9a-9e to illustrate the manufacturing method of the compound semiconductor device according to the embodiment of the present invention.

Referring to FIG. 9 a , firstly, a GaAs wafer is provided, such as a commercial GaAs wafer, which includes a GaAs substrate 200 and a channel layer 202 and a cladding layer 204 thereon. Here, the channel layer 202 is shown as a single film layer, but it may actually include several P-type and/or N-type doped and/or undoped gallium arsenide materials that are stacked. Sub-layers (sub-layers). As mentioned above, the cladding layer 204 is a dielectric material layer such as silicon nitride, which has an extremely thin thickness of about 100˜2000 angstroms.

Referring to FIG. 9b, a patterning process (not shown) is then performed, such as known photolithography and etching processes, to leave a patterned channel layer 202 on a part of the gallium arsenide substrate 200 and on another The patterned channel layer 202 and the cladding layer 204 thereon are left on the top.

Referring to FIG. 9 c , a source region, a drain region and a channel region (not shown) therebetween are formed in the channel layer 202 by using a conventional silicon semiconductor process. Then, the ohmic contact layer 206 is deposited on the gallium arsenide substrate 200 to form a patterning process (not shown), such as a known photolithography and etching process, to form a source region in the channel layer 202. A patterned ohmic contact layer 206 is formed on the drain region and on the cladding layer 204 respectively. In the embodiment, the ohmic contact layer 206 is a composite film layer, which includes gold germanium (AuGe) layer, nickel (Ni) layer, gold (Au) layer and other sub-film layers stacked from bottom to top. Next, a conductive material 208 is deposited on the gallium arsenide substrate 200 to form a patterning process (not shown), such as a known photolithography and etching process, to form a channel region in the channel layer 202. A patterned gate electrode 208 is formed on a portion. In an embodiment, the gate electrode 208 may include conductive materials such as titanium (Ti), gold (Au), platinum (Pt).

As shown in FIG. 9 c , an element G such as a transistor is fabricated on a part of the GaAs substrate 202 , and another element H is fabricated on another part of the GaAs substrate 202 . Next, a protection layer 210 is formed on the GaAs substrate 200, which conformably covers the GaAs substrate 200, the channel layer 202 in the device G and the device H, the cladding layer 204, the ohmic contact layer 206, and the gate electrode. 208 and other exposed surfaces of the element film layer. In an embodiment, the passivation layer 210 may include a dielectric material such as silicon nitride and have a thickness ranging from 100 angstroms to 2000 angstroms.

Referring to FIG. 9d, a part of the protective layer 210 on the part of the GaAs substrate 200 located on the element G and the element H, on the gate electrode 208, and on the part of the GaAs substrate 200 between the element G and the element H is partially removed to be in the An opening 212 is formed. In an embodiment, a patterning process (not shown), such as known photolithography and etching procedures, is first performed to simultaneously remove the GaAs substrate on the devices G and H and between the devices G and H A part of the passivation layer 210 is used to expose a part of the device G and a part of the device H and a part of the GaAs substrate 200 between the device G and the device H, respectively. In another embodiment, a first patterning process (not shown) is first performed to remove a part of the passivation layer 210 on the devices G and H to respectively expose parts of the devices G and H and perform a second patterning process. A patterning process (not shown) to then remove a portion of the passivation layer 210 on the GaAs substrate 200 between the devices G and H to expose a portion of the GaAs substrate 200 between the devices G and H. Then an etching process (not shown) is performed, using the protective layer 210, the ohmic contact layer 206 and the gate electrode 208 as an etching mask to form a trench in a part of the GaAs substrate 200 exposed by the opening 212 between the elements G and H Slot 246.

Please refer to FIG. 9e, and then form a conductive material on the gallium arsenide substrate 200 and perform a patterning process (not shown) to form a contact electrode 214 on the gate electrode 208 and the ohmic electrode 214 in the elements G and H respectively. over the contact layer 206 . Then another passivation layer 240 is formed, which conformably covers the passivation layer 210 on the GaAs substrate 200 , the contact electrode 214 and the surface of the GaAs substrate 200 exposed by the groove 246 . A patterning process (not shown) is then performed to partially remove a part of the passivation layer 240 in the devices G and H and expose a part of the inner contact electrode 214 .

As shown in FIG. 9e, the process so far has produced a semiconductor device similar to the compound semiconductor device 250" shown in FIG. Restricted by the above implementation situation, the element H can also be replaced by a capacitor as shown in Figure 10. In addition, in other embodiments, the process shown in Figures 9a-9e can be referred to and the process of forming the trench 246 therein can be omitted. Alternatively, the same process as that of the device H is used at the device G to manufacture the compound semiconductor devices 250 and 250 ′ as shown in FIGS. 6-7 .

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be defined by the claims.

Claims (8)

1. the manufacture method of a compound semi-conductor device comprises:

The GaAs substrate is provided;

Form the first element and the second element, lay respectively on the First of this GaAs substrate and second one;

Form the first protective layer on this GaAs substrate, this first element and this second element;

Part removes on this first element and this second element and this first protective layer on this GaAs substrate between this first element and this second element;

Implement etching program, take this first protective layer as etching mask, form groove in the part of this GaAs substrate between this first element and this second element;

Form electrode on this first element and this second element; And

Form the second protective layer, this GaAs substrate that conformably covers this first protective layer, this electrode and expose for this groove.

2. the manufacture method of compound semi-conductor device as claimed in claim 1, wherein part remove on this first element and this second element and this first protective layer on this GaAs substrate between this first element and this second element comprise:

Implement Patternized technique; remove simultaneously on this first element and this second element and the part of this first protective layer on this GaAs substrate between this first element and this second element, with a part of exposing respectively this first element and this second element and this part of this GaAs substrate between this first element and this second element.

3. the manufacture method of compound semi-conductor device as claimed in claim 1, wherein part remove on this first element and this second element and this first protective layer on this GaAs substrate between this first element and this second element comprise:

Implement the first Patternized technique, to remove a part that is positioned at this first protective layer on this first element and this second element, expose respectively the part of this first element and this second element; And

Implement the second Patternized technique, to remove the part of this first protective layer on this GaAs substrate between this first element and this second element.

4. the manufacture method of compound semi-conductor device as claimed in claim 1 wherein before forming this first element and this second element, comprises that also the formation channel layer is on this First of this GaAs substrate and this second one.

5. the manufacture method of compound semi-conductor device as claimed in claim 4, also comprise forming coating layer on this channel layer.

6. the manufacture method of compound semi-conductor device as claimed in claim 1, wherein this first element is the identical or distinct elements that comprises conductive structure with this second element.

7. the manufacture method of compound semi-conductor device as claimed in claim 1, wherein this first element and this second element are transistor, electric capacity, resistance or conductive connection pads.

8. the manufacture method of compound semi-conductor device as claimed in claim 1, wherein have the spacing between 2～30 microns between this first element and this second element.

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