CN102263125B - Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides - Google Patents
Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides Download PDFInfo
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- CN102263125B CN102263125B CN2011102434548A CN201110243454A CN102263125B CN 102263125 B CN102263125 B CN 102263125B CN 2011102434548 A CN2011102434548 A CN 2011102434548A CN 201110243454 A CN201110243454 A CN 201110243454A CN 102263125 B CN102263125 B CN 102263125B
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 20
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title description 10
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开一种横向扩散金属氧化物功率MOS器件，包括：位于P型的衬底层内的P型阱层和N型轻掺杂层；所述N型轻掺杂层由第一N型轻掺杂区、第二N型轻掺杂区和P型轻掺杂区组成；所述第一N型轻掺杂区的掺杂浓度高于所述P型轻掺杂区的掺杂浓度，所述P型轻掺杂区的掺杂浓度高于所述第二N型轻掺杂区的掺杂浓度；所述第一N型轻掺杂区位于所述第二N型轻掺杂区上方；所述P型轻掺杂区在水平方向上位于所述第一N型轻掺杂区的中央区域且此P型轻掺杂区在垂直方向上位于所述第一N型轻掺杂区中央区域的中下部并与所述第二N型轻掺杂区表面接触。本发明功率MOS器件提高了击穿电压并降低了器件比导通电阻，同时大大改善了器件的响应时间和频率特性。
The invention discloses a laterally diffused metal oxide power MOS device, comprising: a P-type well layer and an N-type lightly doped layer located in a P-type substrate layer; the N-type lightly doped layer is composed of a first N-type lightly doped layer doped region, a second N-type lightly doped region and a P-type lightly doped region; the doping concentration of the first N-type lightly doped region is higher than the doping concentration of the P-type lightly doped region, The doping concentration of the P-type lightly doped region is higher than the doping concentration of the second N-type lightly doped region; the first N-type lightly doped region is located in the second N-type lightly doped region above; the P-type lightly doped region is located in the central region of the first N-type lightly doped region in the horizontal direction and the P-type lightly doped region is located in the vertical direction of the first N-type lightly doped region The middle and lower part of the central region of the region is in contact with the surface of the second N-type lightly doped region. The power MOS device of the invention improves the breakdown voltage and reduces the specific on-resistance of the device, and at the same time greatly improves the response time and frequency characteristics of the device.
Description
Technical field
The present invention relates to a kind of MOS device, be specifically related to a kind of lateral diffused metal oxide power MOS (Metal Oxide Semiconductor) device.
Background technology
Lateral diffused metal oxide power MOS (Metal Oxide Semiconductor) device (LDMOS); Along with the fast development of semicon industry, the power electronic technology take large power semiconductor device as representative develops rapidly, and application constantly enlarges, such as the control of alternating current machine, printer driver circuit.In various power devices now, LDMOS has the operating voltage height, and technique is relatively simple, so LDMOS has vast potential for future development.In the LDMOS designs, puncture voltage and conducting resistance always are the main target of paying close attention to when people design such devices, and the length of the thickness of epitaxial loayer, doping content, drift region is the most important parameter of LDMOS.The length that can pass through to increase the drift region is with the raising puncture voltage, but this can increase chip area and conducting resistance.Withstand voltage and conducting resistance is contradiction for the concentration of epitaxial loayer and the requirement of thickness.High puncture voltage requires thick light dope epitaxial loayer and long drift region, low conducting resistance then requires thin heavy doping epitaxial loayer and short drift region, therefore must select best extension parameter and drift region length, so that under the prerequisite that satisfies certain source drain breakdown voltage, obtain minimum conducting resistance.RESURF (RESURF principle) is widely used in the design of high tension apparatus always, and this principle requires drift region charge and substrate electric charge to reach charge balance, can bear when accomplishing that the drift region exhausts fully higher withstand voltage.
Although Single RESURF structure can satisfy certain puncture voltage requirement, owing to the concentration low conducting resistance that causes in drift region is larger.Cause part depletion if the drift region implantation dosage is excessive, then the described P type trap layer of close channel region and the knot internal electric field between the N-type lightly-doped layer reach in advance the critical electric field of silicon materials and puncture, and cause puncture voltage to reduce; Occur exhausting fully and having simultaneously the part drain region also depleted if the drift region implantation dosage is crossed low, then puncture too early near the drain region of drain terminal and the knot between the N-type lightly-doped layer, puncture voltage is reduced.Prior art is reported in N-type lightly-doped layer surface and injects P type light doping section, thereby improves the surface electric field distribution of drift region, although this design can improve puncture voltage, is unfavorable for reducing the design of device conduction resistance; Thereby and can cause electric field inhomogeneous and mutually exhaust the cut-off frequency that causes reducing the LDMOS device.
Summary of the invention
The invention provides a kind of lateral diffused metal oxide power MOS (Metal Oxide Semiconductor) device, this power MOS (Metal Oxide Semiconductor) device has improved puncture voltage and has reduced the device conduction resistance, has greatly improved response time and the frequency characteristic of device simultaneously.
For achieving the above object, the technical solution used in the present invention is: a kind of lateral diffused metal oxide power MOS (Metal Oxide Semiconductor) device, comprise: the P type trap layer and the N-type lightly-doped layer that are positioned at the substrate layer of P type, consist of a PN junction thereby described P type trap layer and N-type lightly-doped layer are adjacent in the horizontal direction, the one source pole district is positioned at described P type trap floor, one drain region is positioned at described substrate layer, be provided with grid oxide layer above the P type trap layer in zone between described source area and the N-type lightly-doped layer, this grid oxide layer top is provided with the described N-type lightly-doped layer of a gate regions by the first N-type light doping section, the second N-type light doping section and P type light doping section form; The doping content of described the first N-type light doping section is higher than the doping content of described P type light doping section, and the doping content of described P type light doping section is higher than the doping content of described the second N-type light doping section;
The doping content proportion of described the first N-type light doping section and the second N-type light doping section is: 1.2: 1～1.3: 1;
Described the first N-type light doping section is positioned at described the second N-type light doping section top; Described P type light doping section be positioned in the horizontal direction the middle section of described the first N-type light doping section and middle and lower part that this P type light doping section is positioned at described the first N-type light doping section middle section in vertical direction and with described the second N-type light doping section Surface Contact.
As preferably, the doping content ratio of described the first N-type light doping section and P type light doping section is: 1.1: 1.
As preferably, the junction depth ratio of described P type trap layer and N-type lightly-doped layer is 2: 1.
As preferably, described drain region is positioned at described N-type lightly-doped layer.
As preferably, described N-type lightly-doped layer is between described drain region and described P type trap layer.
Because technique scheme is used, the present invention compared with prior art has following advantages and effect:
1, P type light doping section of the present invention is positioned in vertical direction the middle and lower part of described the first N-type light doping section middle section and contacts with described the second N-type light doping section, reduced gate leakage capacitance Cgd through emulation testing, cut-off frequency has improved about 8%, form two current branch, further reduced conduction resistance.
2, the doping content of the first N-type light doping section of the present invention, P type light doping section and the second N-type light doping section reduces successively, and the junction depth ratio of P type trap layer and N-type lightly-doped layer is 2: 1, the vertical direction depletion region and the horizontal direction depletion region that are conducive to substrate layer intercouple, thereby are convenient to the puncture voltage of device and the parameter designing of conduction resistance.
3, the first N-type light doping section of P type light doping section of the present invention both sides is different with the second N-type light doping section doping content separately, and the interface between the first N-type light doping section and the second N-type light doping section is positioned at P type light doping section below; Be conducive to form in P type light doping section both sides the depletion layer of vertical direction, can further improve the high voltage performance of device.
When 4, the present invention keeps high-breakdown-voltage, thereby the concentration that further improves the N-type lightly-doped layer has reduced the whole conduction resistance of device and the switching loss of device, and P type light doping section more is tending towards planarization to the electric field of its N-type lightly-doped layer internal modulation, effectively reduces the electric field strength between P type trap layer and the N-type lightly-doped layer.Description of drawings
Accompanying drawing 2 concerns schematic diagram for puncture voltage of the present invention with than on-state rate and doping content;
Accompanying drawing 3 is for puncture voltage of the present invention with than on-state rate and doping content proportionate relationship schematic diagram;
Accompanying drawing 4 is capacitance characteristic schematic diagram of the present invention.
In the above accompanying drawing: 1, substrate layer; 2, P type trap layer; 3, N-type lightly-doped layer; 4, source area; 5, drain region; 6, P type light doping section; 7, grid oxide layer; 8, gate regions; 9, the first N-type light doping section; 10, the second N-type light doping section.
Embodiment
The invention will be further described below in conjunction with drawings and Examples:
Embodiment: a kind of lateral diffused metal oxide power MOS (Metal Oxide Semiconductor) device, comprise: the P type trap layer 2 and the N-type lightly-doped layer 3 that are positioned at the substrate layer 1 of P type, consist of a PN junction thereby described P type trap layer 2 and N-type lightly-doped layer 3 are adjacent in the horizontal direction, one source pole district 4 is positioned at described P type trap floor 2, one drain region 5 is positioned at described substrate layer 1, be provided with grid oxide layer 7 above the P type trap layer 2 in zone between described source area 4 and the N-type lightly-doped layer 3, these grid oxide layer 7 tops are provided with a gate regions 8; Described N-type lightly-doped layer 3 is comprised of the first N-type light doping section 9, the second N-type light doping section 10 and P type light doping section 6; The doping content of described the first N-type light doping section 9 is higher than the doping content of described P type light doping section 6, and the doping content of described P type light doping section 6 is higher than the doping content of described the second N-type light doping section 10;
The doping content proportion of above-mentioned the first N-type light doping section 9 and the second N-type light doping section 10 is: 1.2: 1～1.3: 1;
Above-mentioned the first N-type light doping section 9 is positioned at described the second N-type light doping section 10 tops; Described P type light doping section 6 is positioned at the middle section of described the first N-type light doping section 9 in the horizontal direction, and described P type light doping section 6 is positioned in vertical direction the middle and lower part of described the first N-type light doping section 9 middle sections and contacts with described the second N-type light doping section 10.
Above-mentioned the first N-type light doping section 9 with the doping content ratio of P type light doping section 6 is: 1.1: 1.
The junction depth ratio of above-mentioned P type trap layer 2 and N-type lightly-doped layer 3 is 2: 1.
Above-mentioned drain region 5 is positioned at described N-type lightly-doped layer 3.
Above-mentioned N-type lightly-doped layer 3 is between described drain region 5 and described P type trap layer 2.
When adopting above-mentioned a kind of lateral diffused metal oxide power MOS (Metal Oxide Semiconductor) device, P type light doping section is positioned in vertical direction the middle and lower part of described the first N-type light doping section middle section and contacts with described the second N-type light doping section, reduced Cgd electric capacity through emulation testing, cut-off frequency has improved about 8%, forms two current branch and has further reduced conduction resistance; Secondly, the doping content of described the first N-type light doping section, P type light doping section and the second N-type light doping section reduces successively, and the junction depth ratio of P type trap layer and N-type lightly-doped layer is 2: 1, the vertical direction depletion region and the horizontal direction depletion region that are conducive to substrate layer intercouple, thereby are convenient to the puncture voltage of device and the parameter designing of conduction resistance.
The first N-type light doping section of described P type light doping section both sides is different with the second N-type light doping section doping content separately, and the interface between the first N-type light doping section and the second N-type light doping section is positioned at P type light doping section below; Be conducive to form in P type light doping section both sides the depletion layer of vertical direction, can further improve the high voltage performance of device; Again, when the present invention keeps high-breakdown-voltage, thereby the concentration that further improves the N-type lightly-doped layer has reduced the whole conduction resistance of device and the switching loss of device, and P type light doping section more is tending towards planarization to the electric field of its N-type lightly-doped layer internal modulation, effectively reduces the electric field strength between P type trap layer and the N-type lightly-doped layer.
Above-described embodiment only is explanation technical conceive of the present invention and characteristics, and its purpose is to allow the personage who is familiar with technique can understand content of the present invention and according to this enforcement, can not limit protection scope of the present invention with this.All equivalences that Spirit Essence is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
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| CN2011102434548A CN102263125B (en) | 2011-08-24 | 2011-08-24 | Power MOS (metal oxide semiconductor) component for transversely diffusing metallic oxides |
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| CN102263125B true CN102263125B (en) | 2013-04-03 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569404B (en) * | 2012-01-18 | 2014-11-26 | 苏州市职业大学 | Transverse diffusion metal oxide semiconductor (MOS) device with low on-resistance |
| CN103367431B (en) * | 2012-03-31 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Ldmos transistor and manufacture method thereof |
| CN103280455B (en) * | 2013-04-28 | 2016-05-18 | 苏州市职业大学 | Horizontal proliferation type low on-resistance MOS device |
| CN104752499A (en) * | 2013-12-25 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and technological method |
| CN103928529B (en) * | 2014-04-30 | 2016-11-23 | 西安电子科技大学 | 4H-SiC metal-semiconductor field effect transistor |
| CN107302025B (en) * | 2017-07-27 | 2019-11-01 | 电子科技大学 | A kind of VDMOS device with anti-single particle effect |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101099242A (en) * | 2005-01-06 | 2008-01-02 | 英飞凌科技股份公司 | LDMOS transistor |
| CN101414630A (en) * | 2007-10-15 | 2009-04-22 | 天钰科技股份有限公司 | laterally diffused metal oxide transistor |
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | A method for fabricating SOI superjunction LDMOS with linear buffer layer |
| US7868378B1 (en) * | 2005-07-18 | 2011-01-11 | Volterra Semiconductor Corporation | Methods and apparatus for LDMOS transistors |
| CN201936885U (en) * | 2011-01-14 | 2011-08-17 | 苏州英诺迅科技有限公司 | RF transverse diffusion P-type MOS tube |
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- 2011-08-24 CN CN2011102434548A patent/CN102263125B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101099242A (en) * | 2005-01-06 | 2008-01-02 | 英飞凌科技股份公司 | LDMOS transistor |
| US7868378B1 (en) * | 2005-07-18 | 2011-01-11 | Volterra Semiconductor Corporation | Methods and apparatus for LDMOS transistors |
| CN101414630A (en) * | 2007-10-15 | 2009-04-22 | 天钰科技股份有限公司 | laterally diffused metal oxide transistor |
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | A method for fabricating SOI superjunction LDMOS with linear buffer layer |
| CN201936885U (en) * | 2011-01-14 | 2011-08-17 | 苏州英诺迅科技有限公司 | RF transverse diffusion P-type MOS tube |
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